JPH07240090A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To check characteristics of a bit unit of an input/output buffer at the time of a test and to make optimization of a process easy by controlling an input/output buffer independently of respective bits, when data is read out and written in. CONSTITUTION:A data input signal is applied to a first gate 2. This first gate is controlled by logical conditions of a writing control signal and a bit unit control signal, the data input signal is selectively transmitted to a next stage latch circuit 4. The input signal latched by the latch circuit 4 is selectively outputted through a second gate 3 controlled by the bit unit control signal. Thereby, write-in and read-out are performed independently of each bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to controlling an input / output buffer suitable for independently inputting / outputting data of a memory cell bit by bit when an image memory or a memory test circuit is constructed. Regarding

[0002]

2. Description of the Related Art In recent years, the number of semiconductor memory devices has been increasing from 4 bits to 8 bits and 16 bits.

FIG. 6 is a block diagram showing a first example of such a conventional semiconductor memory device, and particularly illustrates the configuration of an 8-bit general-purpose SRAM.

As shown in FIG. 1, a row address buffer 12, a row address register 13 and a row address decoder 14 are connected to a memory cell array 11 for storing data, and a row address is designated. The row address buffer 12 has addresses A4-A.
7, A12-A16 are given to input the row address.

On the other hand, in the memory cell array 11, a column address buffer 17, a column address register 18,
A column address decoder 19 is connected and specifies a column address. Addresses A0-A3 and A8-A11 are given to the column address buffer 17 to input the column address.

A sense amplifier 20 is provided between the memory cell array 11 and the column address decoder 19 to input / output data. The data read from the memory cell array 11 is read through the data output buffer 21 and is output to the outside as input / output data I / O1-I / O8.

On the other hand, the data to be written in the memory cell array 11 is written in the memory cell array 11 as the input / output data I / O1-I / O8 from the data control 15 through the sense amplifier 20.

A clock generator 16 is connected to the row address buffer 12 and the column address buffer 17, and controls the input / output timing of data.
The clock generated by the clock generator 16 is supplied to the sense amplifier 20.

Output enable / OE, read / write control signal R / W, chip enable / CE1 and / CE2 are given from the outside as control signals.

The chip enable / CE2 is a logic circuit 22.
Are input to the logic circuit 23 together with the chip enable / CE1. As a result, the chip enable CE is obtained as the output of the logic circuit 23. The chip enable CE includes a row address buffer 12, a row address register 13, a row address decoder 14, a column address buffer 17, a column address register 18,
It is applied to the column address decoder 19.

Logic circuit 24 generates a signal for controlling data control 15 based on output enable / OE, read / write control signal R / W and chip enable CE.

The logic circuit 25 generates a signal for controlling the data output buffer 21 based on the output enable / OE, the read / write control signal R / W, and the chip enable CE.

A high potential power supply VDD and a ground potential GND are supplied to the entire chip constituting the semiconductor memory device.

The operation of the above-described structure will be described below.

The row address and column address of the memory cell array 11 are designated based on the addresses A0-A16. Data access to the specified address is 8
It is performed as bit input / output data I / O1-I / O8. Data writing to the memory cell array 11 is performed from the data control 15 via the sense amplifier 20, and data reading from the memory cell array 11 is performed from the sense amplifier 20 to the data output buffer 2.
It is done through 1.

That is, at the time of data writing operation to the memory cell array 11, the input / output data I / O is made through the data control 15 connected to the sense amplifier 20.
1-The data input to I / O8 is the memory cell array 1
Written to 1. On the other hand, during a data read operation from the memory cell array 11, the data output buffer 21 connected to the sense amplifier 20 operates and the read data is output to the input / output data I / O1-I / O8.

That is, the data write operation and the data read operation are performed in completely different modes.

FIG. 7 is a block diagram showing a second example of a conventional semiconductor memory device, particularly a 16-bit general-purpose SRA.
3 illustrates an example of the configuration of M.

As shown in the figure, a row address buffer 12 and a row address decoder 14 are connected to a memory cell array 11 for storing data, and a row address is designated. Addresses A3 to A10 are given to the row address buffer 12 to input a row address.

On the other hand, a column address buffer 17 and a column address decoder 19 are connected to the memory cell array 11 to specify a column address. The column address buffer 17 has addresses A0-A2 and A11.
-A15 is given and the column address is input.

A sense amplifier 20 is provided between the memory cell array 11 and the column address decoder 19 to input / output data. The data read from the memory cell array 11 is the data output buffers 211, 21.
I / O1-I / O
16 is derived to the outside.

On the other hand, the data to be written in the memory cell array 11 is written in the memory cell array 11 as the input / output data I / O1-I / O16 from the data input buffers 311 and 312 through the sense amplifier 20.

A clock generator 16 is connected to the row address buffer 12 and the column address buffer 17, and controls the data input / output timing.
The clock generated by the clock generator 16 is supplied to the sense amplifier 20.

Output enable / OE, write enable / WE, upper byte / U as control signals from the outside
B, lower byte / LB, and chip enable / CE are given.

The chip enable / CE is inverted through the logic circuit 26 and becomes the chip enable CE. The chip enable CE is given to the row address decoder 14 and the column address decoder 19.

The logic circuit 27 is write enable / WE,
A control signal based on the upper byte / UB, the lower byte / LB, and the chip enable / CE is generated and given to the data output buffer 211.

The logic circuit 28 is write enable / WE,
A control signal based on the upper byte / UB, the lower byte / LB, and the chip enable / CE is generated and given to the data output buffer 212.

The logic circuit 29 is write enable / WE,
A control signal based on the lower byte / LB and chip enable / CE is generated and applied to the data input buffer 311.

The logic circuit 30 has write enable / WE,
The data input buffer 312 is generated by generating a control signal based on the upper byte / UB and chip enable / CE.
Give to.

The high potential power supply VDD and the ground potential GND are supplied to the entire chip constituting the semiconductor memory device.

Next, the operation of the above-described structure will be described.

In the configuration as described above, the memory cell array 1 designated based on the addresses A0-A15.
I / O data I is assigned to the row address and column address of 1.
16-bit data is written or read through / O1-I / O16.

That is, during the data write operation to the memory cell array 11, the data input to the input / output data I / O1-I / O16 through the data input buffers 311 and 312 connected to the sense amplifier 20 is stored in the memory. It is written in the cell array 11.

On the other hand, during the operation of reading data from the memory cell array 11, the data output buffers 211 and 212 connected to the sense amplifier 20 operate,
The read data is output to the input / output data I / O1-I / O16.

The data output buffer 211 and the data output buffer 212 can be operated completely independently by the upper byte / UB and the lower byte / LB. Similarly, the data input buffer 311 and the data input buffer 312 can be similarly operated. Can be operated completely independently.

That is, the data output buffer 21
1. The input / output data I / O1-I / O8 connected to the data input buffer 311 and the data output buffer 212, and the input / output data I / O9-I / O16 connected to the data input buffer 312 can be written or read independently. it can.

As described above, in the configuration of FIG. 7, the data width can be controlled by the upper byte / UB and the lower byte / LB, and the reading / writing of the memory cell array 11 can be performed for every 8 bits (1 byte). .

FIG. 8 is a block diagram showing a third example of a conventional semiconductor memory device, and particularly illustrates the configuration of a 4-bit multiport DRAM.

As shown in the figure, a row address buffer 12 and a row address decoder 14 are connected to a memory cell array 11 for storing data, and a row address is designated. Addresses A0 to A8 are given to the row address buffer 12 to input a row address.

On the other hand, a column address buffer 17 and a column address decoder 19 are connected to the memory cell array 11 to specify a column address. Addresses A0 to A8 are given to the column address buffer 17, and the column address is input.

An I / O gate 31 and a sense amplifier 2 are provided between the memory cell array 11 and the column address decoder 19.
0 is provided to input / output data.

The data read from the memory cell array 11 is read through the I / O gate 31, and is output to the outside as the input / output data W1 / IO1-W4 / IO4 from the write per bit controller 39 through the data input / output buffer 38. To be done.

On the other hand, the data to be written in the memory cell array 11 is the input / output data W1 / IO1-W4 / IO4.
The data is supplied to the I / O gate 31 through the write per bit control unit 39 and written into the memory cell array 11 through the column address decoder 19.

In writing data through the data input / output buffer 38, the write per-bit control unit 39 can mask any data of 4-bit data by the mask data MD. You can control.

On the other hand, a serial register 33 is connected to the memory cell array 11 via a transfer gate 32.
This is for reading / writing serial data in the memory cell array 11.

Serial input / output data SIO1-SIO4
Are input and output through the serial input / output buffer 37, and these data are selected by the serial data selector 34. The serial data selector 34 is controlled by the serial address pointer 35.

When writing serial data,
Serial input / output data S of the serial input / output buffer 37
Necessary data in IO1-SIO4 is selected by the serial data selector 34 by designation from the serial address pointer 35, taken into the serial register 33, and this is transferred through the transfer gate 32 to the memory cell array 1
Write to 1.

On the other hand, in the case of reading serial data,
The data read from the memory cell array 11 through the transfer gate 32 is stored in the serial register 33, and as the data selected by the serial address pointer 35, the serial input / output data is transferred from the serial register 33 through the serial data selector 34 to the serial input / output buffer 37. It is derived as SIO1-SIO4.

The refresh counter 36 controls the row address buffer 12 to control the row address given to the row address decoder 14. As a result, the memory cell array 11 can perform multiport operation.

The operation of the configuration described above will be described below.

Reading / writing of parallel data is performed by I
/ O gate 31.

First, the data to be written in the memory cell array 11 is the input / output data W1 / IO1-W4 / IO4.
To the data input / output buffer 38. This data is given to the I / O gate 31 through the write per bit control section 39 and written into the memory cell array 11 through the column address decoder 19.

On the other hand, the read data from the memory cell array 11 is read through the I / O gate 31, and the write per bit control section 39 outputs the data input / output buffer 38.
Through I / O data W1 / IO1-W4 / IO4.

When writing the parallel data, the write per bit control unit 39 can perform a mask in bit units, that is, a write bit can be selected based on the mask data MD.

Reading / writing of serial data is performed through the transfer gate 32.

First, the data to be written in the memory cell array 11 is the serial input / output data SIO1-SIO4.
Is input and output through the serial input / output buffer 37. These data are stored in the serial address pointer 35.
It is selected by the serial data selector 34 controlled by. The selected data is taken into the serial register 33, which is written in the memory cell array 11 through the transfer gate 32.

On the other hand, the data to be read from the memory cell array 11 is read to the serial register 33 via the transfer gate 32, and as the data selected by the serial address pointer 35, serial input / output from the serial register 33 through the serial data selector 34. Serial input / output data SIO1-SI is stored in the buffer 37.
It is derived as O4.

The serial access can be performed simultaneously with the parallel access by controlling the row address buffer 12 by the refresh counter 36, and a multiport operation can be performed.

[0059]

Since the conventional semiconductor memory device is configured as described above, there are problems listed below.

First, in the case of the first conventional example, since all bits of data are read / written at the same time, there is a problem that reading / writing cannot be performed for each arbitrary bit.

Next, in the case of the second conventional example, 1 byte (8
You can control read / write in bit units,
In each byte, reading / writing is performed in units of 8 bits, and thus reading / writing cannot be performed in arbitrary bits.

Further, in the case of the third embodiment, it is possible to write in bit units, but there is a problem that there is no bit selection function until reading.

As described above, in any of the above-mentioned conventional examples, it is becoming difficult to access in a bit unit as the number of bits is increased. Therefore, it has become difficult to optimize the output buffer due to the increase in the number of bits. That is, at the time of noise evaluation, for example, in the case of the first and second conventional examples, since the input / output buffer circuits operate simultaneously, the individual characteristics of each output buffer cannot be seen. Also in the case of the third conventional example, it is not possible to judge individual characteristics of the output buffer.

That is, in the case of the conventional semiconductor memory device, it is difficult to optimize the output buffer.

The present invention solves the problems of the prior art as described above, and when reading / writing data, by controlling the input / output buffer independently for each bit, data in bit units can be read to the output buffer. The present invention provides a semiconductor memory device capable of writing data in bit units to an input buffer and realizing optimization of an output buffer.

[0066]

In order to achieve the above object, the present invention provides a semiconductor memory device having a plurality of memory cells and capable of simultaneously inputting a plurality of bits of data, and for writing / reading each bit. A control means for controlling the operation of the buffer so that writing / reading can be independently performed for each bit is provided, and the control means is controlled by a logical condition of a write control signal and a bit unit control signal and added. A first gate that selectively outputs a data input signal, a latch circuit that latches the data input signal that has passed through the first gate, and the data that is controlled by the bit unit control signal and that is latched by the latch circuit And a second gate for selectively outputting an input signal, the present invention provides a semiconductor memory device.

[0067]

The data input signal is applied to the first gate.
The first gate is controlled by the logical condition of the write control signal and the bit unit control signal, and selectively transmits the data input signal to the latch circuit of the next stage. The input signal latched by the latch circuit is selectively output via the second gate controlled by the bit unit control signal.
As a result, writing / reading is independently performed for each bit.

[0068]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention, and particularly illustrates the configuration of an input / output buffer (I / O buffer).

As shown in the figure, the data input signals DI and / DI which are the input data to the memory cell and the data output signal D which is the output data from the memory cell.
O and / DO are externally input / output through the data input / output terminal 6.

To access the memory cell, the data setup mode (first mode) for setting the bit to be selected first and the memory cell
Normal mode such as normal write for writing all bits of data input to the data input / output terminal 6 and normal read for outputting all bits of data read from the memory cell to the data input / output terminal 6 (second mode) And write only the preset bits of the data input to the data input / output terminal 6 to the memory cell, and write only the preset bits of the data read from the memory cell to the data input / output terminal. 6 and a bit mode (third mode) such as bit read.

The mode detection circuit 5 generates a mode detection signal S3 for discriminating each of the above modes based on the bit enable signal BE and the write enable signal WE.

The mode detection signal S3 is applied to the AND gate 47 together with the write enable signal WE, and the signal S1 based on the logical product of the two is generated. This signal S1 is used to determine the above data setup mode.

The bit control circuit 1 has a structure in which a first gate 2, a latch circuit 4, and a second gate 3 are connected in series. The first gate 2 gates the data input signal DI based on the signal S1. The latch circuit 4 holds the signal passed through the first gate 2 by itself. On the other hand, the second gate 3 gates the signal from the latch circuit 4 based on the bit enable signal BE and outputs the signal S2.

The signal S2 from the bit control circuit 1 is output to the NAND gates 48 and 50. In addition, Nand Gate 4
8. The signal S2 input to the NAND gate 50 is connected to the drain of the MOS transistor 58 to which the bit enable signal BE is input. By the way, the signal COW is also input to the NAND gate 48, and the write enable signal WE is input to the NAND gate 50.

The output of the NAND gate 48 is the inverter 49.
Through the NAND gates 42 and 43.

On the other hand, the output of the NAND gate 50 is output to the NOR gate 51.

Further, the data output signal DO is the NOR gate 4
The data output signal / DO is input via the NOR gate 41.

The output of NOR gate 40 is applied to the input side of NOR gate 41 and NAND gate 42, and the output of NOR gate 41 is applied to the input side of NOR gate 40 and NAND gate 43.

The data input signal DI is the NOR gate 4
0 and NAND gate 43 connected to data input signal / D
I is connected to NOR gate 41 and NAND gate 42.

The output of the NAND gate 42 is given to the gate of the MOS transistor 56 through the inverters 44 and 46, and the output of the NAND gate 43 is output to the inverter 45.
Through the gate of the MOS transistor 57. MOS transistor 56 and MOS transistor 57
Is a complementary connection, and its output is given to the data input / output terminal 6.

On the other hand, the input to the data input / output terminal 6 is given to the NOR gate 51.

The output of the NOR gate 51 is inverted through the inverter 52 and further becomes the data input signal / DI through the inverter 53. On the other hand, the output of the inverter 52 becomes the data input signal DI through the inverters 54 and 55.

The operation of the above-described structure will be described below with reference to the timing chart of FIG. By the way, FIG. 2A shows the bit enable signal B.
E, the same figure (B) is write enable / WE, the same figure (C)
Shows the 1st bit of I / O data, and FIG. 6D shows the i-th bit of I / O data.

First, at time t1, as shown in FIG. 2B, when the write enable / WE falls to the low level, the data setup period starts.

In this data setup period, it is set whether or not bit write (bit write) or bit read (bit read) is necessary, and which bit is to be bit write or bit read. In this case, the bit selection is performed based on the input data from the data input / output terminal 6.

When it is desired to perform bit write or bit read, the bit enable signal BE is raised at the timing of time t2 in the data setup period, and at the same time, the bit to be bit written or bit read is desired. The data input signal DI of is set to the high level based on the input data from the data input / output terminal 6. Here, as shown in FIG. 2C, I / O1 is raised to a high level.

As a result, the mode detection circuit 5 detects the bit write or bit read mode and sets the mode detection signal S3 to the high level. The mode detection signal S3 is gated by the AND gate 47 by the write enable signal WE, and the first signal of the bit control circuit 1 is generated as the signal S1.
Given to gate 2.

As a result, the data input signal DI based on the input data from the data input / output terminal 6 is taken into the latch circuit 4 through the first gate 2 of the bit control circuit 1 and latched there.

When the write enable / WE is returned to the high level at the timing of time t3, the I / O1 is returned to the low level at the same time, and the bit enable signal BE is returned to the low level at time t4, the normal write mode is set.

In the normal mode, since the bit enable signal BE is at low level, the signal S2 is in a high impedance state and the MOS transistor 58 is turned on to activate the NAND gate 48 and the NAND gate 50.

Therefore, the signal COW is transmitted to the NAND gate 4
8 and a NAND gate 42 and a NAND gate 43 via an inverter 49, and these gates are supplied with the signal COW.
To be active based on At the time of normal write, the signal COW is at low level, and therefore the outputs of both the NAND gates 42 and 43 are at high level, and the inverter 4
Since the gates of the MOS transistors 56 are set to the high level through 4 and 46 and the gates of the MOS transistors 57 are set to the low level through the inverter 45, the drains of the MOS transistors 56 and 57 are in the high impedance state.

On the other hand, the NAND gate 50 activates the NOR gate 51 based on the write enable signal WE. That is, when the write enable signal WE is at high level, the NOR gate 51 becomes active.

Therefore, at the time of normal write, every time the write enable / WE becomes high level at the timing of time t5 and time t7, all the bits of the data input from the data input / output terminal 6 are transferred from the NOR gate 51,
The data is input through the inverter 52, becomes a data input signal / DI through the inverter 53, and the inverters 54, 5
It becomes a data input signal DI through 5. These data input signals DI, / DI are written in all bits of a memory cell (not shown) as shown in FIGS. 2 (C) and (D).

At the time of normal write, when the write enable / WE changes from low level to high level at times t6 and t8, the NOR gate 51 sets its output to low level and data writing is not performed.

Next, at the timing of time t9, as shown in FIG.
As shown in (A), when the bit enable signal BE goes high, the bit write mode is entered.

In this case, the signal S2 is set to the high level in the bit for which the bit write and the bit read are set up in the latch circuit 4, and the signal S2 is set to the low level in the other bits. On the other hand, MO
Since the S transistor 58 is brought into a high impedance state by the bit enable signal BE, the NAND gate 48 and the NAND gate 50 are controlled by the signal S2.

That is, when the signal S2 is at a low level, both the NAND gate 48 and the NAND gate 50 are inactive. As a result, even if the write enable / WE becomes low level at the times t10 and t12, FIG.
As shown in (D), no data is written.

On the other hand, when the signal S2 is at a high level bit, the NOR gate 5 is used just as in the case of normal write.
Since 1 is activated, the write enable signal WE
Based on the above, the data write will be performed.

Note that at times t11 and t13, FIG.
As shown in, when the write enable / WE becomes high level, no data is written in any bit.

At time t14, as shown in FIG.
When the bit enable signal BE becomes low level and the write enable signal WE remains high level as shown in FIG. 7B, the normal read mode is set.

In this state, the MOS transistor 58 is turned on to give a high level signal to the NAND gates 48 and 50, so that the NAND gates 48 and 50 are activated in all bits. Further, since the write enable signal WE becomes low level and the signal COW becomes high level, the NAND gate 50 sets its output to high level and the NOR gate 51 inactive, and the NAND gate 48 sets its output to low level to set the inverter 4
The NAND gates 42 and 43 are activated through 9.

In this state, the data read from the memory cell (not shown) is applied to NOR gates 40 and 41 as data output signals DO and / DO, respectively. These signals are transmitted to the NAND gates 42 and 43 and the inverter 4
MOS transistors 56, 5 through 4, 46, 45
Given to gate 7. As a result, the MOS transistors 56 and 57 perform complementary operation according to the states of the data output signals DO and / DO, and output read data to the outside through the data input / output terminal 6.

In the normal read mode, all bits of data are read out according to the memory cycle from time t15 to time t16 and from time t17 to time t18, as shown in FIGS. Is done during.

In this state, when the bit enable signal BE goes high at the timing of time t19, as shown in FIG. 2A, the bit read mode is entered.

In this case, the signal S2 is set to the high level in the bit for which the data write-in or the bit read is set up in the latch circuit 4, and the signal S2 is set to the low level in the other bits. On the other hand, MO
Since the S transistor 58 is brought into a high impedance state by the bit enable signal BE, the NAND gate 48 and the NAND gate 50 are controlled by the signal S2.

That is, when the signal S2 is at the low level, both the NAND gate 48 and the NAND gate 50 are inactive. As a result, data is not read as shown in FIG.

On the other hand, when the signal S2 is at a high level, the NAND gate 48 is activated just as in the case of normal read. Therefore, when the signal COW is at a high level, both the NAND gates 42 and 43 are active. Data can be read.

Since data is read in accordance with the memory cycle even in bit read, as shown in FIG. 2C, from time t20 to time t2.
Data is read only during 1 and between time t22 and time t23.

Next, as shown in FIG. 2B, time t2
At 4, when the bit enable signal BE returns to the low level, the normal read state is restored.

FIG. 3 is a circuit diagram illustrating a specific configuration of the bit control circuit 1 for enabling the above operation. As shown in the figure, the data input signal DI is input through a gate circuit composed of MOS transistors 59 and 60. The signal S1 is input directly to the gate of the MOS transistor 60 and to the gate of the MOS transistor 59 through the inverter 63. As a result, when the signal S1 is at high level, the MOS transistors 59, M
Both the OS transistors 60 are turned on, and the data input signal D
I is transferred to the latch circuit 4. Otherwise, MO
Both the S transistors 59 and 60 are turned off and have high impedance when viewed from the input side of the latch circuit 4.

The latch circuit 4 has a self-holding type latch configuration in which the inverters 65 and 66 are connected in anti-parallel, and if there is a signal input from the first gate 2, it is self-holding according to its state. To do. The output of the inverter 65 is sent to the second gate 3 through the inverter 67.

The second gate 3 is connected to the MOS transistor 6
A gate circuit is composed of 1 and 62, and outputs the output of the inverter 67 as a signal S2. The gate of the MOS transistor 62 is controlled by the bit enable signal BE, and the gate of the MOS transistor 61 is controlled by the bit enable signal BE through the inverter 64. That is, when the bit enable signal BE is at the high level, the latched state in the latch circuit 4 is output as it is, but when the bit enable signal BE is the MOS transistor 60, the signal S2 is set to high impedance.

In the configuration as described above, the operation thereof will be described next together with the operation of the mode detection circuit 5 based on the timing charts of FIGS. 4 and 5. Incidentally, in FIGS. 4 and 5, (A) is the bit enable signal B.
E, (B) are write enable / WE, and (C) is a mode detection signal S3 which is an output signal of the mode detection circuit 5. 4 shows the state of each signal when writing data, and FIG. 5 shows the state of each signal when setting up data.

First, at the time of writing, as shown in FIG. 4, after some delay time has passed after the bit enable signal BE is set to the high level at time t1, the write enable signal BE is enabled at time t2. / WE falls to low level. At this time, the output signal of the mode detection circuit 5 becomes low level, and the mode detection signal S3 remains low level. As a result, the signal S1 is not supplied to the first gate 2, and the bit control circuit 1 outputs the latched state in the latch circuit 4.

As a result, while the write enable / WE is at the low level, the bit write operation and the write enable / W are performed.
When E becomes high level, the bit read operation is performed.

On the other hand, at the time of data setup, as shown in FIG. 5, the bit enable signal BE is set to the high level after some delay time has elapsed after the write enable / WE was set to the low level at the time t1. There is. As a result, the mode detection circuit 5 sets the mode detection signal S3, which is its output signal, to the high level. As a result, the first gate 2 of the bit control circuit 1 is turned on to cause the latch circuit 4 to latch the state of the data input signal DI.

At time t3, write enable / WE
When becomes a high level, it becomes a bit read operation state,
When the bit enable signal BE becomes low level at time t4, the normal read operation state is set.

In the data setup state, the bit enable signal BE and the data input signal DI of the bit to be bit-written or bit-read are set to high level to set the bit at the time of bit-writing or bit-reading.

As described above, the mode detection circuit 5 and the bit control circuit 1 operate so that each of data setup, normal write and normal read, bit write and bit read, as shown in the timing chart of FIG. It becomes possible to operate.

As described above, conventionally, since the input / output buffer circuit connected to the input / output terminal operates at the same time for every several bits, it is not possible to write or read data in bit units, so While it is difficult to check the individual characteristics of each bit of the input / output buffer circuit as described above, the configuration shown in FIG. Only by adding the bit control circuit 1, it becomes possible to control the data input / output through the input / output buffer in bit units.

[0122]

According to the semiconductor memory device of the present invention, since the input / output data can be controlled in bit units with a simple structure, the bit unit characteristics of the input / output buffer can be checked at the time of a test, so that the process can be optimized. Moreover, when applied to an image memory, processing in pixel units and image processing in screen units can be performed easily, so cost performance is better than in memories designed exclusively for images. It is excellent and has an effect that a general SRAM can be used to configure a video RAM for a graphics system.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an input / output buffer unit of a semiconductor memory device according to an exemplary embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG.

3 is a circuit diagram illustrating a specific configuration of a bit control circuit in the configuration of FIG.

FIG. 4 is a timing chart for explaining an operation at the time of bit writing in the configuration of FIG.

5 is a timing chart for explaining an operation at the time of data setup of the configuration of FIG.

FIG. 6 is a block diagram showing a first example of a conventional semiconductor memory device.

FIG. 7 is a block diagram illustrating a configuration of a 16-bit general-purpose SRAM in a second example of the conventional semiconductor memory device.

FIG. 8 is a block diagram illustrating a configuration of a 4-bit multi-port DRAM in a third example of the conventional semiconductor memory device.

[Explanation of symbols]

 1-bit control circuit 2 1st gate 3 2nd gate 4 latch circuit 5 mode detection circuit 6 data input / output terminal

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Claims (2)

[Claims] 1. In a semiconductor memory device having a plurality of memory cells and capable of simultaneously inputting a plurality of bits of data, the operation of a write / read buffer for each bit is controlled to perform write / read for each bit. An independently operable control means, wherein the control means is controlled by a logical condition of a write control signal and a bit-unit control signal and selectively outputs an added data input signal; A latch circuit that latches the data input signal that has passed through one gate; and a second gate that is controlled by the bit-unit control signal and that selectively outputs the data input signal latched by the latch circuit. A semiconductor memory device comprising: 2. A method for determining whether the mode is a data setup mode, a normal mode or a bit mode based on the write control signal and the bit unit control signal, and when it is determined to be the data setup mode. 2. The semiconductor memory device according to claim 1, further comprising a mode detection circuit that opens the first gate only when data for controlling each bit is set in the latch circuit and separates it from a normal write. .