JPH07239844A - Vector processor - Google Patents

Abstract

PURPOSE:To much more accelerate the vector processing by executing a conditional vector arithmetic instruction with a vector length degenerated just to a valid position. CONSTITUTION:A vector control register 1 holds a mask bit showing validity and invalidity to be used for the conditional vector arithmetic instruction. An instruction issue control part 2 controls the issue of vector arithmetic instruction. When the conditional vector arithmetic instruction is issued from the instruction issue control part 2, valid address designating means 3 and 4 successively investigate valid bit positions where the mask bit is '1' in the vector control register 1 and designate the valid address to respective vector data registers 7, 8 and 9 corresponding to those valid bit positions. The vector data registers 7 and 8 are read by using only the designated valid address, and a computing element 10 alternately calculates those contents and stores the arithmetic result in the vector data register 9 by using only the designated valid address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing device, and more particularly to a vector processing device for an information processing system.

[0002]

2. Description of the Related Art A conventional vector processing apparatus is used when vector operation instructions are consecutive and the number of mask bits indicating the effectiveness of processing in a vector control register is low in the vector length (for example, a sparse vector In such a case), after executing a vector compress instruction to degenerate the original vector data into vector data having only valid positions, execute a vector operation instruction with vector data of short vector length, and finally, again. By executing a vector expand instruction that expands each data degenerated according to the contents of the vector control register to the position of the element number before degeneration, the speed of vector processing is increased.

[0003]

Although the above-described conventional vector processing device can speed up the vector processing as compared with the case where the conditional vector operation instruction of the original vector length is executed, the original vector data can be processed. The vector compress instruction degenerates only valid data, executes the vector operation instruction with the vector length of valid data, and finally the vector expand instruction expands each data again to the position of the element number before degeneration. Therefore, it has a drawback that it requires a lot of processing time.

[0004]

The vector processing device of the first invention is (A) N of mask information (N is a positive integer) indicating valid and invalid used for a conditional vector operation instruction.
A vector control register that holds the mask bits,
(B) an instruction issue control unit for controlling the issue of vector operation instructions; (C) M (M is a positive integer) vector data registers each having N addresses; and (D) the instruction issue control. Section sequentially issues a conditional vector operation instruction, sequentially examines valid bit positions in which the mask bit of the vector control register is "1", and M vector data registers corresponding to the valid bit positions A plurality of valid address designating means for designating valid addresses, and (E) reading only some of the vector data registers using only valid addresses sequentially designated by one of the valid address designating means, The contents are mutually calculated, and the calculation result is calculated by using only the effective addresses sequentially specified by the other effective address specifying means. It is configured to include a calculating means for storing the data register, a.

The vector processing device of the second invention is
(A) A vector control register that holds N (N is a positive integer) mask bits of mask information indicating valid and invalid to be used for a conditional vector operation instruction, and (B) a vector length to be operated L (L is a positive integer and L ≦
N), a vector length register, (C) an instruction issue control unit for controlling the issuance of vector operation instructions, and (D) M (M is a positive integer) vector data each having N addresses. (E) When a conditional vector operation instruction is issued from the instruction issue control unit, the effective bit position where the mask bit of the vector control register is “1” is sequentially examined, and L or less Valid address designating means for holding valid addresses of M vector data registers corresponding to valid bit positions at positions, and (F) the number of mask bits indicating validity at bit positions below L of the vector control register. And (G) some of the vector data by sequentially using only the effective address held in the effective address designating means. Arithmetic means for reading out the registers, mutually calculating the contents thereof, and sequentially storing the operation result in the vector data register using only the effective address held in the effective address designating means. ing.

Further, the vector processing device according to the third invention is (A) a vector holding N (N is a positive integer) mask bits of mask information indicating valid and invalid used for a conditional vector operation instruction. Control register, (B)
Vector length L to be calculated (L is a positive integer L
≦ N), a vector length register holding (N), (C) an instruction issue control unit for controlling the issue of vector operation instructions, and (D)
M (M is a positive integer) vector data registers each having N addresses, and (E) when a conditional vector operation instruction is issued from the instruction issue control unit,
The effective bit positions of which the mask bit of the vector control register is "1" are sequentially examined, and the first effective bit position of which the mask bit is "1" is held for the effective bit positions of positions L and below. Then, after that, an effective address designating means for holding an effective bit interval for obtaining a distance from the held effective bit position to the next effective bit position,
(F) An effective bit number counter for counting the number of mask bits indicating the effectiveness at bit positions below L of the vector control register, and (G) the first effective bit position held in the effective addressing means and the following. A read address counter that sequentially receives valid bit intervals, adds them, and sequentially outputs a read address to the vector data register; and (H) a first valid bit position held in the valid address designating means, and the following. A write address counter that sequentially receives valid bit intervals, adds them, and sequentially sends a write address to the vector data register, and (I) sequentially uses a read address obtained from the read address counter, Read some of the vector data registers and inter-compute their contents, Light sequentially using the write address obtained from the address counter, and the operation result is configured to include a calculating means for storing only valid address vector data register.

[0007]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the vector processing device of the present invention. 2 is shown in FIG.
3 is a diagram showing an example of the contents of the vector control register 1 and the contents of effective address designating means 3 and 4 of FIG.

In the first embodiment, when the mask bit in the vector control register 1 shown in FIGS. 1 and 2 is "1", it indicates that the position with respect to the vector data registers 7, 8 and 9 is valid. At the same time, the maximum vector length that can be processed is "15".

The operation when the conditional vector operation instruction is executed will be described below with reference to FIGS. 1 and 2.

First, when the conditional vector operation instruction is issued by the instruction issue control unit 2, the effective address designating means 3 sets the address of the effective bit position where the mask bit in the vector control register 1 is "1". It is sequentially investigated from "00" and is sent to the read address register 5 every cycle.

That is, as shown in FIG. 2, the address "00" is transmitted in the first cycle, and the address "03" is transmitted in the next cycle because the mask bits of the addresses "01" and "02" are "0". . In this way, the address "0
0 "," 03 "," 04 "," 05 "," 07 "," 0 "
9 "and" 10 "are sequentially sent every cycle.

Therefore, the vector data registers 7 and 8
Reads the vector data sequentially in accordance with these addresses obtained in the read address register 5, the arithmetic unit 1
0 sequentially inputs the data read from the vector data registers 7 and 8 to perform an arithmetic operation, and sequentially outputs the operation result data to the vector data register 9.

On the other hand, the effective address designating means 4 is composed of the arithmetic processing time of the arithmetic unit 10 and the vector data register 7,
8 and the data transfer time between the arithmetic unit 10 and the arithmetic unit 1
According to the total data transfer time between 0 and the vector data register 9, etc., the same as the valid address designating means 3 after a certain time has passed from the sending of the address or data from the valid address designating means 3 to the read address register 5. By the operation, the generated effective addresses are sequentially transmitted to the write address register 6, and the operation result data are sequentially written in the vector data register 9 according to the instruction of the write address register 6.

Further, since the effective address designating means 3 sends a stop report signal to the instruction issue control section 2 when the address transmission is stopped, the instruction issue control section 2 shifts to issue control of the subsequent instruction. ing.

Next, FIG. 3 is a block diagram showing a second embodiment of the vector processing apparatus of the present invention. 4 is a diagram showing an example of the contents of the vector control register 11 and the contents of the effective address designating means 13 of FIG.

In the second embodiment, as shown in FIGS. 3 and 4, when the mask bit in the vector control register 11 is "1", the vector data registers 17, 18,
It indicates that the position with respect to 19 is valid, and the maximum vector length that can be processed is "15".

The operation when the vector length stored in the vector length register 21 is "14" and the conditional vector operation instruction is executed will be described below with reference to FIGS. 3 and 4.

First, the valid bit number counter 12 counts the mask bits in the vector control register 11, and the valid address designating means 13 validates the mask bits of the vector control register 11 being "1". The address of the bit position is sequentially examined from "00" and the effective address is held.

That is, the effective address designating means 13 is
As shown in FIG. 4, the effective address “00” is held first,
Next, since the mask bits of the addresses "01" and "02" are "0", the effective address "03" is held. In this way, valid addresses “00”, “03”, “04”,
Holds "05", "07", "09" and "10", and confirms that the mask bit of the address "13" is "0" because the vector length of the vector length register 21 is "14". Then this operation is stopped.

Further, the effective bit number counter 12 determines that the effective bit number is "7" without counting even if the address "14" has the effective bit "1", and the instruction issuance control unit 14 is notified. The command issuance control unit 14 will be reported later.
Operates with an execution vector length of "7".

Therefore, when the instruction issuance control unit 14 issues a conditional vector operation instruction, the effective address in the effective address designating means 13 is sent to the read address register 15, so that the vector data register 1
7 and 18 sequentially read the vector data in accordance with the above-mentioned effective address from the read address register 15, and the arithmetic unit 20 causes the vector data registers 17 and 18 to read.
The data received from each of the above are sequentially input and operated, and the data of the operation result is output to the vector data register 19.

Further, the effective address designating means 13 is arranged so that the arithmetic processing time in the arithmetic unit 20 and the data transfer time between the vector data registers 17 and 18 and the arithmetic unit 20 and the arithmetic unit 20 and the vector data register 19 are accumulated. The valid addresses are sequentially transmitted to the write address register 16 by a similar operation after a fixed time from the transmission of the address and data to the read address register 15 in accordance with the total time such as the data transfer time. .

Therefore, the vector data register 19 is
According to the instruction of the write address register 16, the calculation result data is sequentially stored only in the effective address. Then, the instruction issuance control unit 14 confirms the end of the operation of the execution vector length and shifts to the instruction issue control of the subsequent instruction.

In the vector processing device of the third embodiment, the contents of the vector control register 11 or the vector length "14" held in the vector length register 21 will be used thereafter.
Is changed, each time a conditional vector operation instruction is issued, the valid address held by the valid address designating means 13 is stored in the vector data registers 17, 18,
The subsequent operation is performed as a read address or a write address for each of the nineteen.

Next, FIG. 5 is a block diagram showing a third embodiment of the vector processing apparatus of the present invention. 6 is a diagram showing an example of the contents of the vector control register 31 and the effective address designating means 33 of FIG.

In the third embodiment, as shown in FIGS. 5 and 6, when the mask bit in the vector control register 31 is "1", the vector data registers 39, 40,
It indicates that the position with respect to 41 is valid, and the maximum vector length that can be processed is "15".

The operation when the vector length stored in the vector length register 43 is "14" and the conditional vector operation instruction is executed will be described below with reference to FIGS. 5 and 6.

First, the valid bit number counter 32 counts the mask bits in the vector control register 31, and the valid address designating means 33 sequentially examines the address of the vector control register 31 from "00". First, the first valid bit position where the mask bit is "1" is held, and thereafter, the distance from the valid bit position held at that time to the next valid bit position is investigated to determine the valid bit interval. keeping.

That is, as shown in FIG. 6, the valid address designating means 33 first holds "00" at the first valid bit position where the mask bit is "1", and sequentially holds the next valid bit from the valid bit position. Effective bit intervals “03”, “01”, “01”, “02”, “0” that are distances to the position
It holds "2" and "01".

In this case, since the vector length of the vector length register 43 is "14", the mask bits up to the address "13" are investigated, and the address "14" becomes
Even if there is "1", it will not be the effective bit position. Further, since the valid bit number counter 32 reports the valid bit number to "7" to the instruction issue control unit 34, the instruction issue control unit 34 thereafter sets the execution vector length to "7".
Is working as.

When the instruction issuance control section 34 issues a conditional vector operation instruction, the read address counter 35 is sequentially given the effective bit intervals of the mask bits held in the effective address designating means 33. Then, these are added and the read address is sequentially sent to the read address register 37.

Therefore, the vector data registers 39, 4
0 is sequentially given the above-mentioned read address from the read address register 37 and sequentially reads the vector data. Therefore, the calculator 42 causes the vector data register 3 to read.
The data read from 9, 40 are sequentially input and calculated,
The data of the calculation result is output to the vector data register 41.

On the other hand, the write address counter 36 calculates the processing time by the arithmetic unit 42, the data transfer time between the vector data registers 39 and 40 and the arithmetic unit 42, and the data between the arithmetic unit 42 and the vector data register 41. In accordance with the total time such as the transfer time, after a certain period of time from the transmission of the effective bit interval from the effective address designating means 33 to the read address counter 35, the effective address designating means 33 also sequentially sets the effective bit intervals of the mask bits. The write addresses are sequentially supplied to the write address register 38 by adding them.

Therefore, the vector data register 41 is
The above write addresses from the write address register 38 are sequentially applied, and the vector data of the operation result from the operation unit 42 is sequentially stored only in the effective address.
Then, the instruction issuance control unit 34 confirms the end of the operation of the execution vector length and shifts to the issuance control of the subsequent instruction.

In the vector processing device of the third embodiment, the contents of the vector control register 31 or the vector length "14" held in the vector length register 43 thereafter.
Unless the value is changed, the valid bit interval held by the valid address designating means 33 is used as the addition number of the read address register 37 and the write address register 38 each time the conditional vector operation instruction is issued.
The subsequent operation is performed after calculating the read address or the write address for the vector data registers 39, 40, 41.

[0036]

As described above, when processing a conditional vector operation instruction, the vector processing device of the present invention stores the vector data register corresponding to the mask bit indicating the validity in the vector control register. By using the effective access designating means for designating only the element number as the read address and the write address, the data compression by the vector compress instruction and the data expansion by the vector expand instruction which have been performed by the conventional vector processing device can be performed. It is possible to execute a conditional vector operation instruction based on a degenerated vector length without executing it, and it is possible to further speed up vector processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a vector processing device of the present invention.

FIG. 2 is a diagram showing an example of contents of a vector control register 1 and contents of effective address designating means 3 and 4 in FIG.

FIG. 3 is a block diagram showing a second embodiment of the vector processing device of the present invention.

FIG. 4 is a diagram showing an example of contents of a vector control register 11 and contents of an effective address designating means 13 of FIG.

FIG. 5 is a block diagram showing a third embodiment of the vector processing device of the present invention.

FIG. 6 is a diagram showing an example of contents of a vector control register 31 and contents of an effective address designating means 33 of FIG.

[Explanation of symbols]

1, 11, 31 Vector control register 2, 14, 34 Instruction issue control unit 3, 4, 13, 33 Effective address designating means 5, 15, 37 Read address register 6, 16, 38 Write address register 7, 8, 9, 17, 18, 19, 39, 40, 41
Vector data register 10, 20, 42 Operation unit 12, 32 Effective bit number counter 21, 43 Vector length register 35 Read address counter 36 Write address counter

Claims (3)

[Claims] 1. A vector control register that holds N (N is a positive integer) mask bits of mask information indicating valid and invalid used for a conditional vector operation instruction, and (B) a vector operation instruction. And an instruction issue control unit for controlling the issue of (C) M each having N addresses.
(M is a positive integer) vector data registers,
(D) When a conditional vector operation instruction is issued from the instruction issue control unit, the effective bit positions where the mask bit of the vector control register is "1" are sequentially examined, and the effective bit positions are corresponded to the effective bit positions. A plurality of valid addressing means for designating valid addresses of the M vector data registers, and (E) some of the vectors using only valid addresses sequentially designated by one of the valid addressing means Arithmetic means for reading out the data register, mutually operating the contents thereof, and storing the operation result in the vector data register using only the effective addresses sequentially designated by the other effective address designating means. A vector processing device comprising: 2. A vector control register that holds N (N is a positive integer) mask bits of mask information indicating valid and invalid used in a conditional vector operation instruction, and (B) performs an operation. A vector length register holding a target vector length L (L is a positive integer and L ≦ N),
(C) an instruction issue control unit for controlling the issue of vector operation instructions, (D) M (M is a positive integer) vector data registers each having N addresses, and (E) the instruction issue control When a conditional vector operation instruction is issued from the section, the effective bit positions in which the mask bit of the vector control register is "1" are sequentially examined, and M corresponding to the effective bit positions at positions L and below are examined. Valid address designating means for holding valid addresses of the vector data registers, and (F) a valid bit number counter for counting the number of mask bits indicating validity at bit positions below L of the vector control register, G) Reading some of the vector data registers by sequentially using only the effective addresses held in the effective address designating means,
Vector processing, wherein the contents are mutually calculated, and only the effective address held in the effective address designating means is used to store the operation result in the vector data register in sequence. apparatus. 3. A vector control register that holds N (N is a positive integer) mask bits of mask information indicating valid and invalid to be used in a conditional vector operation instruction, and (B) performs an operation. A vector length register holding a target vector length L (L is a positive integer and L ≦ N),
(C) an instruction issue control unit for controlling the issue of vector operation instructions, (D) M (M is a positive integer) vector data registers each having N addresses, and (E) the instruction issue control When a conditional vector operation instruction is issued from the section, the effective bit positions in which the mask bit of the vector control register is "1" are sequentially examined, and the effective bit positions at positions equal to or lower than L are masked. Valid address designating means for holding a first valid bit position whose bit is "1" and thereafter holding a valid bit interval for obtaining a distance from the held valid bit position to the next valid bit position; F) A valid bit number counter for counting the number of mask bits indicating validity at bit positions less than L of the vector control register, and (G) held in the valid address designating means. A read address counter that sequentially receives the first valid bit position and subsequent valid bit intervals, adds these, and sequentially sends the read address to the vector data register, and (H) holds in the valid address designating means. A write address counter that sequentially receives the first valid bit position and subsequent valid bit intervals, adds them, and sequentially sends a write address to the vector data register; and (I) a read obtained from the read address counter. Addresses are sequentially used to read some of the vector data registers, mutually calculate their contents, sequentially use the write addresses obtained from the write address counters, and calculate the operation result of the vector data registers. And a calculation means for storing only the effective address. Vector processing apparatus according to.