JPH0744532A - Vector processing device - Google Patents

Abstract

PURPOSE:To enhance the efficiency of the vector processing by selecting vector data read from a vector register so as to apply compression processing to selected data at once. CONSTITUTION:The device is provided with a data selection circuit 5 reading contents of a mask register 4 and an input vector register 1 one by one element and selecting data of the input vector register 1 to an output vector register 2 or 3 depending whether the data read from the mask register 4 is 1 or 0, and compression circuits 6, 7 compressing the selected data, a counter circuit 8 simultaneously counting number of elements counting number of 1s or Os of the data from the mask register 4 and scalar registers 9, 10 storing the output data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing device used in a large-scale information processing device of vector operation type.

[0002]

2. Description of the Related Art Conventionally, a vector processing device of this type performs the following processing. For example, in a Monte Carlo code that simulates the behavior of a plurality of particles, the particle classification process of a program as shown in FIG. 2 frequently appears. The notation of the program is based on the FORTRAN language. This process is M (I) for I from 1 to N.
A (I) is classified into array B and array C depending on whether or not is a positive value. In the conventional vector processing device, this particle classification process is performed by a mask calculation and a compression calculation. The processing flow in this case is shown in FIGS.
Will be described. 5 and 6 are flowcharts of processing in the conventional example.

(1) Mask Generation M (I). GT. 0
Is evaluated by vector operation, and the evaluation result (1 if true, 0 if false) for each loop iteration is stored in the mask register.

(2) Compress 1 Data A on the input vector register 1 whose mask register content corresponds to 1
Compress (I) and store in output vector register 2. Further, the number of 1s in the mask register is obtained by the element number count instruction and stored in the register. The value obtained by adding the value of this register and J1INIT is stored in the memory location of J1.

(3) Store 1 With the value of the above register as the vector length and the memory address of B (J1INIT + 1) as the head memory location, the data in the above compressed vector register is vector-stored.

(4) Inversion of mask The above mask register is inverted element by element (1 becomes 0, 0 becomes 1).

(5) Compress 2 The data A (I) in the vector register whose mask register content corresponds to 1
Is compressed and stored in the output vector register 3.
Further, the number of 1s in the mask register is obtained by the element number count instruction and stored in the register. The value obtained by adding the value of this register and J1INIT is stored in the memory location of J1.

(6) Store 2 With the value of the register obtained in (5) as the vector length and the memory address of C (J1INIT + 1) as the head memory position, the data in the vector register compressed in (5) is vectored. Store. However, when the value of the loop length N exceeds the maximum vector processable vector length, it is necessary to divide N loop iterations into a plurality of operations having iterations equal to or less than the maximum loop length for processing.

[0009]

In the conventional method described above, since the mask inversion process, the two compression processes and the two element number counting processes are required, efficient vector processing cannot be performed. There is a problem.

[0010]

A vector processing device according to the present invention includes a plurality of input vector registers for holding input operand data, a master register for controlling vector operation, vector data held by the input vector register, and The data held by the master register is sequentially read as one set and is output as the first output data when the data of the master register is 1, and is output as the second output data when the data of the master register is 0. A data selection circuit, a first output vector register that holds the first output data, and a second output vector register
Second output vector register for holding the output data of

Further, a counter circuit for counting the number of times that the data of the read master register is 1 or 0 may be provided.

[0012]

In the vector processing device of the present invention, the vector data in the input vector register holding the input data and the data in the mask register are sequentially read one by one, and the value of the data read from the mask register is 1. If the first
2 is equipped with a data selection circuit for selecting and transmitting the above vector data to the output vector register of No. 2 and to the second output vector register if it is 0. For example, this circuit is used to classify particles as shown in FIG. THE in processing
The processing of the N clause and the processing of the ELSE clause can be performed simultaneously.

Further, in the vector processing device according to the first invention of the present application, in order to obtain the vector length for storing the vector data classified in the vector register, a process of counting the number of 1s or 0s in the mask register is performed. Although it must be performed separately, this counting process can be performed at the same time by adding a counter circuit for counting the number of times 1 or 0 of the data read from the mask register.

[0014]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. The input vector register 1 stores input operand data by the number of vector lengths. In the example shown in FIG. 2, the input operand corresponds to the array A. The output vector register 2 and the output vector register 3 store output vector data by the number of vector lengths. In the example shown in FIG. 2, the output vector data corresponds to the data to be stored in the arrays B and C at the end of the processing. The mask register 4 is a register that holds data for controlling conditional vector operation, and holds 1-bit data of 0 or 1 for the number of vector lengths. Normally, the i-th bit data of the mask register is used to control the processing on the i-th data of the vector register.

The data selection circuit 5 receives the data of one element per clock from the input vector register 1 and the mask register 4, and when the bit data received from the mask register 4 is 1, the compress circuit 6 receives the vector register. When the bit data received from the mask register 4 is 0, the data received from 1 is sent, and the data received from the vector register 1 is sent to the compress circuit 7. The compress circuit 6 sends the data received from the distributor 5 to the output vector register 2 and controls the received data to be continuously stored in the output vector register 2. The compress circuit 7 sends the data received from the data selection circuit 5 to the vector register 3 and controls the received data to be continuously stored in the vector register 3.

The counter circuit 8 includes mask registers 4 to 1
The bit data is received for each element by the number of vector lengths for each clock, the number of times the bit data having a value of 1 is received is stored in the register 9 and the value is set to 1
The number of times of receiving the bit data of is stored in the register 10.

Next, the manner in which the processing shown in FIG. 2 is executed will be described with reference to FIGS. As an initial condition, the value of the variable N holding the vector length is 10, and M
The respective values from (1) to M (10) are as follows. M (1) = 3, M (2) =-2, M (3)
= -3, M (4) = 1, m (5) = 10, M (6) =
2, M (7) =-3, M (8) = 2, M (9) = 1, M
(10) =-2 Further, it is assumed that the array A is loaded in the vector register 1 and the value of A (I) is stored as the I-th element of the input vector register 1.

(1) Generation of mask Each element of the array M is set to 0
If it is larger than 0, 1 is stored. If not, 0 is stored in the corresponding element number position of the mask register 4.
In general, this can be realized in a vector computer by a load instruction of the array M, a vector comparison instruction, and a mask generation instruction.

(2) Compress Next, the data of the array A stored in the input vector register 1 and the mask register 4
The bit data stored in 1 is sent to the data selection circuit 5 one element at a time. The data selection circuit 5 sends to the compress circuit 6 if the sent bit data is 1, and to the compress circuit 7 if the bit data is 0. The data received from the register 1 is transmitted. The compress circuit 6 and the compress circuit 7 send the data received from the data selection circuit 5 to the output vector register 2 and the output vector register 3, respectively, and the data received from the data selection circuit 5 are the output vector register 2 and the output vector register. The output vector registers 2 and 3 are controlled so as to be stored consecutively on the output vector register 3. This control is held by, for example, each of the compress circuits 6 and 7 incrementing the data position to be written next to the vector register by 1 only when the data is sent from the data selecting circuit 5, and at the same time as sending the data. This can be done by sending the writing positions of the above to the output vector registers 2 and 3, respectively. Alternatively, the counter circuit 8
In the case of having the above, it is possible to share the counter for controlling the vector register and the counter circuit 8 in the same circuit. Data is generated in the output vector registers 2 and 3 by the processing described above.

(3) Counting the number of elements Counter circuit 8
In the vector processing device having the above, the mask data is sent to the counter circuit 8 at the same time as the above-described processing, that is, at the same time as the mask data is sent from the mask register 4 to the data selection circuit 5 one element at a time. The counter circuit 8 counts the number of pieces of data having a value of 1 and the number of pieces of data having a value of 0 transmitted from the data selection circuit 5, and when the mask data of the vector length N is transmitted, Count value to register 9 and register 1
Store in 0.

Further, in the vector processing device which is not provided with the counter circuit 8, the effective vector length of the vector register 2 is obtained by using the vector instruction for counting the number of 1 values in the mask register, and the vector register 1 The effective vector length of the vector register 3 is obtained by subtracting the effective vector length of the vector register 2 from the value of the register holding the value of the effective vector length N, and the obtained two effective vector lengths are stored in the registers 9 and 10. This processing can be performed by storing.

(4) Store 1, (5) Store 2 The number of registers 9 is used as the vector length, the value of the vector register 2 is vector-stored with the start address of the array B as the store start memory position, and the value of the register 10 is stored. This store processing can be performed by vector-storing the value of the vector register 3 as the vector length with the start address of the array C as the store start memory position.

(6) Storing J1 and J2 Finally, the value of register 9 and the value of J1INIT are added and stored in J1, and the value of register 10 and the value of L2INIT are added and this is stored in J2. By storing, the process shown in FIG. 2 is completed. However, when the value of the loop length N exceeds the maximum vector processable vector length, it is necessary to divide N loop iterations into a plurality of operations having iterations equal to or less than the maximum loop length for processing.

[0024]

As described above, according to the present invention, the vector data is selected and the selected data are simultaneously compressed. Therefore, the speed can be doubled as compared with the conventional compression processing. There is an effect that can be done. Further, if the counter circuit is provided, the element length can be counted at the same time, so that the speed can be similarly increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a program diagram of a processing example.

FIG. 3 is a flowchart showing a processing procedure of an embodiment of the present invention.

FIG. 4 is a flowchart showing a processing procedure of an embodiment of the present invention.

FIG. 5 is a flowchart showing a processing procedure of a conventional example.

FIG. 6 is a flowchart showing a processing procedure of a conventional example.

[Explanation of symbols]

 1 Input vector register 2, 3 Output vector register 4 Mask register 5 Data selection circuit 6, 7 Compress circuit 8 Counter circuit 9, 10 Scalar register

Claims (2)

[Claims] 1. A plurality of input vector registers for holding input operand data, a master register for controlling a vector operation, vector data held by the input vector register and data held by the master register as one set in sequence. A data selection circuit that outputs this as first output data if the data in the master register is 1 and outputs it as second output data if the data in the master register is 0; and the first output data. And a second output vector register that holds the second output data, the vector processing device. 2. The vector processing device according to claim 1, further comprising a counter circuit that counts the number of times that the read data of the master register is 1 or 0, respectively.