JPH0683859A - Vector processor - Google Patents

Abstract

PURPOSE:To easily provide sort algorithm and to execute sort at high speed. CONSTITUTION:This device is provided with a means for successively reading the contents of a first vector register 1 from a position instructed by a first counter 7 and means for comparing the read data with the contents of a comparative data register 10 and for storing them in second and third vector registers 2 and 3 corresponding to the level relation. Further, the device is provided with a means to store the number of elements, which are stored in the second and third vector registers 2 and 3, in a vector length register 16 and general-purpose register 17 and means to simultaneously sort attached information or element numbers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vector processing device.

[0002]

2. Description of the Related Art Sort processing is one of the very important processings along with data retrieval in information processing. In particular, the quick sort algorithm can process problems with n data in order time,
It is known as a high-speed algorithm for the bubble sort algorithm and the like. However, conventionally, the sorting process is generally realized by software, and is realized by sequentially reading and comparing array data on the main memory and performing an operation of exchanging the data.

Further, in the vector processing device, a method of using a mask generation instruction to generate the result of comparing the magnitude relations of data as mask data and performing a replacement operation is used.

[0004]

When the above-described conventional sort processing is performed by the scalar processing, since the access to the main memory occurs for each comparison operation and data exchange operation for individual data, the memory access is sorted. There is a possibility of becoming a performance bottleneck in processing. Also,
Although the processing for each element is performed serially, this kind of processing can be performed in parallel, and the parallel processing is expected to speed up the processing.

Even when it is carried out by the vector processing device, there is a problem that it is necessary to carry out mask generation processing data compression processing and the like, the processing is complicated, and a sufficient processing time cannot be expected.

[0006]

The vector processing device of the present invention is a vector processing device having a plurality of sets of vector registers each composed of a plurality of registers. First reading means for reading from the designated position and counting up the contents of the first counter, storage means for storing a predetermined value, and first vector read by the first reading means. Comparing means for comparing the content of the register with the content of the storage means, and as a result of the comparing means, the content of the first vector register read by the reading means is larger than the content of the storage means, or When it is judged that they are equal, the second
Write to a position indicated by the content of the second counter of the vector register and count up the content of the second counter; and as a result of the comparison means, the first read means read by the read means. A second write means for counting up the content of the third vector register when it is determined that the content of the first vector register is smaller than or equal to the content of the storage means.

[0007]

The present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of one embodiment of the present invention.
In this embodiment, the first vector register 1, the second vector register 2, the third vector register 3, the fourth vector register 4, the fifth vector register 5, and the sixth vector register 6 are referred to. , A first counter 7, a second counter 8, a third counter 9, a comparison data register 10, a comparator 11, a positive / negative logic circuit 12, a first selector 13, a second selector 14, and a third selector 1.
5, a vector length register 16 and a general-purpose register 17.

The first vector register 1 includes a signal line 10
1 is connected to the comparator 11 and the second vector register 2 and the third vector register 3, and the comparison data register 10 is also connected to the comparator 11 via the signal line 1001. The first counter 7 is connected to the first vector register 1, the first selector 13, the second selector 14 and the sixth vector register 6 via the signal line 701.

The second counter 8 is connected to the second vector register 2, the fourth vector register 4 and the third selector 15 via a signal line 801.

The third counter 9 is connected to the third vector register 3, the fifth vector register 5 and the third selector 15 via a signal line 901.

The sixth vector register 6 has a signal line 60.
1 is connected to the first selector 13 and the second selector 14, and the first selector 13 and the second selector 14 are connected to the fourth vector register 4 and the fourth vector register 4 via the signal lines 1301 and 1401, respectively. 5 to vector register 5.

The comparator 11 is connected via the signal line 1101.
It is connected to the positive / negative logic circuit 12, and the positive / negative logic circuit 12 is connected to the second counter 8, the second vector register 2, and the fourth vector register 4 via the control line 1201. Further, it is connected to the third counter 9, the third vector register 3, and the fifth vector register 5 via the control line 1202.

The third selector 15 is connected to the vector length register 16 and the general-purpose register 17 via the signal line 1501.

Next, the operation will be described.

The array data to be sorted is loaded from the main memory into the first vector register 1 in advance.
Further, in the comparison data register 10, an arbitrary one of the data to be sorted, for example, the head element of the second vector register 2 is set. The first counter is sequentially incremented from the initial value "0" to the value of the vector length register 16, and accordingly, the data in the first vector raiser 1 is sequentially read.

In the comparator 11, the comparison data register 10
Is sequentially compared with the content read from the first vector register 1, and when the modulus of the content of the first vector register 1 is large, "1" is small on the signal line 1101. 0 "is output. "0" if they are equal
Or "1" is output.

The information on the signal line 1101 is the positive / negative logic circuit 1
2, information as it is for the control line 1201,
Inverted logic signals are output to the control line 1202. The control lines 1201 and 1202 operate as write enable signals for the second vector register 2 and the third vector register 3, and the value of the control line is "1".
At this time, the content of the first vector register 1 read via the signal line 101 is written to the position designated by the second counter 8 of the second vector register 2, or
Is written in the position designated by the third counter 9 of the vector register 3. At the same time, the values of the second counter 8 and the third counter 9 are incremented, so that the counter values are changed to the next write position.

By returning the above processing by the number of times indicated by the value of the vector length register 10, the comparison data register 1 among the data of the first vector register 1 is returned.
Elements greater than the value of 0 are in the second vector register 2
The smaller one is stored in the third vector register 3. The number of elements stored in the second vector register 2 is the content of the second counter 8, and the number of elements stored in the third vector register 3 is the content of the third counter 9.

Next, the contents of the second vector register 2 are replaced with the first vector register 1, and the value of the second counter 8 is set in the vector length register 16 via the third selector 15. However, the contents of the third vector register 3 are saved in a seed memory or the like (not shown), and the value of the third counter 3 is saved in the general-purpose register 17 via the third selector 15, and then, as described above. By repeating the process, the quick sort algorithm is realized. This algorithm divides into two large and small constituent groups, repeats until the element 1 is finally reached, and finally joins the divided groups to sort into array data sorted in ascending or descending order. That is.

In a sort program, there are cases where sort key data and associated data are linked and sorted. For example, using the first vector register 1 as the sort key, the comparison data register 10 and the first vector register 1
The contents stored in the vector register 1 are compared with each other, and the contents of the first vector register 1 are stored in either the second vector register 2 or the third vector register 3 according to the result.

At the same time, the first vector register 1
Is stored in the second vector register 2, the read address of the first vector register 1 (the content of the first counter 7) is stored in the fourth vector register, and the content of the first vector register 1 is stored in the second vector register 1. Suppose that the read address of the first vector register 1 is stored in the fifth vector register 5 when it is stored in the third vector register 3.

A control line 120 is connected to the second vector register 2.
At the same time that the contents of the first vector register 1 are written in accordance with the instruction 1, the signal line 8 is sent to the fourth vector register 4.
01, the same position as the write position of the second vector register 2 is designated, and the first counter 7
Stores the value of.

Further, the fourth vector register 4 is also realized by writing the value of the first counter 7 at the same writing position as the third vector register 3.
At this time, the first selector 13 and the second selector 14 are
It is set so that the content of the signal line 701 is selected.

The element number or associated information is stored in advance in the sixth vector register 6 (first selector 1
3, the second selector 14 is set so that the signal line 601 is selected), and at the same time as reading the first vector register 1, the read position of the first vector register 1 is read via the signal line 701. Reads the contents of the sixth vector register 6 at the same position as and writes it to the fourth vector register 4 at the same position as the second vector register 2 and the fifth vector register 5 at the same position as the third vector register 3. As a result, the sorting process for the accompanying information is realized.

Since the vector processing device is generally pipelined in many cases, each signal line may need to be provided with several registers in order to match the number of stages of the pipeline.

[0027]

As described above, according to the present invention, by adding a function for quick sort processing to the vector processing device, the realization of the sort program can be facilitated and the sort program can be executed at high speed. It will be possible.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

[Explanation of symbols]

 1 1st vector register 2 2nd vector register 3 3rd vector register 4 4th vector register 5 5th vector register 6 6th vector register 7 1st counter 8 2nd counter 9 3rd Counter 10 Comparison data register 11 Comparator 12 Positive / negative logic circuit 13 First selector 14 Second selector 15 Third selector 16 Vector length register 17 General-purpose register

Claims (5)

[Claims] 1. In a vector processing device having a plurality of sets of vector registers composed of a plurality of registers, the contents of the first vector register are read from a position indicated by the contents of the first counter and the contents of the first counter are read. Reading means for counting up, storage means for storing a predetermined value, contents of the first vector register read by the first reading means and contents of the storage means are compared. And a second vector when the content of the first vector register read by the reading means is determined to be greater than or equal to the content of the storage means as a result of the comparing means. Write to the position indicated by the contents of the second counter of the register and count up the contents of the second counter. When the contents of the first vector register read by the reading unit are smaller than or equal to the contents of the storing unit as a result of the first writing unit for writing and the comparing unit,
A vector processing device having second writing means for counting up the contents of a third vector register. 2. The first writing means writes the second vector register at the same time, and simultaneously writes the contents of the first counter to a position indicated by the contents of the second counter of the fourth vector register. 3 writing means and the second writing means write the third vector register at the same time, and at the same time, write the contents of the first counter to a position indicated by the contents of the third counter of the fifth vector register. The vector processing device according to claim 1, further comprising a fourth writing unit. 3. A vector length register representing the number of elements for executing vector processing, said second counter,
2. The vector processing device according to claim 1, further comprising storage means for selectively storing the contents of a third counter in the vector length register. 4. A general-purpose register operable by a program, and storage means for selectively storing the contents of the second counter and the third counter in the general-purpose register. Vector processing device described. 5. The second writing means includes a second writing means.
At the same time as writing to the vector register of, the content read from the position indicated by the content of the first counter of the sixth vector register is written to the position of the content of the second counter of the fourth vector register. The fifth writing means, and the third writing means by the second writing means.
Of the sixth vector register, and at the same time, the contents read from the position indicated by the contents of the first counter of the sixth vector register are written into the position indicated by the contents of the third counter of the fifth vector register. The vector processing device according to claim 1, further comprising a sixth writing unit.