JPH07236158A - Secam signal recording/reproducing circuit - Google Patents

Abstract

PURPOSE:To attain inexpensive recording/reproducing and a discrimination processing circuit. CONSTITUTION:Either one of an output from a frequency dividing circuit 13 for dividing the frequency of an oscillation signal from a VCO 12 by four and the output of the VCO 12 is selected by a switch SW2. Either one of SECAM chroma signals inputted to a recording input terminal Rin and a reproducing input terminal Pin is selected by a switch SW1. The outputs of the switches SW2, SWI are respectively inputted to one and the other input terminals of a phase comparator circuit 11 to compare the phases of these input signals. The oscillation frequency of the VCO 12 is controlled based upon the phase comparing output of the circuit 11. The switch SW2 is controlled so as to select an oscillation signal from the VCO 12 at the time of recording and select an output from the circuit 13 at the time of reproducing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a SECAM type V
The present invention relates to a SECAM recording / reproducing circuit suitable for use in TR.

[0002]

2. Description of the Related Art A conventional L-SECAM VTR signal processing system will be described with reference to FIG. First, in the case of recording, as shown in (a), the SECAM chroma signal separated from the composite video signal is input to the REC input Ri.
It is input from the n to the frequency divider circuit 31 and low-pass converted to a quarter frequency. Rec output R of converted chroma signal
It is output as a recording signal from out and recorded on the tape.

At the time of reproduction, as shown in (b), the chroma signal component low-frequency-converted by the divide-by-4 circuit 31 is extracted from the reproduced signal and introduced from the reproduced input Pin to the quadrupling circuit 32. Since the quadruple multiplication circuit 32 performs an operation opposite to the frequency division performed at the time of recording, the same frequency signal as the chroma signal applied to the REC input Rin is reproduced. The output of the quadruple multiplication circuit 32 is output from the reproduction output Pout.

In either case of recording / reproducing, whether or not the incoming chroma signal is a SECAM system signal is detected by a circuit (c), and whether or not a recording / reproducing processing output is generated is controlled. There is a need. Ie IDE
Input the chroma signal to NT signal input IDin, and input it to I
It is supplied to the DENT discrimination circuit 33. The IDENT discrimination circuit 33 detects the chroma FM center frequency alternation unique to the SECAM method, and obtains the discrimination result from the discrimination output IDout.
Such an IDENT discrimination circuit 33 is disclosed in Japanese Patent Laid-Open No.
-210892, but the description is omitted.

In the system described above, the divide-by-4 circuit 31 for recording, the multiply-by-4 circuit 32 for reproducing, and I
Since each processing circuit such as the DENT discrimination circuit 33 is required to be independent of each other, there is a drawback that the element scale is large and the cost when integrated is high. In particular, the quadrupling circuit 3
2 is often made by two-stage cascade coupling of multiplications, and a band pass filter is required between stages, which is a major factor in increasing the scale.

[0006]

In the conventional SECAM signal recording / reproducing circuit described above, the circuit scale is large and the cost is high.

The present invention provides a SECAM signal recording / reproducing circuit which realizes a low-cost recording / reproducing and discrimination processing circuit.

[0008]

According to the present invention, there is provided a voltage controlled oscillator circuit, a frequency divider circuit for dividing an oscillation signal of the voltage controlled oscillator circuit into quarters, an output of the frequency divider and the voltage control. A switching circuit that selects one of the outputs of the oscillator and a phase comparison circuit that inputs the output of the switching circuit to one input terminal and inputs the SECAM chroma signal to the other input terminal to compare the phases of these inputs. A means for controlling the oscillation frequency of the voltage controlled oscillation circuit based on the phase comparison output of the phase comparison circuit; an oscillation signal of the voltage controlled oscillation circuit at the time of recording, and a frequency division circuit at the time of reproduction,
And means for controlling the switching circuit.

[0009]

With the above-mentioned means, the discriminating circuit is configured by a PLL, and the quadruple function is realized by the PLL by combining the divide-by-four function and the quadrupling function to selectively switch the function between recording and reproduction. Therefore, an independent quadrupling circuit is not needed, and the effect of improving the cost is great.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit configuration diagram for explaining one embodiment of the present invention. The switch SW1 switches between the chroma signal applied to the recording input Rin and the chroma signal after the low frequency conversion applied to the reproduction input Pin. The chroma signal selected by the switch SW1 is connected to one input terminal of the phase comparison circuit 11. The phase comparison output is input to the voltage controlled oscillator (VCO) 12 and the VC
The oscillation frequency of O12 is controlled. The output signal of the VCO 12 is input to the divide-by-4 circuit 13, and the low-frequency converted VCO 12 is input.
And the oscillation signal of the VCO 12 itself are switched by the switch SW2. The signal selected by the switch SW2 is connected to the other input terminal of the phase comparison circuit 11. The output of the phase comparison circuit 11 is input to the integration circuit 14, and the 1 / 2fH signal created by the timing signal generation circuit (not shown) is multiplied and integrated to be output as the determination result. At the same time, the oscillation signal output of the VCO 12 is output from the reproduction output Pout, and the output divided by 4 is output to the recording output Rout.
Take each out.

First, at the time of recording, the switches SW1 and SW2
To the [R] side. Chroma signal of recording input Rin and VC
The output signal of O12 is supplied from the switches SW1 and SW2 to the phase comparison circuit 11. When the oscillation frequency of the VCO 12 is set to a range that allows sufficient oscillation in the band of the chroma signal input to the recording input Rin, the phase comparator circuit 11 and the VCO 12 form a PLL loop, and the VCO 12 records the recording input Rin.
Lock to the signal frequency of. At this time, a signal obtained by dividing the oscillation signal of the VCO 12 by 4 appears at the output of the divide-by-4 circuit 13, so that it becomes a chroma signal obtained by low-frequency conversion, and the recording output Ro
It can be taken out as a signal from ut.

In the case of reproduction, the switches SW1 and SW2
To the [P] side. The low-frequency-converted chroma signal of the reproduction input Pin and the oscillation signal of the VCO 12 divided by 4 are input to the phase comparison circuit 11. Also at this time, the phase comparator circuit 11 to VCO 12 to 4 frequency divider circuit 13
Since the loop is formed, the oscillation frequency of the VCO 12 is locked at a frequency four times as high as the chroma signal input to the reproduction input Pin that has been converted to the low frequency range. Therefore, the output signal of the VCO 12 can be taken out to the reproduction output Pout.

Regarding the determination, in either case of recording or reproduction, the information for controlling the VCO 12, that is, the FM demodulation output appears in the output of the phase comparison circuit 11. Therefore, this output is detected / detected as in Japanese Patent Laid-Open No. 3-210892. It can be taken out as the discrimination output by the integration operation.

In this embodiment, the PLL is realized by switching two different loops.
A circuit for performing multiplication is not required independently, and the 4 × circuit, which was the main factor of the soaring, can be deleted, resulting in a large cost reduction effect.

In addition, as shown in FIG. 2, another effect is obtained by switching the loop filter generally used for the output of the phase comparison circuit 11 at the time of recording / reproducing and using the frequency characteristic of the PLL loop in the optimum state. Can be expected. This will be described below.

As described above, the phase comparison circuit 1 is used during recording.
The signal frequency input to 1 is around 4 MHz (foB =
4.25 MHz), and the loop filter 21 is selected to have a relatively wide band so that the loop does not operate above this band. At the time of reproduction, the phase comparison circuit 11 operates near 1 MHz (foB = 1.07 MHz), but since the signal divided by 4 contains a distortion component that is an integral multiple of 1 MHz,
If it is operated as it is, mislock or spurious will occur. In this case, switching to the loop filter 22 and narrowing the band can prevent the above-mentioned performance deterioration. Therefore, even if the PLL loop is used for both recording and reproduction, no problem in terms of performance will occur.

[0018]

As described above, the SEC of the present invention
According to the AM recording / reproducing circuit, a low-cost recording / reproducing circuit for SECAM signals can be realized without causing a problem in performance.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of a SECAM recording / reproducing circuit of the present invention.

FIG. 2 is a block diagram showing a specific example of the phase comparison circuit shown in FIG.

FIG. 3 is a block diagram showing a conventional SECAM recording / reproducing circuit.

[Explanation of symbols]

 Rin ... Recording input Pin ... Reproduction input SW1, SW2 ... Switch 11 ..... Phase comparator circuit 12 ..... VCO 13 .....

Claims (4)

[Claims] 1. A voltage controlled oscillator circuit, a frequency divider circuit that divides an oscillation signal of the voltage controlled oscillator circuit into quarters, and one of an output of the frequency divider circuit and an output of the voltage controlled oscillator circuit. A switching circuit to be selected, a phase comparison circuit for inputting the output of the switching circuit to one input terminal and a SECAM chroma signal to the other input terminal for comparing the phases of these inputs, and Means for controlling the oscillation frequency of the voltage controlled oscillation circuit based on the phase comparison output; and means for controlling the switching circuit so as to select the oscillation signal of the voltage controlled oscillation circuit at the time of recording and the frequency dividing circuit at the time of reproduction. And a SECAM signal recording / reproducing circuit. 2. SECA based on the output of the phase comparison circuit
The S according to claim 1, wherein the M method is discriminated.
ECAM signal recording / reproducing circuit. 3. The loop filter included in the phase comparison circuit is switched during recording / reproducing.
The SECAM signal recording / reproducing circuit described. 4. A SECAM chroma signal is applied to the other input terminal of the phase comparison circuit via a second switching circuit that selects either the recording chroma signal or the reproduced chroma signal, and the switching circuit is turned on. The SECAM recording / reproducing circuit according to claim 1, wherein switching is performed by recording / reproducing.