JPH08130751A - Signal generation circuit - Google Patents

Abstract

PURPOSE: To perform signal generation by a DDS circuit suitable for being used in a multi-color TV receiver at a low cost. CONSTITUTION: Sine wave signals sampled from the output of the DDS circuit 50 are inputted to one side of the phase comparator 11 of a PLL circuit 10 constituted of the phase comparator 11, a loop filter 12 and a sine VCO 13. The comparison output of the phase comparator 11 is smoothed in the loop filter 12 and inputted to the sine VCO 13. The output of the sine VCO 13 is inputted to the other input of the phase comparator 11 and turned to sine wave output to an outside. A TV system discrimination circuit 20 for discriminating colors and black-and-white inputs a discriminated result as the state control signal of the PLL circuit 10. This signal generation circuit suitable for being used in the multi-color TV receiver is realized at a low cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generating circuit suitable for chroma signal processing of a color TV receiver.

[0002]

2. Description of the Related Art Conventionally, as a signal generation circuit of an arbitrary frequency, P. of "Design and Application of Oscillation Circuit" issued by CQ Publishing Co. 305-P. There is a direct synthesis digital synthesizer (hereinafter abbreviated as DDS circuit) circuit as described in 329. This block diagram is shown in FIG. full·
A DDS including a cumulative adder 51 including an adder and a latch, a sine ROM circuit 52 for converting the addition output data of the cumulative adder 51 into sine wave data, and a DA converter 53 for inputting the converted data and converting into an analog signal. It is composed of a circuit 50 and a low-pass filter (LPF) 54 that removes a high frequency unnecessary signal output from the DA converter 53.

A clock signal FCLK is input to the cumulative adder 51 from the outside, and the latch of data input in a clock cycle is repeated. The adder 51 adds and latches the addition data for obtaining the desired frequency signal and the result of the previous addition. When addition starts and reaches the overflow, the digits are lost and the original value is restored. In this way, a data string that increases in a sawtooth shape is obtained. This can be regarded equivalently as an oscillation circuit, and the oscillation frequency can be changed by externally controlling the addition data. The addition output data is converted into sine wave data by the sine ROM circuit 52. The sine ROM circuit 52 allocates and stores the amplitude information of the sine wave to an address, and regards the added data as an address and reads it. The DA converter 53 at the next stage converts the sine wave data into an analog signal and outputs a sampled sine wave signal.

When such a signal is normally used in the analog processing, the spurious component is removed because the spurious component still remains in the output of the DA converter 53. The LPF 54 does this.

On the other hand, color TV receivers, especially multi-mode T
In the case of a multi-color TV capable of receiving a V signal, different oscillation signals (color subcarrier = fs
c) is required. For example, in the case of a TV receiver capable of receiving the PAL system and the NTSC system, two frequency signals of the PAL system color subcarrier (fp = 4.433619MHz) and the NTSC system color subcarrier (fn = 3.579545MHz) are internally supplied. Play with. Since the color phase (TINT) control is performed in the chroma processing, it is desirable that the color subcarrier to be reproduced be a sine wave. A case where the DDS circuit 50 is used for this purpose will be described.

Now, the clock signal FCLK is set to 16 MHz.
Suppose you chose In the case of the DDS circuit 50, the cumulative adder 5
Since the addition is repeated for each clock signal FCLK at 1 to generate an arbitrary frequency, the DDS circuit 50 does not operate or the circuit scale becomes extremely complicated if the clock signal FCLK has a too high frequency. Also, fp and f
Since the subcarriers of each color of n are reproduced, the clock signal FC
LK must be more than twice these frequencies. FIG. 6 shows the appearance of spurious appearing in the output signal of the DA converter 53 of the DDS circuit 50 for this application.

Assuming that the DDS circuit 50 is oscillating on the color subcarrier fn, the clock signal F is output to its output.
CLK and (FCLK ± fn) components appear. Actually, there are spurs of 2FCLK or more, but here fsn
= Spurious of FCLK-fn only is described. When the color subcarrier fp is oscillating, the components of FCLK and (FCLK ± fp) are also visible. Similarly, there is a spurious of fsp = FCLK-fp. Here again, spurs of 2 FCLK or more are omitted. The unnecessary components other than these color subcarriers fn and fp are L
It is necessary to remove with PF54, and its characteristic example is shown in Fig. 6A.
Indicated as. Set the amount of unwanted signal attenuation to the desired signal to 4
In the case of taking 0 dB or more, the difference between fp and fsp is about twice, so that the LPF 54 has no choice but to be extremely steep.
An order higher than the order is required. In addition, when the LPF 54 has a built-in IC, the L
Since the shoulder frequency fo of the PF 54 varies and the amount of attenuation also varies, a separate correction is required.

FIG. 7 shows a more specific structural example of the LPF 54 that meets such requirements. An LPF is formed by connecting the secondary LPFs 71 to 73 in three stages in cascade.
The fo adjustment circuit 74 is provided for automatic adjustment of 1 to 73. Although there are various known examples of the fo adjustment circuit 74, they are omitted here.

In a signal generation circuit for a multi-color TV receiver using such a DDS circuit 50, the element scale of the LPF is large because the frequency characteristic does not depend on the variation of the built-in time constant, and the cost is high. There's a problem.
The number of filter circuits whose frequency characteristics can be controlled from the outside is about 100 elements in one stage of the secondary LPF, and 100 elements are required even if the fo automatic adjustment circuit is the most compact. Therefore, the LPF portion has 400 elements or more.

[0010]

DISCLOSURE OF THE INVENTION The conventional DDS described above
In the signal generation circuit for the multi-color TV receiver using the circuit, there is a problem that the element scale of the LPF that makes the frequency characteristic independent of the variation in the built-in time constant is large and the cost becomes high.

The present invention is to realize signal generation by a DDS circuit suitable for use in a multi-color TV receiver at low cost.

[0012]

In order to solve the above-mentioned problems, the present invention provides a sine VCO for the output of a DDS circuit.
Input to the PLL circuit equipped with the
As the output of the DS circuit, the above-mentioned object is achieved by performing the optimal control by the discrimination of the color system and the fsc switching signal.

[0013]

Since the PLL circuit is locked to the output signal of the DDS circuit by the means described above, the fo adjusting circuit is basically unnecessary, and the sine VCO itself can realize the secondary LPF with the element scale of one stage. Also, depending on each control signal, PL
Since the operation of the L circuit can be optimally controlled for the reception state,
It is possible to obtain a removal capacity equal to or higher than that of LPF.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram for explaining one embodiment of the present invention. The same parts as those in FIG. 5 will be described with the same reference numerals. The sine wave signal sampled from the output of the DDS circuit 50 is converted into a P signal composed of a phase comparator 11, a loop filter 12 and a sine VCO 13.
One is input to the phase comparator 11 of the LL circuit 10. The comparison output of the phase comparator 11 is smoothed by the loop filter 12 and input to the sine VCO 13. The output of the sine VCO 13 is input to the other input of the phase comparator 11 and used as an external sine wave output. The TV system discrimination circuit 20 for discriminating color / monochrome inputs the discrimination result as a state control signal of the PLL circuit 10.

The control method by the phase comparator 11 will be described with reference to FIG. The phase comparator 11 is a current source IB
And IC bias. Current source IB is switch S
It is connected to the phase comparator 11 via W1. Here, it is assumed that the phase comparator 11 is a current output type. DDS
The output of the circuit 50 and the sine wave signal from the sine VCO 13 are compared, and the comparison result is the loop filter 1
2 to the capacitors CC and CB, the resistor RB, and the bias source VB. The capacitor CC is connected to the output of the phase comparator 11 via the switch SW2 and the bias source VB via the switch SW3 and the resistor RB. Further, the output of the phase comparator 11 is supplied to the frequency control signal input terminal of the sine VCO 13.

At the time of black and white, the sine voltage V is applied to the DDS circuit 50.
CO13 needs to respond quickly, but when in color, L
It is necessary to prevent the phase change of the DDS circuit 50 from being tracked in the same manner as the removal by the PF. The control for realizing this will be described below.

In FIG. 2, the states of the switches SW1 to SW3 all indicate the color signal receiving state. First, in the case of black-and-white reception, both currents of the current sources IB and IC flow into the phase comparator 11. At this time, since the switch SW2 is open and the switch SW3 is closed on the output side, the resistor RB and the capacitor CB form a load circuit. The load circuit is a constant integral, and the voltage fluctuates up and down with the bias source VB as the center. At this time, the sine VCO 13 locks (captures) the sine wave signal from the DDS circuit 50.
When a color signal is received from this state, the system discrimination circuit 2
It is determined that 0 is color. By this discrimination signal, the switches SW1 to SW3 are switched to the states shown in FIG.
Then, the bias current of the phase comparator 11 is
It becomes only and sensitivity decreases. Also, the load circuit is CB + CC
It becomes only the capacity of and becomes indefinite integral.

If the current values of the current sources IB and IC are set in the relation of IB >> IC, the sensitivity of the phase comparator 11 can be high in black and white and extremely small in color. Further, by making the load circuit into indefinite (complete) integration, the cutoff frequency of the load circuit can be made DC, and the output signal of the comparison circuit due to minute phase noise or the like can be reduced. On the other hand, in black and white, the bias is given by RB to shorten the response time and make it easier to respond to noise.
It will lock securely.

As a setting for color, when the current of the current source IC is small and CC + CB is large, the PLL circuit system becomes D
It becomes difficult to follow the DS circuit 50, and the final signature VCO
The characteristic of the output signal of 13 is equivalent to passing through a narrow band pass filter (BPF). This time constant is the number 1
It can be built up to 0 horizontal line periods, and in this order it will not respond to the spurious of the DDS circuit 50 and will show better performance than filtering out.

The peripheral circuit of the sine VCO 13 will be described with reference to FIG. Sine VCO 13 is assumed to be of the current control type. The output of the phase comparator 11 is converted into a current by the voltage-current (VI) converter 31. Here, the control current Δi is supplied. On the other hand, current sources In and Ip that provide the initial oscillation frequency are prepared, and the color subcarrier fn
And fp oscillation are obtained. The control current Δi is added by the adder 32 via the switch SW4 and supplied to the sine VCO 13. Since the control signal for switching the oscillation frequency in the DDS circuit 50 exists inside, that signal is also used as the switching signal of the switch SW4. In this way, since the initial oscillation signal of the sine VCO 13 is switched, it becomes easier for the phase comparator 11 to capture, and the PLL
Locking of the circuit 10 can be avoided.

FIG. 4 shows a concrete circuit configuration diagram of the sine VCO, and the scale of the number of elements will be described. The output of the amplifier 41 having positive and negative input terminals is connected to the positive input terminal of the amplifier 41 and the input terminal of the secondary trap filter 42. Two
The output of the next trap filter 42 is connected to the negative input terminal of the amplifier 41, and the frequency control terminal 43 is used as the oscillation frequency control terminal of the sine VCO 13. Amplifier 4 with trap frequency
The signal at the negative input terminal of 1 is maximally attenuated, but reaches the positive input terminal as it is, so that a signal level difference is generated and the gain is maximized as a differential input. Utilizing this, the gain is set in the amplifier 41 so that stable oscillation continues.
Looking at the differential input, it is not a trap but a bandpass, and if the signal at the differential input terminal is amplified by a separate linear amplifier, the sine wave oscillation signal can be extracted.

As described above, the sine VCO 13 also has one stage of 2
It can be configured by the next trap filter 42 and a simple amplifier 41, and the element scale is about 120 elements. Also, since the phase comparator 11 also has one stage of the analog multiplication circuit, 5
It can be composed of about 0 elements. Therefore, the total size is reduced to about 200 elements, and the scale can be reduced by half compared to the conventional one.

[0023]

As described above, if the signal generating circuit of the present invention is used, it is possible to realize signal generation by a DDS circuit suitable for use in a multi-color TV receiver at low cost.

[Brief description of drawings]

FIG. 1 is a system diagram for explaining an embodiment of a signal generation circuit by a DDS circuit of the present invention.

FIG. 2 is a circuit diagram for more specifically explaining the phase comparator of FIG.

FIG. 3 is a circuit diagram for explaining a VCO peripheral circuit of FIG.

FIG. 4 is a circuit diagram for explaining a specific example of a VCO.

FIG. 5 is a system diagram showing a signal generation circuit using a conventional DDS circuit.

FIG. 6 is a frequency layout diagram showing spurious of a DDS circuit for multi-color TV application.

7 is a block diagram for explaining a more specific configuration example of the LPF of FIG.

[Explanation of symbols]

50 ... DDS circuit, 10 ... PLL circuit, 11 ... Phase comparator, 12 ... Trap filter, 13 ... Sine VCO, 2
0 ... Method discrimination circuit, IB, IC ... Current source, CC, CB ...
Capacitor, VB ... Bias source, SW1 to SW4 ... Switch, 31 ... VI converter, 32 ... Adder, 41 ... Amplifier, 42 ... Secondary trap filter, 43 ... Frequency control terminal.

Claims (6)

[Claims] 1. A digital synthesizer for generating a data string in which input data changes in a sawtooth shape, converting the sawtooth data string into a triangular wave or trapezoidal wave data string, and then converting the analog signal and outputting the analog signal. A PLL circuit having at least a VCO, a phase comparator, and a loop filter; and a discrimination circuit for discriminating a TV signal system. An analog output of the digital synthesizer circuit is supplied to the PLL circuit. A signal generation circuit comprising: means for obtaining an output of a VCO signal according to the discrimination result of the TV system signal discrimination circuit. 2. The digital synthesizer circuit signal comprises:
2. The signal generating circuit according to claim 1, wherein the color subcarrier frequencies based on different TV systems are switched and generated. 3. The signal generating circuit according to claim 1, wherein the VCO has a sine wave oscillation output. 4. The signal generating circuit according to claim 1, wherein the phase comparator is provided with a control terminal for comparison sensitivity, and the sensitivity is switched by the output of the discrimination circuit. 5. The signal generating circuit according to claim 1, wherein the loop filter has a time constant switching terminal, and the time constant is switched by the output of the discrimination circuit. 6. The signal generating circuit according to claim 1, wherein the VCO has a control terminal for an initial oscillation frequency, and the VCO is controlled by a frequency switching signal of the digital synthesizer circuit.