JPH07235610A - Manufacture of cmos type semiconductor device - Google Patents

Abstract

PURPOSE:To simultaneously activate the P and N type layers of a source/drain diffusion layer by a method wherein P-type and N-type impurities are implanted under the specific projection range ion implanting condition and they are heat- treated at the specific temperature. CONSTITUTION:Ions are implanted under the condition of P-type impurity projection flying distance of 0.02mum or smaller and N-type impurity projection flying distance of 0.03mum or smaller at 900 deg.C or higher. A well-element isolation region 4, a gate oxide film 6 and a polysilicon gate electrode 8 are formed on a silicon substrate 2, an NMOS transistor region is covered by a resist layer, and P-type impurities are implanted into an ionimplantation region 12. BF2 ions of dosage 3X10<15>/cm<2> are implanted by the implantation energy of 10Kev. A resist layer 10 is removed, the PMOS region is covered by a resist layer 14, As ions of dosage of 6X10<15>/cm<2> are implanted into an ion implantation region 16 using the implantation energy of 40Kev, and a heat treatment is conducted at 900 deg.C for thirty minutes. As a result, both ion implantation regions 12 and 16 are activated simultaneously, and source/drain regions 12a and 16a can be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a CMOS type semiconductor device.

[0002]

2. Description of the Related Art When ions are implanted into a single crystal silicon substrate, the silicon substrate is made amorphous to a depth determined by the implantation conditions. At this time, the boundary between the amorphized region (A) and the single crystal region (C) (A /
A large number of minute defects such as point defects occur near the (C interface). The microdefects serve as nuclei to form residual defects (= dislocation loops) after the heat treatment. When this residual defect occurs near the bonding position (bonding depth xj from the substrate surface),
The depletion layer of the PN junction is applied to generate a junction leak current.

In order to prevent the occurrence of this junction leakage current, it is sufficient to suppress the occurrence of residual defects by high temperature heat treatment and to sufficiently diffuse the implanted impurities to deepen the junction position and separate it from the residual defect position. However, the method of deepening the junction position is contrary to the trend of forming a shallow junction depth xj with the recent high integration of LSI.

As an example of a manufacturing process of a CMOS type semiconductor device which is generally performed, in order to form an N-type layer of a source / drain diffusion layer, arsenic ions as N-type impurities are 6 × 10 at 40 KeV. Implant ¹⁵ / cm ² and activate at 900 ° C. for 60 minutes. On the other hand, in order to form a P-type layer of the source / drain diffusion layer, BF ₂ ions as a P-type impurity are implanted at 40 KeV at 3 × 10 ¹⁵ / cm ² , and activation is performed at 850 ° C. for 30 minutes. In the source / drain diffusion layer formed under these conditions, the junction depth xj is about 0.19 μm for both N-type and P-type, and the defect position is about 0.04 μm from the substrate surface. Since the activation temperature of the P-type diffusion layer is set to be low in order to make the junction depth xj shallow, many defects occur, and as a result, leak current is likely to occur.

Further, as is apparent from this example, activation of the P-type layer and the N-type layer is carried out in a separate process due to the difference in the characteristics of the impurities. That is, the P-type layer is activated at a low temperature for a short time, and the N-type layer is activated at a high temperature for a long time.
This is because boron, which is a P-type layer forming element, has a larger diffusion coefficient than arsenic, which is an N-type layer forming element, and when the N-type layer is activated at a low temperature, the leak current further increases and the characteristics deteriorate. is there. Generally, the activation temperature is about 800 for the P-type layer.
850 ° C., and the N-type layer has a temperature of 900 to 950 ° C. If the activation of the P-type layer and the N-type layer is performed in separate steps, the number of steps increases.

[0006]

SUMMARY OF THE INVENTION A first object of the present invention is to suppress residual defect generation itself by sufficiently diffusing implanted impurities at a high temperature, and to separate the residual defect generation position and the junction position from each other to leak current. Is to be suppressed and the requirement for the shallow junction depth xj measured from the gate oxide film is also satisfied. A second object of the present invention is to reduce the number of heat treatment steps for activation by enabling activation of the P-type layer and the N-type layer of the source / drain diffusion layer at the same time. A third object of the present invention is to further reduce the number of steps by simultaneously activating the P-type layer and the N-type layer of the source / drain diffusion layer and simultaneously forming the gate oxide film.

[0007]

According to the present invention, in forming a P-type diffusion layer and an N-type diffusion layer by impurity ion implantation and heat treatment, both implanted impurities are sufficiently diffused by heat treatment at high temperature to generate residual defects themselves. Is suppressed, the defect generation position and the junction position are separated, and the P-type diffusion layer and the N-type diffusion layer are activated at the same time.

According to the first aspect of the present invention, the ion implantation for forming the source / drain diffusion layer has a projected range Rp of P-type impurities of 0.02 μm or less and a projected range Rp of N-type impurities.
Under an implantation condition of 0.03 μm or less, and both implanted impurities are simultaneously activated at a temperature of 900 ° C. or more. The implantation energy for the implantation conditions for setting the projection range Rp as described above is 15 KeV or less for BF ₂ ion implantation and 40 KeV or less for arsenic ion implantation, and the dose amount is determined by the required diffusion layer resistance. But 1 × 10 ^{15 to} 6 ×
It is 10 ¹⁵ / cm ² .

According to the second aspect of the invention, before the ion implantation for forming the source / drain diffusion layer, Si or Ge is implanted in the source / drain diffusion layer forming region to make the substrate surface amorphous.

According to the third aspect of the invention, before the ion implantation for forming the source / drain diffusion layers, the gate electrode forming region of the active region of the substrate is etched to a depth of 200.
A hole with a width of 0 to 3000 Å and a width of 0.3 to 0.8 μm is opened, an oxide film is formed on the inner surface of the hole by thermal oxidation, and then the hole is filled with a conductive layer to form a gate electrode, which is then activated. Impurities for forming the source / drain diffusion layer are ion-implanted into the region, and both implanted impurities are simultaneously activated at a temperature of 900 ° C. or higher.

According to the invention of claim 4, after the impurities for forming the source / drain diffusion layers are ion-implanted into the active region of the substrate, the gate electrode forming region of the active region of the substrate is etched to a depth of 2000 to 3000Å. Width is 0.3 ~
A 0.8 μm hole is formed and an oxide film is formed on the inner surface of the hole by thermal oxidation. At the same time, both implanted impurities are activated to form a source / drain diffusion layer. The oxygen concentration is adjusted to, for example, about 10% at the time of gate oxidation, and conditions are set so that an oxide film is formed at 100 to 120Å by the treatment at 900 to 950 ° C.

[0012]

According to the first aspect of the present invention, the implantation profile of the implantation impurities for forming the source / drain diffusion layer is suppressed to be shallow, and the increase of the junction depth xj due to the high temperature heat treatment is prevented. for that reason,
The implantation energy is lowered so as to reduce the projection range Rp. Such low-energy implantation not only suppresses the implantation profile shallow (reduces the projection range Rp), but also thins the amorphous layer formed by this implantation to move the defect occurrence position to the substrate surface side. There is also an effect. That is, since the A / C interface shifts to the surface side due to the reduction in energy, it becomes farther from the bonding position formed on the deep side of the substrate as viewed from the defect position. Also,
Since both implanted impurities are activated simultaneously, the number of steps is reduced.

As described in claim 2, impurity implantation is performed by making the surface of the substrate amorphous (preamorphous) by implanting neutral atoms such as Si or Ge before implanting P-type impurities and N-type impurities. It is possible to prevent channeling at the time and form the implantation profile with a shallower depth. When preamorphization is performed, depending on the implantation conditions, a large amount of interstitial Si generated causes accelerated oxidation during heat treatment, which makes the impurity profile more likely to diffuse. However, the present invention causes more diffusion of impurities. This is not a problem as it is necessary.

According to a third aspect of the present invention, a hole is formed in the substrate by etching, and a conductive electrode material such as polysilicon having a reduced resistance introduced by impurities is embedded therein to form a gate electrode. Therefore, even if the P-type diffusion layer and the N-type diffusion layer are sufficiently diffused, since the gate electrode is buried, the effective junction depth x measured from the gate oxide film x
j can be adjusted by the thickness of the gate electrode and can be formed shallowly. Therefore, the junction position and the defect position can be sufficiently separated from each other without performing the low energy implantation, and at the same time, the shallow junction depth xj can be obtained. Although the implantation energy depends on the thickness of the buried gate electrode, for example, B
40 KeV or more by F ₂ ion implantation, 6 by arsenic ion implantation
It can be 0 KeV or more.

According to a fourth aspect of the present invention, P-type impurity ions and N-type impurity ions are implanted before the gate oxidation, and both implanted impurities are activated during the gate oxidation. As a result, the P-type diffusion layer and the N-type diffusion layer can be activated simultaneously with the formation of the gate oxide film.

[0016]

FIG. 1 shows an embodiment relating to the invention of claim 1. (A) A well (not shown) is formed in the silicon substrate 2, an element isolation region 4 is formed, a gate oxide film 6 is formed, and a polysilicon gate electrode 8 is formed. In order to perform P-type impurity implantation in the PMOS transistor formation region, an NMOS
The transistor formation region is covered with a resist layer 10 by lithography, an opening is provided in the PMOS transistor formation region, and a P-type impurity is implanted into the substrate 2. BF ₂ ions were used as the implanted ion species, and the implantation conditions were an implantation energy of 10 KeV and a dose amount of 3 × 10 ¹⁵ / cm ² . 1
Reference numeral 2 is a BF ₂ ion implantation region.

(B) Next, the resist layer 10 is removed, lithography is performed to cover the PMOS transistor formation region with the resist layer 14, an opening is provided in the NMOS transistor formation region, and N-type impurities are implanted into the substrate 2. To do.
As ions are used as the implantation ion species, and the implantation conditions are an implantation energy of 40 KeV and a dose amount of 6 × 10 ¹⁵ / cm 3.
² 16 is an As ion implantation region.

(C) In order to simultaneously activate the implanted P-type impurities and N-type impurities, heat treatment is performed at 900 ° C. for 30 minutes. As a result, both the ion implantation regions 12 and 16 are activated and the source / drain regions 12a and 16 are respectively activated.
a. The defect generation positions 18 and 20 and the bonding positions of the P-type diffusion layer 12a and the N-type diffusion layer 16a are as follows.

[0019]

[Table 1]

Compared with the conventional source / drain diffusion layer formed by the general process described above, the junction position is almost the same, but the P-type diffusion layer is also activated at a high temperature, so that a leak current is generated. Hateful. In addition, P-type impurities and N
Since the type impurities are simultaneously activated, the number of heat treatment steps can be reduced.

In the embodiment shown in FIG. 1, Si is 20 KeV before ion implantation for forming source / drain diffusion layers on a substrate on which well formation, element isolation, gate oxide film formation and gate electrode formation have been performed in step (A). Then, 3 × 10 ¹⁵ / cm ^{2 is} injected to amorphize the substrate surface. Then, steps (A) to (C) shown in FIG. 1 are performed. This allows
The junction depth xj of the P-type diffusion layer 12a is set to 0.17 to 0.18 μm.
It can be reduced to about m.

FIG. 2 shows an embodiment corresponding to claim 3. (A) On the substrate 2 on which the wells have been formed and the elements have been separated, by lithography and etching, the depth is about 2000 Å and the width is about 400 in the gate electrode formation region of the NMOS transistor and the gate electrode formation region of the PMOS transistor.
Drill 0Å holes 24 and 26. Next, change the oxygen concentration to 10%
The treatment is performed at a treatment temperature of about 900 ° C. for 50 minutes in an atmosphere adjusted to a certain degree. Due to this thermal oxidation, holes 24, 26
An oxide film 28 having a thickness of about 110Å is formed on the inner wall surface of the. Among the oxide films 28 formed on the inner wall surfaces of the holes 24 and 26, the oxide film 28 on the bottom surface of the holes serves as a gate oxide film.

(B) The polysilicon layer 38 whose resistance has been lowered by introducing impurities into the holes 24 and 26 is used as a buried gate electrode. (C) In order to perform P-type impurity implantation into the PMOS transistor formation region, the NMOS transistor formation region is covered with a resist layer 10 by lithography, an opening is provided in the PMOS transistor formation region, and the P-type impurity is implanted into the substrate 2. . BF ₂ ions are used as the implantation ion species, and the implantation conditions are an implantation energy of 50 KeV and a dose amount of 5 ×.
It was set to 10 ¹⁵ / cm ² . Reference numeral 20 is a BF ₂ ion implantation region.

(D) Next, the resist layer 10 is removed, lithography is performed to cover the PMOS transistor formation region with the resist layer 14, an opening is provided in the NMOS transistor formation region, and N-type impurities are implanted into the substrate 2. To do.
As ions are used as the implantation ion species, and the implantation conditions are implantation energy of 70 KeV and dose of 6 × 10 ¹⁵ / cm 3.
² 22 is an As ion implantation region.

(E) After removing the resist layer 14, 90
The treatment is performed at a treatment temperature of about 0 ° C. for 50 minutes. By this heat treatment, both implantation regions 20 and 22 are activated, and
The drain diffusion layers 20a and 22a are formed. Defects may occur at the positions 34 and 36 of the implantation regions 20 and 22 before activation.

By the process of FIG. 2, the effective junction depth xj can be suppressed to about 0.1 μm, and at the same time, the junction position and the defect position can be separated by 0.2 μm or more. Further, activation of the P-type diffusion layer and activation of the N-type diffusion layer can be performed simultaneously.

FIG. 3 shows an embodiment corresponding to claim 4. (A) PMO of substrate 2 after well formation and element isolation
In order to perform P-type impurity implantation into the S-transistor forming region, lithography is performed to cover the NMOS transistor forming region, an opening is formed in the PMOS transistor forming region, and P-type impurities are implanted into the substrate 2. BF ₂ ions are used as the implantation ion species, and the implantation conditions are an implantation energy of 50 KeV and a dose amount of 5 × 10 ¹⁵ / cm 3.
² Reference numeral 20 is a BF ₂ ion implantation region.

(B) Next, the resist layer 10 is removed, lithography is performed to cover the PMOS transistor formation region with the resist layer 14, an opening is provided in the NMOS transistor formation region, and N-type impurities are implanted into the substrate 2. To do.
As ions are used as the implantation ion species, and the implantation conditions are implantation energy of 70 KeV and dose of 6 × 10 ¹⁵ / cm 3.
² 22 is an As ion implantation region.

(C) After removing the resist layer 14, by lithography and etching, the depth is about 2000 Å and the width is about 400 in the gate electrode formation region of the NMOS transistor and the gate electrode formation region of the PMOS transistor.
Drill 0Å holes 24 and 26.

(D) The treatment is carried out at a treatment temperature of about 900 ° C. for 50 minutes in an atmosphere in which the oxygen concentration is adjusted to about 10%. By this thermal oxidation, an oxide film 28 having a thickness of about 110Å is formed on the inner wall surfaces of the holes 24, 26, and at the same time, both implantation regions 20, 22 are activated and become the source / drain diffusion layers 20a, 22a. Implanted regions 20, 2 before activation
Defects may occur at the second positions 34 and 36. Among the oxide films 28 formed on the inner wall surfaces of the holes 24 and 26, the oxide film 28 on the bottom surface of the holes serves as a gate oxide film.

(E) The polysilicon layer 38 whose resistance has been lowered by introducing impurities into the holes 24 and 26 is used as a buried gate electrode. Also by the process of FIG. 3, the effective junction depth xj can be suppressed to about 0.1 μm, and at the same time, the junction position and the defect position can be separated by 0.2 μm or more. Further, activation of the P-type diffusion layer, activation of the N-type diffusion layer and formation of the gate oxide film can be performed simultaneously.

[0032]

According to the present invention, when the P-type diffusion layer and the N-type diffusion layer are formed by the impurity ion implantation and the heat treatment, both the implanted impurities are sufficiently diffused by the high temperature heat treatment to suppress the generation of residual defects themselves. Since the defect generation position and the junction position are separated from each other and the P-type diffusion layer and the N-type diffusion layer are activated at the same time, it is possible to suppress the generation of leak current and to reduce the junction depth xj. The number of heat treatment steps for activation can be reduced. If the impurity ions for the source / drain diffusion layer are implanted before the gate oxidation and both implanted impurities are activated during the gate oxidation, the diffusion layer is activated at the same time as the gate oxide film is formed. The number of steps can be further reduced.

[Brief description of drawings]

FIG. 1 is a process sectional view showing an embodiment corresponding to claim 1.

FIG. 2 is a process sectional view showing an embodiment corresponding to claim 3;

FIG. 3 is a process sectional view showing an embodiment corresponding to claim 4;

[Explanation of symbols]

2 Silicon substrate 6,28 Gate oxide film 8,38 Polysilicon gate electrode 12, 16, 20, 22 Impurity ion implantation layer 12a, 16a, 20a, 22a Source / drain diffusion layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 29/78 21/336 9170-4M H01L 27/08 321 D 7514-4M 29/78 301 Y

Claims (4)

[Claims] 1. An impurity is ion-implanted into a silicon substrate,
In a method of manufacturing a CMOS type semiconductor device in which a source / drain diffusion layer is activated by heat treatment to form a source / drain diffusion layer, in the ion implantation, a projected range of P type impurities is 0.02 μm.
Hereinafter, a method of manufacturing a CMOS type semiconductor device, characterized in that the implantation range of the N-type impurities is set to 0.03 μm or less, and both the implanted impurities are simultaneously activated at a temperature of 900 ° C. or higher. 2. A source / source before the ion implantation.
The CMO according to claim 1, wherein Si or Ge is injected into the drain diffusion layer formation region to make the substrate surface amorphous.
Manufacturing method of S-type semiconductor device. 3. An impurity is ion-implanted into a silicon substrate,
In a method of manufacturing a CMOS type semiconductor device in which a source / drain diffusion layer is activated by heat treatment to form a source / drain diffusion layer, a depth of 2000 to 3000Å and a width of 0. A hole of 3 to 0.8 μm is formed, an oxide film is formed on the inner surface of the hole by thermal oxidation, the hole is filled with a conductive layer to form a gate electrode, and then a source / drain diffusion layer is formed in the active region. A method for manufacturing a CMOS type semiconductor device, characterized in that the impurities are implanted by ion implantation, and both the implanted impurities are heat-treated at a temperature of 900 ° C. or higher to be simultaneously activated. 4. Impurity ion implantation into a silicon substrate,
In a method of manufacturing a CMOS semiconductor device in which a source / drain diffusion layer is activated by heat treatment to form a source / drain diffusion layer, an impurity for forming a source / drain diffusion layer is ion-implanted into an active region of a substrate, and then a gate electrode of the active region of the substrate is formed. The formation area is etched to a depth of 2000-300
A hole of 0Å and a width of 0.3 to 0.8 μm is formed, an oxide film is formed on the inner surface of the hole by thermal oxidation, and at the same time, both implanted impurities are activated to form a source / drain diffusion layer. Method of manufacturing CMOS semiconductor device.