JPH07235556A - Analyzing method of semiconductor device - Google Patents
Analyzing method of semiconductor deviceInfo
- Publication number
- JPH07235556A JPH07235556A JP6027932A JP2793294A JPH07235556A JP H07235556 A JPH07235556 A JP H07235556A JP 6027932 A JP6027932 A JP 6027932A JP 2793294 A JP2793294 A JP 2793294A JP H07235556 A JPH07235556 A JP H07235556A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor device
- die pad
- etching
- silver paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01011—Sodium [Na]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Weting (AREA)
- Die Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、樹脂封止型の半導体装
置の組み立て工程におけるダイスボンド後の半導体チッ
プとダイパッドとの接合状態を解析するための半導体装
置の解析方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of analyzing a semiconductor device for analyzing a bonding state between a semiconductor chip and a die pad after die bonding in a process of assembling a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】従来、半導体装置はその組み立て工程に
おいて、ダイスボンド装置により、銀ペーストを用いて
半導体チップとダイパッドとを接合し、次にワイヤーボ
ンディング装置により金線、Ａｌ線等で半導体チップ上
のＡｌ電極とリードフレームによって保持されているリ
ード線の一端とを電気的に接続し、エポキシ樹脂で全体
を封止することによってパッケージングされて完成して
いた。2. Description of the Related Art Conventionally, in the process of assembling a semiconductor device, a semiconductor chip and a die pad are joined together using a silver paste by a dice bonding device, and then a gold wire, an Al wire or the like is used on the semiconductor chip by a wire bonding device. The Al electrode was electrically connected to one end of the lead wire held by the lead frame, and the whole was encapsulated with an epoxy resin to complete the packaging.
【０００３】図４は樹脂封止型半導体装置の全体構造を
示している。図４において、半導体チップ１は、ダイパ
ッド２上に載置され、前記半導体チップ１とダイパッド
２とは銀ペースト３によって接合され、電気的接続され
た後、金ワイヤー４によって前記半導体チップ１上の周
辺部分に設けられたＡｌ電極（図示せず）と外部のリー
ドフレーム５とを電気的に接続し、その全体をエポキシ
樹脂などのパッケージ樹脂６で被覆していた。FIG. 4 shows the overall structure of a resin-sealed semiconductor device. In FIG. 4, a semiconductor chip 1 is placed on a die pad 2, the semiconductor chip 1 and the die pad 2 are joined by a silver paste 3 and electrically connected, and then on the semiconductor chip 1 by a gold wire 4. An Al electrode (not shown) provided in the peripheral portion was electrically connected to an external lead frame 5, and the whole was covered with a package resin 6 such as an epoxy resin.
【０００４】以上のように構成された半導体装置の信頼
性を確保するためには、その製品の一部を抜き取り、半
導体チップ１とダイパッド２とでの銀ペースト３の接合
状態（ヌレ状態）を検査する必要性がある。そのため従
来は図５に示すように、半導体装置を上方向からＸ線透
視装置を用い、半導体チップ１とダイパッド２との接合
剤である銀ペースト３の接合状態の評価を行なってい
た。In order to ensure the reliability of the semiconductor device configured as described above, a part of the product is extracted and the bonding state (wet state) of the silver paste 3 between the semiconductor chip 1 and the die pad 2 is changed. Need to be inspected. Therefore, conventionally, as shown in FIG. 5, the semiconductor device is evaluated from above by using an X-ray fluoroscope to evaluate the bonding state of the silver paste 3 which is the bonding agent between the semiconductor chip 1 and the die pad 2.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら前記従来
のようにＸ線透視装置を用いての解析方法では、半導体
チップを載置しているダイパッドに多数のスリット形状
などの特有な形状が設けられている場合、銀ペーストで
ダイパッドを全体に均一に接合させるには、非常に困難
であるということと、Ｘ線透視装置の性質上、銀ペース
トの末接合部がどのような接合状態になっているのか判
断できないという課題があった。However, in the analysis method using the X-ray fluoroscope as in the above-mentioned conventional technique, the die pad on which the semiconductor chip is mounted is provided with a unique shape such as a large number of slit shapes. When it is present, it is very difficult to evenly bond the die pad to the entire surface with the silver paste, and due to the nature of the X-ray fluoroscope, the end bonding portion of the silver paste is in a bonded state. There was a problem that I could not judge.
【０００６】本発明は前記従来の課題を解決するもの
で、半導体チップが載置されるダイパッドの形状がどの
ような形状であろうと、半導体チップとダイパッドとの
接合状態の解析が可能な半導体装置の解析方法を提供す
るものである。The present invention solves the above-mentioned conventional problems. A semiconductor device capable of analyzing the bonding state between the semiconductor chip and the die pad, regardless of the shape of the die pad on which the semiconductor chip is mounted. It provides the analysis method of.
【０００７】[0007]
【課題を解決するための手段】本発明は前記従来の課題
を解決するために、半導体装置のパッケージ樹脂を半導
体チップ表面が露出するまで研磨する工程と、前記半導
体チップをエッチング力の異なる２種類のエッチング液
でエッチングし、前記半導体チップのみを除去して前記
半導体チップを載置しているダイパッド表面を露出させ
る工程とを有し、前記半導体チップをエッチングする工
程は、エッチング力の強い第１液でエッチングし、つい
で前記第１液よりエッチング力の弱い第２液でエッチン
グする工程であり、好ましくは第１液は弗酸と硝酸との
混合溶液を用い、第２液は水酸化ナトリウム溶液を用い
てエッチングし、前記半導体チップのみを除去して前記
半導体チップを載置しているダイパッド表面を露出させ
る工程であることを特徴とするものである。In order to solve the above-mentioned conventional problems, the present invention comprises a step of polishing a package resin of a semiconductor device until the surface of the semiconductor chip is exposed, and two types of the semiconductor chip having different etching forces. Etching with the etching solution of 1) to remove only the semiconductor chip to expose the surface of the die pad on which the semiconductor chip is mounted. The step of etching the semiconductor chip is Etching with a liquid, and then etching with a second liquid having a weaker etching power than the first liquid, preferably the first liquid is a mixed solution of hydrofluoric acid and nitric acid, and the second liquid is a sodium hydroxide solution. A step of etching the semiconductor chip to remove only the semiconductor chip and expose the surface of the die pad on which the semiconductor chip is mounted. It is an feature.
【０００８】[0008]
【作用】前記構成により、シリコンだけをエッチングで
きる弗酸と硝酸との混合溶液でエッチングし、ついで水
酸化ナトリウム溶液でエッチングするので、半導体チッ
プのみをエッチング除去できるため、半導体チップが載
置されていたダイパッド上には、半導体チップとダイパ
ッドとの接合に用いた銀ペーストが接合時のままの形状
で残留し、その銀ペーストの状態から半導体チップとダ
イパッドとの接合状態を平面で自然観察することがで
き、その接合状態を正確に観察することができる。また
はじめは弗酸と硝酸との混合溶液で半導体チップの大部
分をエッチングし、ついで半導体チップの残りは前記弗
酸と硝酸との混合溶液よりもエッチング力の弱い水酸化
ナトリウム溶液でエッチングするので、半導体チップと
ダイパッドとの接合に用いた銀ペーストにダメージを与
えず、接合時のままの形状を保持することができる。な
お、本発明でいうエッチング力とは、半導体チップを溶
解する作用を意味し、本発明においては、第２液である
水酸化ナトリウム溶液は第１液である弗酸と硝酸との混
合溶液よりも前記作用が弱いものである。With the above construction, since etching is performed with a mixed solution of hydrofluoric acid and nitric acid capable of etching only silicon, and then with sodium hydroxide solution, only the semiconductor chip can be removed by etching, so that the semiconductor chip is mounted. On the die pad, the silver paste used for joining the semiconductor chip and the die pad remains in the same shape as when joined, and the joining state between the semiconductor chip and the die pad should be observed naturally on a plane from the state of the silver paste. The joining state can be accurately observed. Further, first, most of the semiconductor chip is etched with a mixed solution of hydrofluoric acid and nitric acid, and then the rest of the semiconductor chip is etched with a sodium hydroxide solution having a weaker etching power than the mixed solution of hydrofluoric acid and nitric acid. The silver paste used for joining the semiconductor chip and the die pad is not damaged and the shape as it is at the time of joining can be maintained. The etching power in the present invention means the action of dissolving the semiconductor chip, and in the present invention, the sodium hydroxide solution as the second liquid is more effective than the mixed solution of hydrofluoric acid and nitric acid as the first liquid. Also, the above-mentioned action is weak.
【０００９】[0009]
【実施例】以下、本発明の一実施例について図面を参照
しながら説明する。図１、図２および図３を参照しなが
ら本実施例について説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. This embodiment will be described with reference to FIGS. 1, 2 and 3.
【００１０】図１に示すように、まず半導体装置の外囲
器であるパッケージ樹脂６の表面をその内部に埋め込ま
れている半導体チップ１の表面が完全に露出するまで研
磨する（図面中、破線は研磨によって除去された部分を
示している）。次にまずエッチング力の強い第１液とし
て、弗酸と硝酸との混合溶液である弗硝酸液を用いて、
半導体チップ１の３／４程度が除去されるまでエッチン
グを行なう。この場合のエッチング時間としては、半導
体チップ１の厚さが４００［μｍ］程度である場合に
は、１〜２分間程度でよく、チップ厚によって適宜調整
する。また前記第１液である弗酸と硝酸との混合溶液で
ある弗硝酸液の混合比率は、本実施例では３：１つまり
弗酸が３に対して硝酸が１の混合比である。As shown in FIG. 1, first, the surface of the package resin 6 which is the envelope of the semiconductor device is polished until the surface of the semiconductor chip 1 embedded therein is completely exposed (in the drawing, the broken line). Indicates the part removed by polishing). Next, as a first liquid having a strong etching power, a fluorinated nitric acid liquid which is a mixed solution of hydrofluoric acid and nitric acid is used.
Etching is performed until about 3/4 of the semiconductor chip 1 is removed. In this case, when the thickness of the semiconductor chip 1 is about 400 [μm], the etching time may be about 1 to 2 minutes, and is appropriately adjusted depending on the chip thickness. Further, the mixing ratio of the fluorinated nitric acid solution, which is a mixed solution of the hydrofluoric acid and nitric acid, which is the first liquid, is 3: 1 in this embodiment, that is, the mixing ratio is 3 for hydrofluoric acid and 1 for nitric acid.
【００１１】次に第２液として、前記弗硝酸液よりエッ
チング力の弱い水酸化ナトリウム溶液を用いて半導体チ
ップ１を完全に除去する。この場合のエッチング時間と
しては、半導体チップ１の厚さが４００［μｍ］程度で
ある場合には、３〜５分間程度でよく、チップ厚によっ
て適宜調整する。また水酸化ナトリウム溶液の濃度も適
宜調整する。Next, the semiconductor chip 1 is completely removed by using, as the second liquid, a sodium hydroxide solution having an etching power weaker than that of the hydrofluoric nitric acid solution. In this case, the etching time may be about 3 to 5 minutes when the thickness of the semiconductor chip 1 is about 400 [μm], and is appropriately adjusted depending on the chip thickness. Also, the concentration of the sodium hydroxide solution is adjusted appropriately.
【００１２】またシリコンエッチング液である前記弗硝
酸液および水酸化ナトリウム溶液の性質上、半導体チッ
プ１のみをエッチングすることができ、その他のエポキ
シ樹脂からなるパッケージ樹脂６や前記半導体チップ１
とダイパッド２との接合に用いている銀ペースト３は除
去されない。そのため、これら複数種のエッチング液を
用いることにより、半導体チップ１のみを完全に除去で
きる。そして本実施例では、半導体チップ１の大部分を
エッチング力の強い前記弗硝酸液で除去してから、その
後に半導体チップ１のわずかな残りをエッチング力の弱
い水酸化ナトリウム溶液でゆるやかにエッチングして除
去しているので、目的とする半導体チップ１とダイパッ
ド２との接合に用いている銀ペースト３にダメージを極
力与えることなく、銀ペースト３形状を接合時のままの
形状で残留させて図２および図３に示すような試料を得
ることができる。Due to the nature of the fluorinated nitric acid solution and the sodium hydroxide solution which are silicon etching solutions, only the semiconductor chip 1 can be etched, and the package resin 6 made of other epoxy resin and the semiconductor chip 1 are also available.
The silver paste 3 used for bonding between the die pad 2 and the die pad 2 is not removed. Therefore, by using these plural kinds of etching solutions, only the semiconductor chip 1 can be completely removed. Then, in this embodiment, most of the semiconductor chip 1 is removed by the fluorinated nitric acid solution having a strong etching power, and thereafter, a small amount of the semiconductor chip 1 is gently etched by a sodium hydroxide solution having a weak etching power. Since the silver paste 3 used for joining the target semiconductor chip 1 and the die pad 2 is not damaged as much as possible, the shape of the silver paste 3 is left as it is at the time of joining. 2 and a sample as shown in FIG. 3 can be obtained.
【００１３】なお好ましくは前記各エッチング後にはエ
ッチング停止と洗浄のため水洗処理を施す。溶剤洗浄、
置換は、銀ペースト３の形状にダメージを与える可能性
があるので避ける。Preferably, after each of the above etchings, a water washing treatment is performed to stop the etching and wash. Solvent cleaning,
Substitution is avoided because it may damage the shape of the silver paste 3.
【００１４】このようにして得られた図２および図３に
示すような試料において、銀ペースト３とエポキシ樹脂
であるパッケージ樹脂６、パッケージ樹脂６ａは除去さ
れず、同図に示すように銀ペースト３の形状から半導体
チップ１とダイパッド２との接合状態や、パッケージ樹
脂６の封止の際に半導体チップ１とダイパッド２との隙
間に前記ダイパッド２に形成されたスリット２ａより入
り込んだパッケージ樹脂６ａの状態について、簡単に自
然観察することができる。そして接合状態評価に対して
精度よくフィードバックすることができ、信頼性評価を
向上できるものである。なお、図２および図３において
は、パッケージ樹脂６、パッケージ樹脂６ａ、銀ペース
ト３を図中で区別容易にするためにハッチングを付して
いる。In the samples thus obtained as shown in FIGS. 2 and 3, the silver paste 3 and the package resin 6 and the package resin 6a, which are the epoxy resin, were not removed. From the shape of 3, the bonding state of the semiconductor chip 1 and the die pad 2 and the package resin 6a inserted into the gap between the semiconductor chip 1 and the die pad 2 through the slit 2a formed in the die pad 2 when the package resin 6 is sealed. You can easily observe the state of. Then, it is possible to accurately feed back the bonding state evaluation and improve the reliability evaluation. 2 and 3, the package resin 6, the package resin 6a, and the silver paste 3 are hatched for easy distinction in the drawings.
【００１５】なお、本実施例において、評価対象の半導
体装置の構成材料中、銀ペーストの代わりに金、半田、
非絶縁性材料を用いても本実施例の効果があることは勿
論である。In this embodiment, in the constituent materials of the semiconductor device to be evaluated, gold, solder,
Needless to say, the effect of this embodiment can be obtained even if a non-insulating material is used.
【００１６】[0016]
【発明の効果】本発明は半導体装置のパッケージ樹脂と
半導体チップとを銀ペーストとダイパッドとの接合面に
対して研磨、２段階エッチングして除去することによ
り、銀ペースト形状より半導体チップとダイパッドとの
接合状態を平面的に自然観察、評価でき、ダイスボンド
時における工程管理と半導体装置の品質向上を図ること
ができる。According to the present invention, the package resin and the semiconductor chip of the semiconductor device are removed by polishing and two-step etching on the bonding surface between the silver paste and the die pad, thereby removing the semiconductor chip and the die pad from the silver paste shape. It is possible to naturally observe and evaluate the bonding state in a plane, and it is possible to improve the quality of the semiconductor device and process control during die bonding.
【図１】本発明の一実施例にかかる半導体装置の解析方
法における半導体装置の研磨を示す斜視図FIG. 1 is a perspective view showing polishing of a semiconductor device in a semiconductor device analysis method according to an embodiment of the present invention.
【図２】本発明の一実施例にかかる半導体装置の解析方
法における半導体装置のエッチング後の平面図FIG. 2 is a plan view of the semiconductor device after etching in the semiconductor device analysis method according to the embodiment of the present invention.
【図３】本発明の一実施例にかかる半導体装置の解析方
法における半導体装置のエッチング後の拡大平面図FIG. 3 is an enlarged plan view of the semiconductor device after etching in the semiconductor device analysis method according to the embodiment of the present invention.
【図４】樹脂封止型半導体装置の構成を示す図FIG. 4 is a diagram showing a configuration of a resin-sealed semiconductor device.
【図５】従来の半導体装置の解析方法における半導体装
置のＸ線透視を示す上面図FIG. 5 is a top view showing X-ray see-through of a semiconductor device in a conventional semiconductor device analysis method.
１ 半導体チップ ２ ダイパッド ２ａ スリット ３ 銀ペースト ４ 金ワイヤー ５ リードフレーム ６ パッケージ樹脂 1 Semiconductor Chip 2 Die Pad 2a Slit 3 Silver Paste 4 Gold Wire 5 Lead Frame 6 Package Resin
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/66 Ｓ 7630−4Ｍ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display location H01L 21/66 S 7630-4M
Claims (3)
ップ表面が露出するまで研磨する工程と、表面出しされ
た前記半導体チップをエッチング力の異なる２種類のエ
ッチング液でエッチングし、前記半導体チップのみを除
去して前記半導体チップを載置しているダイパッド表面
を露出させる工程とを有することを特徴とする半導体装
置の解析方法。1. A step of polishing a package resin of a semiconductor device until a surface of a semiconductor chip is exposed, and the exposed semiconductor chip is etched with two kinds of etching solutions having different etching powers to remove only the semiconductor chip. And exposing the surface of the die pad on which the semiconductor chip is mounted.
ップ表面が露出するまで研磨する工程と、表面出しされ
た前記半導体チップを第１液でエッチングし、ついで前
記第１液よりエッチング力の弱い第２液でエッチング
し、前記半導体チップのみを除去して前記半導体チップ
を載置しているダイパッド表面を露出させる工程とを有
することを特徴とする請求項１記載の半導体装置の解析
方法。2. A step of polishing a package resin of a semiconductor device until a surface of a semiconductor chip is exposed, the exposed semiconductor chip is etched with a first liquid, and then a second weaker etching power than the first liquid is used. 2. A method of analyzing a semiconductor device according to claim 1, further comprising the step of etching with a liquid to remove only the semiconductor chip to expose a surface of a die pad on which the semiconductor chip is mounted.
ップ表面が露出するまで研磨する工程と、表面出しされ
た前記半導体チップを弗酸と硝酸との混合溶液でエッチ
ングし、ついで水酸化ナトリウム溶液でエッチングし、
前記半導体チップのみを除去して前記半導体チップを載
置しているダイパッド表面を露出させる工程とを有する
ことを特徴とする請求項１記載の半導体装置の解析方
法。3. A step of polishing a package resin of a semiconductor device until a surface of a semiconductor chip is exposed, the exposed semiconductor chip is etched with a mixed solution of hydrofluoric acid and nitric acid, and then with a sodium hydroxide solution. Then
2. The method for analyzing a semiconductor device according to claim 1, further comprising: removing only the semiconductor chip to expose a surface of a die pad on which the semiconductor chip is mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6027932A JPH07235556A (en) | 1994-02-25 | 1994-02-25 | Analyzing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6027932A JPH07235556A (en) | 1994-02-25 | 1994-02-25 | Analyzing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07235556A true JPH07235556A (en) | 1995-09-05 |
Family
ID=12234675
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6027932A Pending JPH07235556A (en) | 1994-02-25 | 1994-02-25 | Analyzing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07235556A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016046995A1 (en) * | 2014-09-22 | 2016-03-31 | 日本サイエンティフィック株式会社 | Plastic-molded semiconductor integrated circuit package unsealing method and unsealing device |
| CN110660689A (en) * | 2019-09-11 | 2020-01-07 | 大同新成新材料股份有限公司 | Die bonding method of semiconductor element |
-
1994
- 1994-02-25 JP JP6027932A patent/JPH07235556A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016046995A1 (en) * | 2014-09-22 | 2016-03-31 | 日本サイエンティフィック株式会社 | Plastic-molded semiconductor integrated circuit package unsealing method and unsealing device |
| JP2016063194A (en) * | 2014-09-22 | 2016-04-25 | 日本サイエンティフィック株式会社 | Opening method of plastic molded semiconductor integrated circuit package and opening device of plastic molded semiconductor integrated circuit package |
| CN110660689A (en) * | 2019-09-11 | 2020-01-07 | 大同新成新材料股份有限公司 | Die bonding method of semiconductor element |
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