CN115078406A - Analysis method of failure chip - Google Patents
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- CN115078406A CN115078406A CN202210874065.3A CN202210874065A CN115078406A CN 115078406 A CN115078406 A CN 115078406A CN 202210874065 A CN202210874065 A CN 202210874065A CN 115078406 A CN115078406 A CN 115078406A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/2806—Means for preparing replicas of specimens, e.g. for microscopal analysis
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N1/00—Sampling; Preparing specimens for investigation
- G01N1/28—Preparing specimens for investigation including physical details of (bio-)chemical methods covered elsewhere, e.g. G01N33/50, C12Q
- G01N1/34—Purifying; Cleaning
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/8803—Visual inspection
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/956—Inspecting patterns on the surface of objects
- G01N2021/95638—Inspecting patterns on the surface of objects for PCB's
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Abstract
The invention discloses an analysis method of a failed chip, and belongs to the field of chip detection. The deblocking method comprises the following steps: cutting part of the failed chip to reduce the surface area of a packaging film on the failed chip; placing the failed chip in a first acidic solution, wherein the temperature of the first acidic solution is 20-60 ℃; after the packaging film is removed, the failure chip is placed in a first organic solvent for cleaning; placing the failed chip in a second acidic solution; heating the second acidic solution at 50-150 ℃; placing the failed chip in a second organic solvent for cleaning; and placing the failed chip under a microscope for detection. The analysis method of the failure chip provided by the invention can improve the analysis reliability of the failure chip.
Description
Technical Field
The invention belongs to the technical field of chip detection, and particularly relates to an analysis method of a failed chip.
Background
The chip package is a housing for mounting a semiconductor integrated circuit chip, plays a role in mounting, fixing, sealing, protecting the chip and enhancing the electric heating performance, and is also a bridge for communicating the internal world of the chip with external circuits. Chip On Film (COF) packaging technology is commonly used to package the chip, and for the failure chip after packaging, the package film (COF) is stripped as the first step of failure chip analysis.
However, when the packaging film is stripped, the problems of residual surface substances, damage to the insulating layer, chip damage and the like exist, so that partial components in the chip are corroded, and the analysis reliability of the failed chip is influenced.
Disclosure of Invention
The invention aims to provide an analysis method of a failed chip, which can improve the analysis reliability of the failed chip.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a failure chip analysis method, which at least comprises the following steps:
cutting part of the failed chip to reduce the surface area of a packaging film on the failed chip;
placing the failed chip in a first acidic solution, wherein the temperature of the first acidic solution is 20-60 ℃;
after the packaging film is removed, the failure chip is placed in a first organic solvent for cleaning;
placing the failed chip in a second acidic solution;
heating the second acidic solution at 50-150 ℃;
placing the failed chip in a second organic solvent for cleaning; and
and (3) placing the failed chip under a microscope for detection.
In an embodiment of the present invention, after the failed chip is cut, the cut portion of the failed chip is placed in a chip accommodating device, and a plurality of through holes are disposed at the bottom of the chip accommodating device.
In an embodiment of the invention, the size of the through hole is smaller than the size of the cut part of the failed chip.
In an embodiment of the present invention, the reaction of the failed chip with the first acidic solution and/or the second acidic solution comprises the following steps:
placing the chip containing device containing the failed chip in an unsealing device; and
injecting the first acidic solution or the second acidic solution into the decapsulating device until the first acidic solution or the second acidic solution covers the failed chip.
In an embodiment of the invention, the first acidic solution comprises concentrated nitric acid, and the mass fraction of the concentrated nitric acid is 86% -97.5%.
In an embodiment of the invention, the first organic solvent or the second organic solvent includes one or a mixture of acetone, absolute ethyl alcohol or isopropyl alcohol, and the failed chip is washed in the first organic solvent or the second organic solvent for 20-60 s.
In an embodiment of the present invention, after the failed chip is washed in the first organic solvent, the chip accommodating device is taken out and directly placed in the second acidic solution.
In an embodiment of the invention, the second acidic solution includes concentrated sulfuric acid, and the mass fraction of the concentrated sulfuric acid is 70% -98%.
In one embodiment of the invention, the failed chip and the second acidic solution react at 50-150 ℃ for 3-10 min.
In an embodiment of the invention, after the failed chip is cleaned by the second organic solvent, the failed chip is placed in an ultrasonic instrument and is vibrated for 10-40 s.
In summary, the invention provides an analysis method of a failed chip, which can rapidly peel off a packaging film on the failed chip and effectively remove the residual packaging adhesive by reacting the failed chip with two acidic solutions. After each acidic solution reaction, the organic solvent is adopted for cleaning, so that the surface of the failed chip can be prevented from being damaged, and the failure analysis can be efficiently and nondestructively carried out on the failed chip. By cutting the failure chip and analyzing the chip at the failure part, the chemical reaction time can be reduced, the use amount of chemical reagents is reduced, and the enterprise cost is reduced. By the failure chip analysis method provided by the invention, the failure chip can realize efficient failure analysis.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flowchart illustrating a method for analyzing a failed chip according to an embodiment.
Fig. 2 is a schematic diagram of an example of a decapsulating device for a failed chip, wherein the failed chip and a chip-holding device are placed.
FIG. 3 is a schematic diagram of the surface topography of a failed chip after decapsulation in one embodiment.
Description of reference numerals:
10 testing the sample; 11 a chip housing means; 12 through holes; 13 unsealing device.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In the present invention, it should be noted that, as the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, their indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present application and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, as used herein, are used for descriptive and differential purposes only and are not to be construed as indicating or implying relative importance.
In the chip preparation process, the chip is directly packaged on the flexible printed board by the soft film packaging technology of the crystal grains, the packaging mode has the advantages of high packaging density, light weight, reduced volume and the like, and meanwhile, the purpose of free bending and mounting is achieved, and the flexible film packaging technology of the crystal grains is widely applied to the packaging process of the chip. When a chip using such a packaging process fails, the packaging film is stripped off as a first step of failure analysis of the failed chip. The packaging film comprises materials such as polyimide, acrylic polymer and epoxy resin, the packaging film can also comprise other resin materials or plastic materials, and the packaging film is difficult to peel by adopting a single solution, so that accurate failure analysis cannot be carried out. The invention provides an analysis method of a failure chip, which can rapidly peel off a packaging film, effectively remove residual packaging adhesive, avoid damage to the surface of a sample, perform accurate failure analysis on the failure chip and improve the accuracy of the failure analysis.
Referring to fig. 1, the present invention provides a failure analysis method for a failed chip, which can be applied to failure analysis of die soft film packaging technologies of various chip types, and can effectively remove a packaging film and a packaging adhesive, and the surface of the failed chip is not damaged, thereby improving the accuracy of the failure analysis. Specifically, the analysis method for the failed chip provided by the invention comprises the steps of S11-S15.
And S11, sampling the failed chip.
Referring to fig. 1 to 2, in one embodiment of the present invention, before analyzing the failed chip, a sample is prepared to obtain a test sample 10. The invention is not limited to the kind of the failed chip, and the failed chip includes, for example, a Field Effect Transistor (FET), a Metal-Oxide Semiconductor Field Effect Transistor (MOSFET), a Complementary Metal Oxide Semiconductor (CMOS), an Insulated Gate Bipolar Transistor (IGBT), a Fast Recovery Diode (FRD), a high-speed high-Efficiency rectifier Diode (CCD), a constant voltage Diode, a high frequency Diode, a Light Emitting Diode (LED), a Gate Thyristor (GTO), a Light Triggered Thyristor (Signal Triggered Thyristor, LTT), a Thyristor (Charge Coupled Device), a Charge Coupled Device (Device), a Digital image sensor (Digital image sensor), one or more of semiconductor devices such as a DSP (digital signal Processor), a Photo Relay (Photo Relay) or a microprocessor (Micro Processor) are integrated. Before failure analysis, the specific failure position of the chip is judged according to the electrical test and marked, and a sample is prepared according to the failure position of the electrical test, and the failed chip is cut to obtain a test sample 10. The surface shape of the test sample 10 is, for example, a rectangle, a square, or a polygon with other shapes, a curved surface pattern, and the like, and the test sample 10 ensures that the failure cause can be analyzed, and at the same time, the surface area of the test sample 10 is reduced, that is, the surface area of the encapsulation film on the test sample 10 is reduced, so that on one hand, the chemical reaction time can be reduced, on the other hand, the usage amount of chemical reagents can be reduced, and the cost of failure analysis can be reduced.
Referring to fig. 1 to 2, in an embodiment of the present invention, after the preparation of the failed chip sample, the test sample 10 is placed in the chip container 11, and the size of the chip container 11 is larger than that of the test sample 10, so as to ensure that the test sample 10 is flatly placed in the chip container 11 and reduce the usage amount of the chemical reagent. Wherein, the bottom of the chip container 11 is provided with a plurality of through holes 12, and the shape of the through holes 12 is, for example, circular or quadrilateral. The opening of the through hole 12 is smaller in size than the test specimen 10, preventing the test specimen 10 from being expelled from the through hole 12 during the unsealing. In other embodiments, a plurality of test samples 10 may be placed in the chip container 11, and there is no overlapping portion in the plurality of test samples 10, so as to improve the unsealing efficiency.
Referring to fig. 2, in an embodiment of the present invention, the chip container 11 is made of a glass material or a metal material with excellent corrosion resistance. In the present embodiment, the chip container 11 is made of glass material, for example, and is a small beaker with holes, for example. Through setting up chip accommodate device 11, place test sample 10 in chip accommodate device 11, at the deblocking in-process, press from both sides and get chip accommodate device 11 and operate, reduce tweezers and test sample 10's contact, prevent that tweezers from producing the damage to test sample 10's surface, improving failure analysis's reliability.
Referring to fig. 1 to 2, in an embodiment of the present invention, after the test sample 10 is placed in the chip container, step S12 is performed to place the failed chip in the first acidic solution and cover the failed chip.
Referring to fig. 1 to 2, in an embodiment of the present invention, in step S12, the chip container 11 containing the test sample 10 is placed in the decapsulating unit 13, and the size of the decapsulating unit 13 is slightly larger than that of the chip container 11, so as to ensure smooth removal and insertion of the chip container 11 and reduce the amount of chemicals used. Then, the first acidic solution is added along the edge of the decapsulating device 13, and the first acidic solution enters the chip-housing device 11 from the through hole 12 at the bottom of the chip-housing device 11 until the first acidic solution covers the surface of the test sample 10, and the addition of the first acidic solution is stopped. The phenomenon of uneven surface reaction of the test sample 10 caused by the fact that the first acidic solution is directly added to the chip accommodating device 11 can be prevented, and the phenomenon that the chip test sample 10 turns over due to too much first acidic solution which flows in when the first acidic solution is added to the deblocking device 13 and the chip accommodating device 11 is placed can be avoided, so that the surface of the test sample 10 is damaged. Meanwhile, the addition amount of the first acidic solution can be accurately controlled.
Referring to fig. 1 to 2, in an embodiment of the present invention, the first acidic solution is, for example, concentrated nitric acid, the mass fraction of the concentrated nitric acid is, for example, 86% to 97.5%, and the test sample 10 and the first acidic solution are chemically reacted at a predetermined temperature, for example, 20 ℃ to 60 ℃. In this embodiment, for example, the decapping device 13 is placed on a heating stage and heated, so that the reaction speed between the first acidic solution and the encapsulation film can be increased, and the decapping time of the failed chip can be reduced. In other embodiments, heating may be performed in other ways. Meanwhile, the heating temperature is controlled within a preset range, and the nitric acid in the first acidic solution is prevented from volatilizing, so that the concentration of the first acidic solution is changed, and the dilute nitric acid is caused to react with a passivation layer or a metal layer in the test sample 10. The reaction time of the test sample 10 in the first acidic solution example is, for example, 10min to 30min, and the reaction time can be adjusted by the size of the test sample 10, and the test time is prolonged as the size of the test sample 10 increases. By observing the color of the first acidic solution, when the color of the first acidic solution changes to green, for example, the encapsulating film completely reacts with the first acidic solution, and the test sample 10 can be taken out. In this embodiment, the first acidic solution is, for example, concentrated nitric acid, which can react with the polyester-based material and not with the metal on the test specimen 10, so as to ensure the structural integrity of the metal pad on the test specimen 10. In other embodiments, the first acid solution is selected to strip the encapsulation film according to the polymer material in the encapsulation film.
Referring to fig. 1, in an embodiment of the invention, after the test sample 10 completely reacts with the first acidic solution, step S13 is performed, and after the encapsulation film is removed, the failed chip is cleaned in the first organic solvent.
Referring to fig. 1 to 2, in an embodiment of the present invention, after the test sample 10 completely reacts with the first acidic solution, the chip container 11 is directly gripped, and the chip container 11 together with the test sample 10 is placed in a cleaning device, such as a beaker or a measuring cup. And adding a first organic solvent for cleaning, wherein the first organic solvent comprises one or a mixture of acetone, absolute ethyl alcohol, isopropanol and the like. In this embodiment, the first organic solvent is, for example, acetone, and the cleaning time is, for example, 20s to 60 s. By selecting the organic solvent for cleaning, on one hand, the organic solvent can react with the residual packaging adhesive on the test sample 10, the packaging adhesive is epoxy resin, the damage of an insulating layer of a failed chip caused by the packaging adhesive due to the fact that a cotton swab is used for wiping is avoided, and in the process that a gold ball (gold bump) is removed by using aqua regia in the later period, strong acid diffuses into the test sample 10 from the damaged part of the insulating layer and enters the inner layer of the failed chip to damage the test sample, and the result of failure analysis is influenced. On the other hand, when the organic solvent is used for cleaning, the acid solution on the test sample 10 is diluted to a dilute acid to react with the passivation layer or the metal layer in the test sample 10 when the first acidic solution remained on the test sample 10 or enters the second acidic solution, which affects the reliability of the failure analysis.
Referring to fig. 1, in one embodiment of the present invention, after the test sample 10 is cleaned, step S14 is performed to place the failed chip in the second acidic solution and cover the failed chip.
Referring to fig. 1 to 2, in an embodiment of the present invention, after the test sample 10 completely reacts with the first acidic solution, the chip container 11 is directly gripped, and the chip container 11 together with the test sample 10 is placed in a new decapsulation unit 13. Likewise, the size of the new decapsulating device 13 is slightly larger than the size of the chip-housing device 11, so as to ensure the smooth removal and insertion of the chip-housing device 11, and reduce the amount of chemicals used. Then, a second acidic solution is added along the edge of the decapsulation unit 13, and the second acidic solution enters the chip-housing unit 11 from the through hole 12 at the bottom of the chip-housing unit 11 until the second acidic solution covers the surface of the test sample 10, and the addition of the second acidic solution is stopped. The phenomenon that the surface reaction of the test sample 10 is not uniform can be prevented, and the test sample 10 can be prevented from turning over to damage the surface of the test sample 10.
Referring to fig. 1, in an embodiment of the present invention, after the test sample 10 is placed in the second acidic solution, step S15 is performed to heat the second acidic solution.
Referring to fig. 1 to 2, in an embodiment of the present invention, the second acidic solution is, for example, concentrated sulfuric acid, and the mass fraction of the concentrated sulfuric acid is, for example, 70% to 98%. And heating the second acidic solution to accelerate the reaction speed of the test sample 10 and the second acidic solution, wherein the heating temperature is 50-150 ℃, for example. In this embodiment, for example, the decapsulation unit 13 is placed on a heating stage and heat-treated to accelerate the reaction and reduce the decapsulation time. In embodiments thereof, heating may also be performed in other ways. Meanwhile, the heating temperature is controlled, and the volatilization amount of concentrated sulfuric acid is reduced. The test sample 10 is reacted for 3min to 10min in the second acidic solution example, the reaction time can be adjusted by the size of the test sample 10, and the test time is prolonged along with the increase of the size of the test sample 10. The reaction time is controlled according to the composition of the encapsulation film on the test sample 10 and the type of the encapsulation adhesive, so as to ensure that the encapsulation adhesive and the encapsulation film possibly remaining after the reaction with the first acidic solution are removed. And the second acidic solution, such as concentrated sulfuric acid, can react with the resinous material in the encapsulating film and the encapsulating glue, such as epoxy glue, but not with the metal on the test specimen 10, ensuring the structural integrity of the metal pads on the test specimen 10. In other embodiments, different second acidic solutions are selected according to the types of the resin material and the encapsulation adhesive in the encapsulation film.
Referring to fig. 1, in one embodiment of the present invention, after the test sample 10 is reacted with the second acidic solution, step S16 is performed to clean the failed chip in the second organic solvent.
Referring to fig. 1 to 2, in an embodiment of the present invention, after the test sample 10 completely reacts with the second acidic solution, the chip container 11 is directly gripped, and the chip container 11 together with the test sample 10 is placed in a new cleaning device, such as a beaker or a measuring cup. And adding a second organic solvent for cleaning, wherein the second organic solvent comprises one or a mixture of acetone, absolute ethyl alcohol, isopropanol and the like. In this embodiment, the second organic solvent is, for example, acetone, and the cleaning time is, for example, 20s to 60 s. The second organic solvent may react with the resin remaining on the test specimen 10, for example, with an epoxy resin, to ensure complete removal of the encapsulation film and the encapsulation paste on the test specimen 10. Meanwhile, the damage of the insulating layer of the failed chip caused by the fact that a cotton swab is used for wiping is avoided, and strong acid is caused to diffuse into the test sample 10 from the damaged part of the insulating layer and enter the inner layer of the failed chip in the process that the gold ball of the routing is removed by using aqua regia in the later period, so that the test sample is damaged, and the accuracy of failure analysis is influenced.
Referring to fig. 2, in an embodiment of the present invention, after the test sample 10 is washed by the second organic solvent, the test sample 10 is taken out from the chip container 11 by using tweezers, and during the taking out process, the test sample 10 is prevented from contacting the target area. And clamping the test sample 10 by using tweezers, placing the test sample 10 in an ultrasonic instrument, and oscillating for 10-40 s to remove the second organic solvent attached to the surface of the test sample 10. The clamping head of the tweezers is made of an elastic material with a smooth surface, such as polytetrafluoroethylene, polyperfluoroethylpropylene or modified polytetrafluoroethylene, and the like, so as to reduce damage to the surface of the test sample 10.
Referring to fig. 1, in an embodiment of the invention, after the packaging film on the failed chip is peeled off, step S17 is performed, and the failed chip is placed under an optical microscope for detection.
Referring to fig. 2 to 3, in an embodiment of the present invention, after the test sample 10 is processed, the test sample 10 is placed under an optical microscope for inspection, and by inspection, the encapsulation film on the surface of the test sample 10 is completely removed, no encapsulation adhesive and no encapsulation film remain on the surface, and the structure of the test sample 10 is complete. After the packaging film of the test sample 10 is removed, the needle insertion electrical property test can be performed on the surface of the test sample 10, and the test can be performed after the physical stripping, so that the failure reason of the chip can be analyzed. By the failure chip analysis method provided by the invention, in the failure analysis process, the structures of the failure chip, the metal wiring structure and the like are complete, the damage to the surface of a failure chip sample can be avoided, the package film can be peeled off without damage, and the reliability of the failure analysis can be improved.
In summary, the present invention provides a method for analyzing a failed chip, in which a test sample is placed in a chip accommodating device, so as to reduce the touch of a clamping device on the surface of the failed chip 10 during the peeling process of the packaging film. Polyester materials in the packaging film are removed through the first acidic solution, resin materials and packaging glue in the packaging film are removed through the second acidic solution, and after the first acidic solution and the second acidic solution react, organic solutions are respectively washed, so that no packaging film and no packaging glue are left on a test sample. By controlling the reaction conditions of the acid solution and the test sample, the deblocking process is accelerated, the deblocking effect is improved, the failure chip with the complete surface structure is obtained, and the reliability of failure analysis of the failure chip can be improved.
The above description of illustrated embodiments of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As indicated, these modifications may be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.
The above description is only a preferred embodiment of the present application and a description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application. Besides the technical features described in the specification, other technical features are known to those skilled in the art, and are not described in detail herein in order to highlight the innovative features of the present invention.
Claims (10)
1. A method for analyzing a failed chip is characterized by at least comprising the following steps:
cutting part of the failed chip to reduce the surface area of a packaging film on the failed chip;
placing the failed chip in a first acidic solution, wherein the temperature of the first acidic solution is 20-60 ℃;
after the packaging film is removed, the failure chip is placed in a first organic solvent for cleaning;
placing the failed chip in a second acidic solution;
heating the second acidic solution at 50-150 ℃;
placing the failed chip in a second organic solvent for cleaning; and
and (3) placing the failed chip under a microscope for detection.
2. The method for analyzing the failed chip according to claim 1, wherein the failed chip is cut, and then the cut portion of the failed chip is placed in a chip accommodating device, and a plurality of through holes are formed in the bottom of the chip accommodating device.
3. The method of analyzing a failed chip according to claim 2, wherein the size of the through-hole is smaller than the size of the cut portion of the failed chip.
4. The method for analyzing a spent chip according to claim 2, wherein the reaction of the spent chip with the first acidic solution and/or the second acidic solution comprises the steps of:
placing the chip containing device containing the failed chip in an unsealing device; and
injecting the first acidic solution or the second acidic solution into the decapsulating device until the first acidic solution or the second acidic solution covers the failed chip.
5. The method for analyzing the failed chip according to claim 1, wherein the first acidic solution comprises concentrated nitric acid, and the mass fraction of the concentrated nitric acid is 86% -97.5%.
6. The method for analyzing the failed chip according to claim 1, wherein the first organic solvent or the second organic solvent comprises one or more of acetone, absolute ethyl alcohol or isopropyl alcohol, and the failed chip is washed in the first organic solvent or the second organic solvent for 20-60 s.
7. The method for analyzing a failed chip according to claim 2, wherein the failed chip is washed in the first organic solvent, and then the chip holder is taken out and directly placed in the second acidic solution.
8. The method for analyzing a failed chip according to claim 1, wherein the second acidic solution comprises concentrated sulfuric acid, and the mass fraction of the concentrated sulfuric acid is 70% to 98%.
9. The method for analyzing a failed chip according to claim 8, wherein the failed chip reacts with the second acidic solution at 50 ℃ to 150 ℃ for 3min to 10 min.
10. The method for analyzing the failed chip according to claim 1, wherein the failed chip is placed in an ultrasonic instrument and is vibrated for 10-40 s after being cleaned by the second organic solvent.
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