JPH07231260A - High speed serial parallel converter - Google Patents

Abstract

PURPOSE:To realize high speed serial parallel conversion by devising a method that a circuit realizing a shift function is provided to a circuit part whose speed is low because of frequency division thereby realizing the circuit facilitating a stable operation. CONSTITUTION:The converter is provided with a clock frequency divider 12 receiving an input clock 50, frequency-dividing the clock into 1/N and providing an output of the result to a parallel latch section 15 for the conversion of N-bit length, a shift register section 14 comprising (2N-1) stages of shift circuits receiving input data 52 and the clock 50 and providing an output of the result to the parallel latch section 15, the parallel latch section 15 receiving (2N-1) shift data from the shift register section 14 and the clock subject to 1/N frequency division at the clock frequency divider 12 an converting them into (2N-1) sets of parallel data, and a bit replacement device 17 receiving a selection signal 19 and the (2N-1) sets of data from the parallel latch section 15 and selecting N-bit consecutive data and providing an output of the result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is an ultra-high-speed serial-parallel converter used in the field of communications, etc., and restores serial data with a period close to the performance limit of the device used in a predetermined parallel data string unit. It relates to a circuit to convert.

[0002]

2. Description of the Related Art The term "serial-parallel conversion" as used herein means not only conversion of a serial data string into an N-bit parallel data string, but serial conversion in 1-bit units by an external data string shift control signal. A converter that has a function of shifting data (hereinafter referred to as a shift function) and restores and converts into predetermined N-bit parallel data.

FIG. 4, FIG. 5 and FIG. 6 for an example of the prior art.
The serial-parallel conversion operation in the case of converting the input serial data into 4-bit parallel data using will be described below. The input / output signals are, as shown in FIG.
Serial input data 52, a clock control signal 51,
Input clock 50 and input 4-bit parallel signal 66
It outputs a to 66d. The configuration is the clock control unit 6
1, a clock frequency divider 62, a demultiplexing circuit 60, and a delay element 63. This demultiplexing circuit 60
Is a shift register unit 64 and a parallel latch unit 6
5, and a minute delay element for matching the timing of the clock and the data is provided in each.

The clock control signal 51 is, as shown in FIG. 5, a clock inhibition signal 82 for one cycle time of the input clock 50, and one output clock 8 is supplied.
This is a signal for deleting 3. This clock control signal 5
1 is used for shifting in 1-bit units in order to shift to the position where the target 4-bit parallel data string is arranged. The clock control unit 61 is composed of an AND gate, and supplies the clock 50 to one gate input terminal and the clock control signal 51 to the other inverting input terminal. Then, as described above, one output clock 83 is deleted by the clock inhibit signal 82 of one cycle time and is supplied to the next clock frequency divider 62. However, in this circuit means, it becomes difficult to stably form the clock signal in which the clock is prohibited, and correct clock control may not be performed, resulting in malfunction.

The cause of this instability is that the operating frequency of the serial-parallel conversion used here is extremely high, and for example, 1
Since it will be 0 GHz or higher,
The fall time occupies a large range, the voltage amplitude decreases due to the cut-off frequency characteristic of the device, and the propagation delay changes due to the change of the junction temperature of the device used for the clock controller 61 and the input signal system. As a result, the output waveform varies such that the output waveform becomes thin or thick due to the timing shift between the two signals of the gate circuit. Also, stable high level and low level are effective due to these factors, such as the tolerance decrease due to the jitter of the clock itself, the tolerance decrease due to the jitter of the input serial data itself, and the occurrence of jitter due to the reflection of the signal transmission line. Such a range (hereinafter referred to as an eye opening) becomes a narrow range as shown in FIG. For this reason, it is difficult to obtain a stable clock-controlled output signal even when using a high-speed gallium arsenide device, etc., and it may not operate stably due to individual variations of the device, etc. It is selected and used. Because of the above
To perform stable serial / parallel conversion, restrictions such as limiting the operating ambient temperature range to within ± 5 ° C and requiring a heat-up time of 30 minutes or more after turning on the power are necessary. There are cases.

Next, the clock divider 62 receives the output clock of the clock control signal 51, divides it by 1/4, and supplies it to each clock terminal of the parallel latch section 65.
On the other hand, the shift register unit 64 is a 4-bit shift circuit. The clock 50 signal is supplied to each clock terminal of the shift register section 64 after timing is adjusted with the input data 52 by the delay element 63, and the serial input data 52 is given to the D input terminal of the shift register section 64, The input data is shifted every clock to output 4-bit parallel data. Parallel latch unit 65
Is a 4-bit latch circuit, which receives 4-bit parallel data from the shift register unit 64 and supplies a 1/4 clock from the clock frequency divider 62 to the clock terminal for every 4 clock unit time. The low speed parallel data 65a to 65d are output to the outside.

[0007]

As described above, since the device is used in the frequency range close to the performance limit of the device, there are many unstable factors, so that the eye opening becomes narrow and the operation margin is small. There is. Therefore, it is not easy to maintain a stable serial / parallel conversion operation.

Therefore, the problem to be solved by the present invention is to realize a circuit that realizes a stable operation by devising a circuit that realizes a shift function on the frequency-divided low-speed side. And

[0009]

[Means for solving the problem]

(Means for Solving Claim 1) FIG. 1 shows a means for solving 4-bit parallel conversion according to the present invention. In order to solve the above problems, in the configuration of the present invention, in order to convert and restore parallel data of N-bit length, a clock that receives the input clock 50, divides it by 1 / N, and outputs it to the parallel latch unit 15 is output. The shift register unit 1 which is provided with the frequency divider 12 and receives the input data 52 and the clock 50 and is provided with a shift circuit of 2N-1 stages to output to the parallel latch unit 15
4 is provided and receives 2N-1 pieces of shift data from the shift register unit 14 and a clock divided into 1 / N by the clock divider 12 and converts it into 2N-1 pieces of parallel data.・ Latch section 15 is provided to select signal 19
And 2N-1 pieces of data from the parallel latch section 15 to select and output N-bit continuous data, thereby forming a bit exchanging unit 17.

(Means for Solving Claim 2) FIG. 2 shows a means for solving 4-bit parallel conversion according to the present invention. In order to solve the above problems, in the configuration of the present invention, N
In order to convert and restore parallel data of bit length, the clock controller 21 receives the input clock 50 and divides it by M / N.
The clock control unit 21 is provided with a pre-stage frequency divider 22a for outputting to the clock control unit 28, which receives the clock control signal 28 and controls and outputs the input signal of the pre-stage frequency divider 22a.
A post-stage frequency divider 22b that receives the output signal of 1 and frequency-divides it by 1 / M and outputs it to the parallel latch unit 25 is provided, and receives the input clock 50 and receives the pre-stage frequency divider 22a and the post-stage frequency divider 22.
In both configurations with b, input data 52 is divided by 1 / N.
And a clock 50, and a shift circuit for outputting to the parallel latch unit 25 by providing an N + N / M-1 stage shift circuit.
The register section 24 is provided, and the clock frequency-divided by the post-stage frequency divider 22b and N + N / M from the shift register section 24 are provided.
A parallel latch unit 25 that receives -1 shift data and converts it into N + N / M-1 parallel data is provided, and a selection signal 29 and N from the parallel latch unit 25 are provided.
Bit interchanger 2 for receiving + N / M-1 parallel data and selecting and outputting N-bit continuous data
7 is provided. In the above, the front stage frequency divider 22a
Is not limited to 1/2 frequency division, and is therefore used as frequency division means for M / N frequency division.

[0011]

In the case of the circuit configuration of FIG. 1, the bit interchanger 17
Is composed of four sets of four-input one-output selectors, receives 7-bit parallel data from the parallel latch unit 15 in the preceding stage, and selects 2-bit selection data 19 from among the 7-bit parallel data. There is an effect that continuous 4-bit data can be shifted and output in 1-bit units. Moreover, this selection signal has an effect that the arrangement of the output data is not disturbed even if the selection signal is selected regardless of the clock. In the case of the circuit configuration of FIG.
0 is simply divided by the front divider 22a to 1/2
A clock is supplied to the clock control unit 21, and every time one output clock 73 is deleted by the clock control signal 28, a function of shifting the input data 52 in units of 2 bits can be obtained. In the case of the circuit configuration shown in FIG. 2, the bit interchanger 27 has an effect of realizing a 1-bit shift function by selecting 4 bits from the 5-bit parallel data by the selection signal 29. Moreover, this selection signal has an effect that the arrangement of the data string is not broken even if the selection signal is selected at any timing regardless of the clock. From the second embodiment, the frequency division value of the front stage frequency divider 22a is set to 2, and the value M of the rear stage frequency divider 22b is 2, 3, 4, 5,
If the frequency division value is 6, 7, 8, etc., 4, 6, 8, 10, 1,
It is also possible to easily realize conversion into parallel data having a length of 2, 14, 16 bits or the like. The number of J times to give the clock control signal 28 and (N + N / M-
1) By providing a bit arrangement, it is possible to realize a shift function in 1-bit units, and it is possible to easily realize parallel conversion by realizing an arbitrary bit shift.

[0012]

【Example】

(Embodiment 1) With respect to an embodiment of the present invention, a serial-parallel conversion operation in the case of converting into 4-bit parallel data will be described below with reference to FIG. The configuration is made up of a clock divider 12, a demultiplexing circuit 10, a bit interchanger 17, and a delay element 13. The demultiplexing circuit 10 includes a shift register section 14 and a parallel latch section. 15, and a minute delay element for matching the timing of the clock and each input data is provided in each. As shown in FIG. 1, the input / output signals include the selection signal 19, the serial input data 52, and the clock 50.
, And outputs 4-bit parallel signals 16a to 16d, and the selection signal 19 serves as a substitute for the conventional clock control signal 51.

The clock divider 12 receives the input clock of the clock 50 and simply divides it by 1/4 and supplies it to the clock terminal of the parallel latch section 15. Therefore, the clock frequency divider 62 can easily realize a stable frequency dividing circuit. The shift register unit 14 is a 7-bit shift circuit. The clock 50 signal is supplied by the delay element 13 to the clock terminal of the shift register unit 14 after timing with the input data 52, while the serial input data 52 is supplied to the D input terminal of the shift register unit 14. , 7-bit parallel data is output by shifting the input data for each clock. This is because (2 × 4-1) = 7-bit parallel data is required in the bit interchanger 17 in the subsequent stage. Parallel latch unit 15
Is a 7-bit latch circuit which receives the 7-bit parallel data from the shift register unit 14 and supplies the 1/4 clock from the clock frequency divider 12 to the clock terminal to output the clock signal every 4 clock unit time. Then, the low-speed 7-bit parallel data 15a to 15g are output to the bit interchanger 17 in the next stage.

The bit exchanging device 17 comprises four sets of four-input one-output selectors, which receives the 7-bit low-speed parallel data from the parallel latch section 15,
A 2-bit selection signal 19 is supplied to the select terminals of all the selectors 17a to 17d, and in response to this selection signal, continuous 4-bit data is selected from 7-bit low speed parallel data and output to the outside. As a result, the arrangement of the target 4-bit parallel data string can be changed. That is, for example, when the 2-bit selection signal 19 has the first value = 00, the 4-bit output data is 15a, 15b, 15c, 15d of the parallel latch unit 15 of FIG.
Is selected and output. Next, select signal 1
When the value of 9 = 01, 15b, 15c, 15d, 15
e is selected and output. Further, when the value of the selection signal 19 = 10, 15c, 15d, 15e and 15f are selected and output. Further, the value of the selection signal 19 = 11
In the case of, 15d, 15e, 15f and 15g are selected and output. As described above, only by sequentially switching the 2-bit selection signal 19, it is possible to achieve the same effect as shifting consecutive 4-bit data in units of 1 bit and outputting the data. Moreover, even if the selection signal 19 is selected at an arbitrary timing regardless of the clock 50,
There is also an advantage that the arrangement of the target 4-bit parallel data string is not disturbed. In other words, this can eliminate the strict timing condition at the time of 1-bit shift operation as in the past.

In the above embodiment, the case where the serial / parallel conversion number N = 4 is selected and consecutive N = 4 data is selected from (2N-1) = 7 parallel data and output is described. . From this fact, serial / parallel conversion can be similarly performed for other N values. For example, in the case of N = 8 bits, the frequency dividing circuit is divided into 1/8 and (2N
-1) = 15 parallel data circuits may be provided, and consecutive N = 8 may be selected and output from the parallel data circuits.

(Embodiment 2) With respect to an embodiment of the present invention, a serial-parallel conversion operation in the case of converting into 4-bit parallel data will be described below with reference to FIGS. The configuration is such that the clock divider 22, the clock controller 21, the demultiplexing circuit 20, and the bit interchanger 27.
And a delay element 23. Here, the clock frequency divider 22 is divided into a front stage frequency divider 22a and a rear stage frequency divider 22b. The demultiplexing circuit 20 includes a shift register section 24, a parallel latch section 25,
Each of them is provided with a bit interchanger 27 and a minute delay element for adjusting the timing of a clock and each input data. The input / output signals are, as shown in FIG.
The clock control signal 28, the selection signal 29, the serial input data 52, and the clock 50 are input to output 4-bit parallel output data 26a to 26d. It is a substitute for the clock control signal 51 of FIG.

The clock frequency divider 22 receives the input clock of the clock 50, and the pre-frequency divider 22a receives the clock 50.
Is output to the clock control unit 21 by simply dividing the clock into 1/2 as shown in FIG. The clock control unit 21 is composed of an AND gate, and applies the 1/2 clock, which has been reduced in speed by half as described above, to one gate and the clock control signal 28 to the other inverting input terminal. Then, as shown in FIG. 3, one output clock 73 is generated by the clock inhibit signal 72 having a two clock cycle time.
To remove the clock divider 22 of the next stage
b. Therefore, clock control can be performed at a stable timing with a margin about twice that of the conventional case. However, since the deletion is performed for 1/2 clock, the data of 4-bit arrangement can be shifted only in units of 2 bits. This countermeasure is provided to the last bit interchanger 27. I have it. next,
The post-stage frequency divider 22b further halves this input clock.
The clock signal which is divided into 1/4 and is divided into 1/4 in total is supplied to each clock terminal of the parallel latch section 25.

On the other hand, the shift register section 24 is a 5-bit shift circuit. Clock 50 signal to delay element 2
3 supplies the clock data to the clock terminal of the shift register unit 24 after adjusting the timing with the input data 52, supplies the serial input data 52 to the D input terminal of the shift register unit 24, and shifts the input data for each clock. And outputs 5-bit parallel data. Next, the parallel latch unit 25 is a 5-bit latch circuit, which receives the 5-bit parallel data from the shift register unit 24 and supplies the 1/4 clock from the clock divider 22 to the clock terminal. Then, the low-speed 5-bit parallel data 25a to 25e for every 4-clock unit time is output to the bit exchanging device 27 of the next stage. This is because (4 + 1) -bit parallel data is required in the bit interchanger 27 in the subsequent stage.

The bit interchanger 27 comprises four sets of 2-input 1-output selectors, receives 5-bit parallel data from the parallel latch unit 25, and, on the other hand,
The selection signal 29 is supplied to the select terminals of all the selectors 27a to 27d to select 4 bits from the 5 bits of parallel data and output them to the outside. As a result, a 1-bit shift function can be realized with 4-bit aligned data. Moreover, the selection signal 29 is supplied to the clock 50.
Regardless of the above, even if it is selected at an arbitrary timing, the arrangement of the 4-bit parallel data sequence will not be disturbed.

Thus, by controlling both the clock control signal 28 and the selection signal 29 described above by combining them as described below, the input serial data 52 can be sequentially corrected in 1-bit units. Can be converted into a 4-bit sequence and output.

First, the two signals are controlled to give four states. For example, as an initial state, the selection signal 29
= Low level, the clock control signal 28 is not applied and the 4-bit output data 26a to 26d at this time are the parallel data 25b to 25e of the parallel latch section 25 selected and output. I assume. First, in order to shift the arrangement of the 1-bit input data from this state, only the selection signal 29 = high level is changed, and the 4-bit output data 26a to 26d are selected and output on the parallel data 25a to 25d side. It As a result, an output obtained by shifting the arrangement of 1-bit input data is obtained. Secondly, in order to shift the arrangement of the 2-bit input data, if the selection signal 29 is returned to the low level and the clock control signal 28 is generated once, the 2-bit arrangement is shifted only by this clock control signal 28. It has been done. As a result, as the 4-bit output data 26a to 26d, the parallel data 25b to 25e side is selected and the output obtained by shifting the 2-bit arrangement is obtained. Thirdly, in order to shift the arrangement of the 3-bit input data, it is only necessary to change the selection signal 29 to the high level, and the 2-bit arrangement is shifted by the clock control signal 28 and the 1-bit arrangement by the selection signal 29. The sum of the shift and the shift means that the 3-bit arrangement is shifted. As a result, the 4-bit output data 26a to 26d are parallel data 25a to 25d.
The side is selected and the output obtained by shifting the 3-bit sequence is obtained. After that, by repeating the control of both signals described above, it is possible to shift the target arrangement of the 4-bit parallel data string in units of 1 bit.

In the above embodiment, the serial / parallel conversion number N = 4 is explained, but this N value is actually also the frequency division value of the clock frequency divider 22. That is, the latch clock given to the parallel latch unit 25 means the serial-parallel conversion number N = 4. Therefore, when the frequency division value of the post-stage frequency divider 22b is set to K, the above embodiment is an example of K = 2.

On the other hand, from the above description of the embodiment, it can be understood that the role of the shift function can be shared and executed. That is, by providing a sequence of (N + 1) bits in the bit interchanger 27, a shift function can be realized in 1-bit units. On the other hand, if the number of times of control of the clock control signal 28 is set to J, the output signal obtained by dividing the output signal by 1/2 in the preceding stage frequency divider 22a in response to the input clock of the clock 50 can realize the shift function in J × 2 bit units. . By controlling by combining these two shift functions, it is possible to realize the shift of an arbitrary bit. Therefore, if the value of K, which is the frequency division value of the post-stage frequency divider 22b, is set to frequency division values of 2, 3, 4, 5, 6, 7, 8, etc., 4, 6, 8, 10, 12, 14, 14, It can be converted into parallel data of 16-bit length or the like. Moreover, according to the above description, by providing the number of times the J clock control signal 28 is applied and the arrangement of (N + 1) bits in the bit interchanger 27, a shift function can be realized in 1-bit units, and an arbitrary bit shift can be performed. By realizing the above, parallel conversion can be similarly realized.

[0024]

Since the present invention is configured as described above, it has the following effects. In the case of the circuit configuration shown in FIG. 1, even if the selection signal 19 is used to select at any timing regardless of the clock 50, the target 4-bit parallel data sequence is shifted in 1-bit units without being disturbed. It has the advantage that it can be output. That is, this has a great effect of eliminating the strict timing condition of the related art.

In the case of the circuit configuration shown in FIG. 2, the clock divider 22 simply changes the input clock 50 to 1 by the preceding stage divider 22a.
The control circuit is configured to delete the 1/2 clock with the low-speed 1/2 clock divided by / 2. The 1-bit shift function is made independent of the clock timing by the bit interchanger 27. As a result, 2
It is possible to obtain an effect that clock control can be performed at stable timing with a margin more than double. Further, if the value of K, which is the frequency division value of the post-stage frequency divider 22b, is set to a frequency division value of 2, 3, 4, 5, 6, 7, 8, etc., 4, 6, 8, 10, 12, 14, With the 16-bit length or the like, it is possible to obtain an effect that it can be converted into parallel data that realizes a shift function in units of 1 bit.

[0026]

[Brief description of drawings]

FIG. 1 shows a high-speed serial-parallel conversion circuit according to the present invention.
It is a first embodiment of bit-parallel conversion.

FIG. 2 shows a high-speed serial-parallel conversion circuit according to the present invention.
It is Embodiment 2 of bit-parallel conversion.

FIG. 3 is a timing diagram illustrating a clock control operation according to the second embodiment of the present invention.

FIG. 4 is an example of 4-bit parallel conversion in a conventional high-speed serial-parallel conversion circuit.

FIG. 5 is a timing diagram illustrating a clock control operation of a conventional example.

FIG. 6 is a diagram illustrating eye opening.

[Explanation of symbols]

10, 20, 60 Demultiplexing circuit 12, 22, 62 Clock divider 13, 23, 63 Delay element 14, 24, 64 Shift register unit 15, 25, 65 Parallel latch unit 15a to 15g Low speed parallel data 16a to 16d, 66a to 66d 4-bit parallel signal 17, 27-bit interchanger 17a to 17d, 27a to 27d selector 19, 29 selection signal 21, 61 clock control unit 22a pre-stage frequency divider 22b post-stage frequency divider 25a to 25e , 65a to 65d Parallel data 26a to 26d Output data 28 Clock control signal 29 Selection signal 50 Clock 51 Clock control signal 52 Data 72, 82 Clock inhibit signal 73, 83 One output clock

Claims (2)

[Claims] 1. A circuit for inputting serial input data (52) and a clock (50) to restore and convert into a predetermined data string unit of N-bit parallel, and receives the input clock (50) to 1 / N. A clock divider (1 that divides and outputs to the parallel latch unit (15)
2) is provided, and the input data (52) and the clock (50) are received and 2N
-1 stage shift circuit is provided and parallel latch unit (1
A shift register unit (14) for outputting to 5) is provided, and 2N-1 shift data from the shift register unit (14) and 1 / N are divided by the clock divider (12). A parallel latch unit (15) that receives the clock and converts it into 2N-1 parallel data is provided, and the selection signal (19) and the parallel latch unit (15) are provided.
Bit interchanger (17) for receiving 2N-1 data from and selecting and outputting N-bit continuous data
And a high-speed serial-parallel converter characterized by including the above. 2. A circuit for inputting serial input data (52) and a clock (50) to restore and convert in units of a predetermined data sequence of N-bit parallel, receive the input clock (50) and receive M / N minutes. A clock that is provided with a pre-stage frequency divider (22a) that divides and outputs to the clock control unit (21), receives a clock control signal (28), and controls and outputs the input signal of the pre-stage frequency divider (22a). A control unit (21) is provided and receives an output signal of the clock control unit (21) to
The post-stage frequency divider (22a) is provided with a post-stage frequency divider (22b) that divides the frequency by M and outputs it to the parallel latch unit (25).
Both the input and the post-stage frequency divider (22b) are divided into 1 / N, receive the input data (52) and the clock (50), and output N +
An N / M-1 stage shift circuit is provided and a shift register section (24) for outputting to a parallel latch section (25) is provided, and a clock divided by the latter stage frequency divider (22b) and the shift A parallel latch unit (25) for receiving N + N / M-1 shift data from the register unit (24) and converting it into N + N / M-1 parallel data, and providing a selection signal (29); The parallel latch unit (25)
A high-speed serial-parallel converter characterized by comprising a bit interchanger (27) which receives 2M + 1 pieces of parallel data from and selects and outputs 2M-bit continuous data.