JPH07231094A - Thin-film transistor and its manufacturing method - Google Patents

Abstract

PURPOSE:To provide a thin-film transistor which can perform an accurate mask aligning without using the lift-off method, and its manufacture. CONSTITUTION:I-type amorphous silicon layer 12 and n<+>-type amorphous silicon layer 14 are formed on a glass substrate 10 and a metal layer 16 consisting of chromium is formed on it by 100-1000Angstrom in thickness. When performing patterning for TFT, a mark for positioning consisting of n<+> layer with i layer as a ground is simultaneously formed at the edge of the substrate. Since the color of chromium differs from that of the i layer, a mark for alignment can be recognized even if the ground is i-type silicon. Using this mark and the succeeding glass masks for photolithography, an accurate alignment can be made.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor which can be applied to various circuits including a shift register of an input circuit of a contact image sensor and a method for manufacturing the thin film transistor.

[0002]

2. Description of the Related Art Generally, a thin film transistor (TFT) is formed through the following steps. First, low pressure CVD (LP
I-type amorphous silicon is deposited by CVD) or plasma CVD (PCVD). Next, this is annealed to turn the amorphous into polycrystalline silicon. As the annealing method, a laser annealing method in which a surface of amorphous silicon is scanned and melted with an ultraviolet laser, or a method of annealing in nitrogen at about 500 to 600 ° C. for about 24 hours is used.

Here, the reason why silicon is annealed to polycrystallize amorphous silicon is that polycrystalline silicon has a higher carrier mobility than amorphous silicon. That is, amorphous silicon having a low carrier mobility can flow a smaller current than polycrystalline silicon even when the same voltage is applied, and thus a TFT using amorphous silicon may not have sufficient performance. . Therefore, by changing the amorphous silicon into polycrystalline silicon, the mobility is increased and a sufficient current can flow.

After the amorphous silicon layer is polycrystallized, a resist is attached to the surface of the polycrystal silicon and ions are implanted to form an n ⁺ layer (or p ⁺ layer; hereinafter the same). Then, the resist is removed, the i layer is patterned, SiO ₂ is formed and patterned on the i layer, holes are formed in the electrode portions, and finally the electrodes are formed to obtain a TFT.

However, for example, in the case of collectively forming a shift register used for driving a photodiode and a blocking diode on a substrate of a contact image sensor, a glass substrate having a length of about 300 mm is used. Therefore, the ion implantation method as described above cannot be used.

Therefore, as an alternative method, the TFT is formed by using the lift-off method so far. First, as shown in FIG. 3A, the i-type amorphous silicon layer 5 is formed on the glass substrate 50 by the same method as described above.
2 is deposited, and a resist 54 having a predetermined pattern is formed thereon. Amorphous silicon 5 doped with phosphorus or boron as shown in FIG.
6 is deposited. Then, when the resist 54 is removed, the silicon layer deposited on the resist is also removed as shown in FIG. 6C, and the silicon layer 56 doped with phosphorus or boron is removed only in the portion where the resist is not deposited first. Remain. Then, the whole is annealed to polycrystallize the amorphous silicon. At this time, phosphorus or boron is activated to simultaneously produce n ⁺ or p ⁺ polycrystalline silicon.
After that, the i-type silicon layer 52 is patterned in the same manner as described above, a SiO ₂ layer is formed and patterned, and an electrode is formed to obtain a TFT.

[0007]

By the way, in FIG. 3, since the resist formed on the i-type silicon layer 52 contains an organic substance, it is generally weak against heat. Therefore, FIG.
When the n ⁺ -type amorphous silicon layer 56 is deposited as shown in (b), the deposition temperature is 100 to 1 at most from room temperature.
It needs to be performed at a temperature of about 50 ° C. Therefore, the doped impurities (phosphorus in the case of the n ⁺ layer and boron in the case of the p ⁺ layer) are not well activated by the subsequent annealing,
Only low resistance can be obtained, and the ohmic characteristics obtained are insufficient.

Also, since the resist is an organic substance, carbon atoms inside the resist remain on the silicon surface, and the T
There is a risk of degrading the properties of FT. For the above reasons, the lift-off method cannot be said to be suitable as a method for forming a TFT used in a shift register for a contact image sensor.

As a method of forming a TFT by a method other than the above, the steps shown in FIGS. 4A to 4G can be considered. That is, first, as shown in FIG.
The i-type amorphous silicon layer 62 and n ⁺ -type amorphous silicon layer 64 is formed on the upper, n ⁺ -type amorphous silicon layer 6 as shown in FIG. (B) by etching
4 is patterned and etched. At this time, marks (not shown) having a predetermined shape for alignment are also formed at several points on the end of the glass substrate 10 at the same time. This mark is composed of an n ⁺ type amorphous silicon layer on which the i type amorphous silicon layer 62 is a base.

Then, this is annealed, and i-type and n ⁺ -type amorphous silicon layers 6 are formed as shown in FIG.
2 and 64 are i-type and n ⁺ -type polycrystalline silicon layers 66 and 68, respectively. Next, the i-type polycrystalline silicon layer 66
Is patterned as shown in FIG. An SiO ₂ layer 70 is deposited thereon as shown in FIG. 6E, and this SiO ₂ layer 70 is further patterned as shown in FIG.
A hole is formed for forming the electrode layer. Finally, the source electrode 72, the gate electrode 74, and the drain electrode 76 are formed to obtain the TFT shown in FIG.

By the way, as shown in FIG. 4D, when patterning the i-type polycrystalline silicon layer 66, the position of the etching mask is set while observing the alignment mark made of the n ⁺ layer with a microscope. I have to decide. However, the i-type polycrystalline silicon layer 66 and the n ⁺ -type polycrystalline silicon layer 68 have almost the same color. Further, since the etching selection ratio of the n ⁺ -type polycrystalline silicon layer 66 and the underlying i-type polycrystalline silicon layer 68 is not sufficient, basically, the n ⁺ -type polycrystalline silicon layer 68 should be formed relatively thin. I have to. Therefore, when the alignment is performed with a microscope, the alignment marks are hardly visible, and there is a problem that the mask for patterning the i-type polycrystalline silicon layer 66 cannot be accurately aligned.

The present invention has been made based on the above circumstances. The semiconductor layer is contaminated with a resist, and since phosphorus-doped or boron-doped amorphous silicon cannot be deposited at a sufficient temperature, the n ⁺ or p ⁺ semiconductor layer cannot be deposited. An n ⁺ or p ⁺ polycrystalline silicon layer and an i-type polycrystalline silicon layer having good properties can be accurately aligned without using the lift-off method, which has a problem that the characteristics cannot be improved. An object of the present invention is to provide a thin film transistor having the above and a manufacturing method thereof.

[0013]

In order to solve the above problems, a method of manufacturing a thin film transistor according to claim 1 comprises a first semiconductor layer, a second semiconductor layer doped with phosphorus or boron, and chromium. A first step of forming a metal layer on the substrate in this order, a second step of annealing the first and second semiconductor layers, and a third step of simultaneously patterning the second semiconductor layer and the metal layer. Step, a fourth step of patterning the first semiconductor layer, an insulating layer is formed on the patterned first semiconductor layer, second semiconductor layer, and metal layer, and predetermined patterning is performed. It is characterized by comprising a fifth step to be carried out and a sixth step of forming a wiring layer on the insulating layer.

According to a second aspect of the present invention, there is provided a method of manufacturing a thin film transistor according to the first aspect, wherein the first and second regions are formed in a region different from a region where the thin film transistor is formed on the substrate by the first step. The semiconductor layer and the metal layer are simultaneously formed, and the alignment mark composed of the second semiconductor layer and the metal layer is simultaneously formed in this region by the third step.

According to a third aspect of the present invention, in the method of manufacturing the thin film transistor according to the first or second aspect, the thickness of the metal layer is 100 angstroms or more and 1000 angstroms or less.

According to a fourth aspect of the present invention, a thin film transistor has a metal layer made of chromium between a semiconductor layer serving as a source and an electrode layer thereof and between a semiconductor layer serving as a drain and an electrode layer thereof. To do.

According to a fifth aspect of the present invention, in a thin film transistor, between a semiconductor layer serving as a source and an electrode layer thereof, and a semiconductor layer serving as a drain and an electrode thereof, which are formed on a substrate forming a sensor element of a contact image sensor. It is characterized by having a metal layer made of chromium between the layers.

[0018]

According to the invention described in claim 1, when the semiconductor layer is annealed by, for example, a thermal annealing method,
Since silicide is formed between the chromium of the metal layer and the semiconductor layer, the ohmic characteristics are improved, and as a result, the electric characteristics of the semiconductor layer are improved such that the field effect mobility is improved. Further, by forming a metal layer made of chromium on the second semiconductor layer and patterning the metal layer at the same time as the second semiconductor layer, in the subsequent step of forming and patterning an insulating layer thereon, When the holes for the electrodes are formed by etching on the second semiconductor layer, the etching can be accurately stopped at the metal layer.

According to a second aspect of the present invention, by the above configuration,
Even if the second semiconductor layer cannot be distinguished from the underlying first semiconductor layer because the first semiconductor layer and the second semiconductor layer have the same color, the uppermost layer of the alignment mark is the second semiconductor layer. Since it is not a layer but a metal layer, the position and shape of this alignment mark can be clearly distinguished from the underlying first semiconductor layer. Therefore, the positioning work thereafter can be accurately performed by using the positioning mark as a mark.

According to the third aspect of the present invention, with the above structure, the metal layer has a thickness of 100 angstroms or more, so that the alignment mark can be sufficiently recognized when the alignment is performed, and 1000 angstroms. By the following, the lower amorphous silicon layer can be effectively polycrystallized when laser annealing is performed.

According to a fourth aspect of the present invention, according to the above configuration,
When the amorphous silicon is annealed to form polycrystalline silicon, a silicide is formed between the chromium of the metal layer and the semiconductor layer, so that the electrical characteristics of the semiconductor layer are improved. Further, when the insulating layer is etched to form the metal layer for wiring, the etching stops accurately at the metal layer, so that it is possible to effectively prevent the etching from reaching the semiconductor layer.

According to a fifth aspect of the present invention, by the above configuration,
By the above method, since the thin film transistor has improved electrical characteristics of the semiconductor layer and can flow more current, it is possible to form the thin film transistor at the same time on the substrate on which the sensor element of the contact image sensor is formed. ,
For example, a shift register for supplying an input pulse of the contact image sensor can be configured.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a partial cross-sectional view showing a series of steps for manufacturing a thin film transistor which is an embodiment of the present invention, and FIG. 2 is an enlarged plan view showing an example of a mark for alignment.

1A to 1G show a process of forming a thin film transistor (TFT) on a glass substrate 10 common to a sensor element (for example, one composed of a photodiode and a blocking diode) of a contact image sensor. It is shown in time series and corresponds to FIG. 4. These TF
T forms a shift register for sequentially supplying input pulses to many sensor elements. Although only one TFT is shown in FIG. 1, several thousands of TFTs are actually formed on one substrate.

As shown in FIG. 1 (a), first, an i of about 1000 to 3000 angstrom is formed on the glass substrate.
-Type amorphous silicon layer 12 and n ⁺ -type amorphous silicon layer 14 of about 100 to 500 angstrom
Deposit. The process up to this point is the same as in the case of FIG. Then, in the present embodiment, a chromium layer 16 having a thickness of 100 to 1000 angstrom is further deposited thereon. This chrome layer 16 is deposited not only in the TFT region but also in a region where an alignment mark described later is formed.

In FIG. 1B, the n ⁺ type amorphous silicon layer 14 is patterned and etched leaving only a predetermined region. At this time, the board shown in FIG.
A cross-shaped alignment mark 30 as shown in FIG.
Patterning to form the. When the n ⁺ type amorphous silicon layer 14 is patterned, the chromium 16 on the upper layer is also patterned at the same time, so that in the present embodiment, the chromium layer 16 is left as it is on the uppermost portion of the alignment mark 30.

Next, annealing is performed in order to polycrystallize the i-type amorphous silicon layer 12 and the n ⁺ -type amorphous silicon layer 14 thus patterned. If amorphous silicon is polycrystallized, the mobility will improve and more current can flow, so
T constituting a shift register for a contact image sensor
It is advantageous as an FT. By passing through this annealing step, the i-type amorphous silicon layer 12 and the n ⁺ -type amorphous silicon layer 14 respectively have an i-type polycrystalline silicon layer (hereinafter simply referred to as i layer) 18 and an n-type amorphous silicon layer 14 as shown in FIG. It becomes an n ⁺ type polycrystalline silicon layer (hereinafter simply referred to as an n ⁺ layer) 20.

As the above annealing method, a laser annealing method at room temperature or a thermal annealing method performed by heating in a nitrogen atmosphere can be used. By the way, the chrome layer 16
The thickness is set to 1000 angstroms or less as described above. When the thickness is set to be more than 1000 angstroms, the laser light is reflected during the laser annealing, and the amorphous silicon layer thereunder is unlikely to be polycrystalline silicon. Because.

Further, in this step, it becomes possible to deposit n ⁺ amorphous silicon at about 250 ° C., which is impossible in the lift-off method. That is, since the lift-off method uses a resist containing an organic substance that is weak against heat,
If the temperature is 50 ° C. or higher, there is a problem that the resist deteriorates or carbon in the resist remains on the surface of the semiconductor layer and contaminates the semiconductor layer. On the other hand, in this embodiment, since the lift-off method is not used, n ⁺ at a temperature of about 250 ° C.
Since the amorphous layer can be deposited, n ⁺ amorphous silicon can be effectively turned into n ⁺ polycrystalline silicon. Therefore, as compared with the case where the lift-off method is used, it is possible to further improve the carrier mobility and increase the amount of current that can flow. If quartz is used for the substrate, thermal annealing can be performed at a higher temperature, and the mobility of polycrystalline silicon is further improved.

The chromium layer 1 is formed on the n ⁺ layer 20 as described above.
The provision of 6 provides several non-conventional advantages associated with this annealing. First, since it is possible to anneal at a high temperature as described above, n
^The impurities doped in the ⁺ layer 20 are well activated, a low resistance value is obtained, and ohmic characteristics are improved. Further, when the high temperature annealing in a state that the chromium layer 16 is formed on the n ⁺ layer 20, n ⁺ layer 20 and chromium layer 16
An alloy of silicon and chromium, that is, a silicide is formed between the n and the layer, and the contact between the Al or chromium electrode formed on the n ⁺ layer is improved to facilitate the flow of current.

Next, as shown in FIG. 1D, the i layer is patterned into a predetermined shape. At this time, if the distance between the edge of the n ⁺ layer 20 and the edge of the i layer 18 is too large, the number of TFTs that can be formed per unit surface decreases. Further, if this interval is too short, the edge of the i layer 18 becomes the n ⁺ layer 2
There is a risk of getting inside the zero edge. For this reason,
When patterning the i layer 18, it is necessary to accurately align the edge of the i layer 18 with the edge of the already deposited n ⁺ layer 20 by about 5 to 10 μm.

By the way, when the alignment mark is formed by the method shown in FIG. 4, the alignment mark made of the n ⁺ layer has the same color as the underlying i layer and its thickness is very thin. This mark is almost invisible even when used. Since the tolerance of placement of the mask for photolithography is about several μm, it is difficult to perform accurate alignment within such tolerance when the mark is invisible. On the other hand, in this embodiment, since the chromium layer 16 was formed on the n ⁺ layer 20, the mark 3 was observed when viewed with a microscope.
The position of 0 and its shape can be clearly recognized.
In order to make the chrome layer 16 fully visible during this alignment, the thickness of the chrome layer 16 should be 100
It is preferable that the thickness is angstrom or more.

On the other hand, on a mask glass (not shown) for photolithography for patterning the i layer 18, marks 32 having the shape shown in FIG. 2B are formed at positions corresponding to the marks 30 on the substrate. ing. When the mark 32 is overlapped with the cross mark 30 shown in FIG.
It becomes a square as shown in FIG. Therefore, while observing the mark 30 on the substrate and the mark 32 on the mask glass with a microscope, the position of the mask glass is adjusted so that they overlap each other as shown in FIG. be able to. And all the marks 3
If 0 and 32 match as shown in FIG. 2C, it means that the mask is accurately aligned for all the elements formed in large numbers on the substrate.

After patterning the i-layer 18, FIG.
As shown in (e), a SiO ₂ layer 22 is deposited on the entire surface, and this is further patterned by, for example, RIE (reactive ion etching) method, as shown in FIG. Also at this time, accurate alignment can be performed by using the mark 30 having chrome formed on the uppermost layer. Finally, as shown in FIG. 6G, a source electrode 27, a gate electrode 28, and a drain electrode 29 are formed,
A TFT is obtained by performing predetermined wiring.

In addition, when patterning the SiO ₂ layer 22, holes 2 for forming electrodes for source and drain are formed.
4 and 26 are also formed at the same time, but at this time, the n ⁺ layer 20
By providing the chrome layer 16 on the above, there are the following advantages. That is, without the chromium layer 16, SiO ₂
When the layer 22 is etched by RIE to form the holes 24 and 26, it is difficult to stop the etching accurately when the etching of the SiO ₂ layer 22 reaches the n ⁺ layer 20, and it is difficult to etch the n ⁺ layer. It may progress. However, by providing the chromium layer 16 on the n ⁺ layer 20 as in the present embodiment, the etching is accurately stopped when the etching reaches the chromium layer 16.

The present invention is not limited to the above embodiment, but various modifications can be made within the scope of the gist thereof. For example, in the above embodiment, the case where the present invention is applied to the drive circuit of the contact image sensor has been described.
Other than this, for example, it can be applied to a switch element of an active matrix type liquid crystal display, various switching elements, and the like.

[0037]

As described above, according to the present invention, since the uppermost metal layer of the alignment mark formed at the edge of the substrate has the metal layer, the alignment mark is distinct from the underlying semiconductor layer. The alignment mark can be used to accurately align the glass mask for photolithography for patterning the first semiconductor layer, for example. Therefore, conventionally, there was no choice but to use the lift-off method, which has various drawbacks because the alignment mark cannot be seen and accurate alignment cannot be performed. Without worrying about deterioration of the n ⁺ layer 25
Provided is a method for manufacturing a thin film transistor, which can improve the characteristics of n ⁺ silicon by depositing at about 0 ° C., prevent unnecessary etching of a semiconductor layer, and enable more accurate alignment. be able to. Further, by manufacturing a thin film transistor using this method, a thin film transistor with various characteristics further improved can be provided.

Further, since the electrical characteristics of the thin film transistor can be improved by the above features, the input pulse supply of the contact image sensor is collectively performed on the same substrate on which the sensor element of the contact image sensor is formed. It is possible to provide a thin film transistor that can configure a shift register for a display.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing a manufacturing process of a thin film transistor which is an embodiment of the present invention in time series.

FIG. 2 is an enlarged plan view showing a shape of an alignment mark used in a manufacturing process of a thin film transistor which is an embodiment of the present invention.

FIG. 3 is a partial cross-sectional view showing a manufacturing process of an example thin film transistor using a conventional method in time series.

FIG. 4 is a partial cross-sectional view showing a manufacturing process of another example of a thin film transistor using a conventional method in time series.

[Explanation of symbols]

10, 50, 60 Glass substrate 12, 52, 62 i-type amorphous silicon layer 14, 56, 64 n ⁺ type amorphous silicon layer 16 Chrome layer 18, 66 i-type polycrystalline silicon layer (i layer) 20, 68 n ⁺ type Polycrystalline silicon layer (n ⁺ layer) 22, 70 SiO ₂ layer 27, 72 Source electrode 28, 74 Gate electrode 29, 76 Drain electrode 54 Resist

Claims (5)

[Claims] 1. A first step of forming a first semiconductor layer, a second semiconductor layer doped with phosphorus or boron, and a metal layer made of chromium in this order on a substrate, and the first and second steps. A second step of annealing the semiconductor layer, a third step of simultaneously patterning the second semiconductor layer and the metal layer, a fourth step of patterning the first semiconductor layer, and the patterned From a fifth step of forming an insulating layer on the first semiconductor layer, the second semiconductor layer, and the metal layer and performing a predetermined patterning, and a sixth step of forming a wiring layer on the insulating layer. And a method of manufacturing a thin film transistor. 2. The first and second semiconductor layers and the metal layer are simultaneously formed in a region different from the region where the thin film transistor is formed on the substrate by the first step, and the first region and the metal layer are formed in the different region. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the alignment mark composed of the second semiconductor layer and the metal layer is simultaneously formed in the third step. 3. The method for manufacturing a thin film transistor according to claim 1, wherein the thickness of the metal layer is 100 angstroms or more and 1000 angstroms or less. 4. A thin film transistor comprising a metal layer made of chromium between a semiconductor layer serving as a source and its electrode layer and between a semiconductor layer serving as a drain and its electrode layer. 5. A semiconductor layer serving as a source and an electrode layer thereof, and a semiconductor layer serving as a drain and an electrode layer thereof, which are formed on a substrate forming a sensor element of a contact image sensor. A thin film transistor having a metal layer made of chromium.