JPH07231040A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH07231040A
JPH07231040A JP2152194A JP2152194A JPH07231040A JP H07231040 A JPH07231040 A JP H07231040A JP 2152194 A JP2152194 A JP 2152194A JP 2152194 A JP2152194 A JP 2152194A JP H07231040 A JPH07231040 A JP H07231040A
Authority
JP
Japan
Prior art keywords
fuse
film
barrier metal
semiconductor device
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2152194A
Other languages
Japanese (ja)
Inventor
Shigenori Ichinose
茂則 一ノ瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2152194A priority Critical patent/JPH07231040A/en
Publication of JPH07231040A publication Critical patent/JPH07231040A/en
Withdrawn legal-status Critical Current

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  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the reliability of a semiconductor device which has a fuse by reducing the depth of holes generated on the protecting film and the interlayer insulating film under the protecting film at the time of fusing the fuse. CONSTITUTION:A semiconductor device comprises a fuse which is formed of a conductive film 9 on the topmost layer insulating film 8 on a semiconductor substrate 1. Therefore, the conductive film 9 is the barrier metal film inserted between a pad 10 and a bump 11.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に係り,特
に, フューズ溶断型半導体集積回路装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a fuse blown semiconductor integrated circuit device.

【0002】集積回路の外部導出端子であるアルミニウ
ム(Al)パッド上に凸状のバンプを形成する際に,パッド
とバンプ間の反応を防止するためバリアメタル膜がその
間に挿入される。
When forming a convex bump on an aluminum (Al) pad which is an external lead terminal of an integrated circuit, a barrier metal film is inserted between the pad and the bump to prevent a reaction between the pads.

【0003】本発明は,パッドとバンプ間にバリアメタ
ル膜を有するデバイスであって,冗長回路用のフューズ
を必要とするメモリLSI, ウエハプロセスによる素子特
性のバラツキの微調整を実施するためのフューズを必要
とするアナログLSI 等に利用することができる。
The present invention relates to a device having a barrier metal film between a pad and a bump, which requires a fuse for a redundant circuit, a fuse for finely adjusting variations in element characteristics due to a wafer process. Can be used for analog LSIs that require

【0004】[0004]

【従来の技術】図2(A),(B) は従来のフューズの説明図
である。図2(A) において, 1は半導体基板, 2は1層
目層間絶縁膜, 3は1層目配線, 4は2層目層間絶縁
膜, 5, 6 は層間接続導体(VIA), 7は2層目配線, 8は
最上層の保護膜である。
2. Description of the Related Art FIGS. 2A and 2B are explanatory views of a conventional fuse. In FIG. 2 (A), 1 is a semiconductor substrate, 2 is a first layer interlayer insulating film, 3 is a first layer wiring, 4 is a second layer interlayer insulating film, 5 and 6 are interlayer connecting conductors (VIA), and 7 is The second layer wiring, 8 is the uppermost protective film.

【0005】フューズは2層目配線 7を用いて形成さ
れ,1層目配線の切断部に層間接続導体 5により接続さ
れている。また,最上層の保護膜は,フューズの切断を
容易にするためフューズ上においてフォトリソグラフィ
工程により薄く形成される。
The fuse is formed by using the second layer wiring 7, and is connected to the cut portion of the first layer wiring by the interlayer connecting conductor 5. Further, the uppermost protective film is formed thin on the fuse by a photolithography process to facilitate the cutting of the fuse.

【0006】例えば, メモリLSI では冗長信号を与える
手段の一つとして, LSI 内部に設けられたアルミニウム
(Al)配線やポリシリコン膜からなるフューズにレーザ光
等のエネルギービームを照射して, フューズを切断して
電気的に開放することにより信号を与えている。
For example, in a memory LSI, as one of means for giving a redundant signal, an aluminum provided inside the LSI is used.
A signal is given by irradiating a fuse composed of (Al) wiring and a polysilicon film with an energy beam such as a laser beam, and cutting the fuse to electrically open it.

【0007】図2(B) はレーザ光の照射により,フュー
ズを切断した状態を示す。
FIG. 2B shows a state in which the fuse is blown by the irradiation of laser light.

【0008】[0008]

【発明が解決しようとする課題】従来例の構造のフュー
ズでは,フューズ溶断の際に保護膜 8を貫通して, その
下層の層間絶縁膜まで届く穴を開けてしまい,この穴は
チップの素子領域上にあるため,デバイスの信頼性を大
幅に低下させていた。
In the fuse having the structure of the conventional example, when the fuse is blown, a hole that penetrates the protective film 8 and reaches the underlying interlayer insulating film is opened, and this hole is the element of the chip. Since it is on the area, the reliability of the device has been significantly reduced.

【0009】また,フューズの切断を容易にするため
に, 保護膜の一部を除去するリソグラフィ工程のフォト
マスクを用意する必要があった。本発明はフューズ溶断
の際に保護膜やその下の層間絶縁膜に生じる穴の深さを
低減して,デバイスの信頼性を向上することを目的とす
る。
Further, in order to facilitate the cutting of the fuse, it is necessary to prepare a photomask for the lithography process for removing a part of the protective film. An object of the present invention is to reduce the depth of the holes formed in the protective film and the interlayer insulating film thereunder when the fuse is blown, and improve the reliability of the device.

【0010】[0010]

【課題を解決するための手段】上記課題の解決は, 1)半導体基板 1上に被着された最上層の絶縁膜 8上に
形成された導電膜 9からなるフューズを有する半導体装
置,あるいは 2)前記導電膜 9が, パッド10とバンプ11間に挿入する
バリアメタル膜である前記1)記載の半導体装置により
達成される。
Means for Solving the Problems To solve the above problems, 1) a semiconductor device having a fuse made of a conductive film 9 formed on an uppermost insulating film 8 deposited on a semiconductor substrate 1, or 2 3. The semiconductor device according to 1), wherein the conductive film 9 is a barrier metal film inserted between the pad 10 and the bump 11.

【0011】[0011]

【作用】本発明ではパッドとバンプ間に形成されるバリ
アメタル膜は最上層の保護膜の更に上層に形成されるた
め,このバリアメタル膜を用いてフューズを形成すれ
ば,バリアメタル膜は最上層に存在するため, フューズ
溶断の際に保護膜やその下の層間絶縁膜に生じる穴の深
さを最小限に抑えることができる。
In the present invention, the barrier metal film formed between the pad and the bump is formed on the uppermost layer of the uppermost protective film. Therefore, if the fuse is formed by using this barrier metal film, the barrier metal film will be the maximum. Since it exists in the upper layer, it is possible to minimize the depth of the holes formed in the protective film and the interlayer insulating film below it when the fuse is blown.

【0012】また,バリアメタル膜は最上層に存在する
ため, 従来例のようにバリアメタル膜の上層に形成され
た保護膜の一部を除去するリソグラフィ工程を必要とし
ないことと,パッドを形成した後, 通常は余分なバリア
メタルをリソグラフィ工程で除去するが,フューズの形
成はその工程で使用されるマスクにフューズのパターン
を挿入することで実現できるため,製造工程の削減がで
きる。
Further, since the barrier metal film is present in the uppermost layer, there is no need for a lithography process for removing a part of the protective film formed on the upper layer of the barrier metal film unlike the conventional example, and the pad is formed. After that, the extra barrier metal is usually removed by the lithography process, but the fuse formation can be realized by inserting the fuse pattern into the mask used in the process, thus reducing the manufacturing process.

【0013】[0013]

【実施例】図1(A) 〜(C) は本発明の実施例のフューズ
の説明図である。図1(A) において, 1は半導体基板,
2は1層目層間絶縁膜, 3は1層目配線, 4は2層目層
間絶縁膜で硼素を含むりん珪酸ガラス(BPSG)膜, 5, 6
は層間接続導体(VIA), 7は2層目配線, 8は最上層の絶
縁性の保護膜, 9はバリアメタル膜でチタン(Ti)/パラ
ジウム(Pd)積層膜, またはTi/ニッケル(Ni)積層膜, 10
はAl合金膜等からなるパッド (電源パッドでも信号パッ
ドでもよい), 11は金(Au), 鉛錫(PbSn)等からなるバン
プである。
1 (A) to 1 (C) are explanatory views of a fuse of an embodiment of the present invention. In FIG. 1 (A), 1 is a semiconductor substrate,
2 is the first interlayer insulating film, 3 is the first wiring layer, 4 is the second interlayer insulating film, a phosphosilicate glass (BPSG) film containing boron, 5, 6
Is an inter-layer connection conductor (VIA), 7 is a second layer wiring, 8 is an uppermost insulating protective film, 9 is a barrier metal film of titanium (Ti) / palladium (Pd) laminated film, or Ti / nickel (Ni ) Laminated film, 10
Is a pad made of Al alloy film or the like (which may be a power supply pad or a signal pad), and 11 is a bump made of gold (Au), lead tin (PbSn) or the like.

【0014】フューズはバリアメタル膜 9を用いて次の
ように形成される。まず, リソグラフィ技術を用いて保
護膜 8を開口し,1層目配線の切断部に層間接続導体
5, 6 により接続された2層目配線 7の接続部を露出さ
せ, この上を覆って基板上全面にバリアメタル膜 9を成
膜し,これをパターニングして形成される。
The fuse is formed using the barrier metal film 9 as follows. First, a protective film 8 is opened by using a lithographic technique, and an interlayer connecting conductor is formed at a cut portion of the first layer wiring.
The connection portion of the second-layer wiring 7 connected by 5, 6 is exposed, a barrier metal film 9 is formed on the entire surface of the substrate so as to cover the connection portion, and this is patterned.

【0015】なお,上記の工程で同時に,保護膜 8を開
口してパッド10を露出させ,その上にバリアメタル膜 9
を形成し,その上にバンプ11を形成する。図1(B) はレ
ーザ光の照射により,フューズを切断した状態を示す。
At the same time in the above process, the protective film 8 is opened to expose the pad 10, and the barrier metal film 9 is formed thereon.
Are formed, and the bumps 11 are formed thereon. Figure 1 (B) shows the state in which the fuse is blown by the irradiation of laser light.

【0016】図示のように,実施例ではフューズが最上
層にあるため,フューズ溶断のために生ずる穴は浅くな
る。図1(C) は実施例のフューズの平面図である。
As shown in the figure, in the embodiment, since the fuse is in the uppermost layer, the holes caused by the blowout of the fuse are shallow. FIG. 1C is a plan view of the fuse of the embodiment.

【0017】この例では,バリアメタル膜 9で形成され
たフューズの切断位置の幅を細くして切断を容易にして
いる。実施例ではレーザ光による溶断について説明した
が,本発明によればフューズが最上層に存在するため,
素子領域の外側に延長して形成可能なため,フューズの
両端にプローブを直接接触させて電流を流し,ジュール
熱により溶断することも可能である。
In this example, the fuse formed of the barrier metal film 9 has a narrow cutting position to facilitate the cutting. Although the fusing by the laser beam is described in the embodiment, according to the present invention, since the fuse exists in the uppermost layer,
Since it can be formed to extend outside the element region, it is also possible to directly contact the probes at both ends of the fuse to pass an electric current, and to melt the fuse by Joule heat.

【0018】さらに,本発明ではフューズが最上層に存
在するため,配線の切断のみならず,集束イオンビーム
(FIB) 装置等により配線を接続することも可能であり,
フューズの再生も可能である。
Further, in the present invention, since the fuse exists in the uppermost layer, not only the wiring is cut but also the focused ion beam is used.
(FIB) It is also possible to connect the wiring by a device,
It is also possible to reproduce the fuse.

【0019】[0019]

【発明の効果】本発明によれば,フューズ溶断の際に保
護膜やその下の層間絶縁膜に生じる穴の深さを低減で
き,デバイスの信頼性を向上することができる。
According to the present invention, it is possible to reduce the depth of the holes formed in the protective film and the underlying interlayer insulating film when the fuse is blown, and improve the reliability of the device.

【0020】また,フューズの形成位置が自由に選べる
ため,いろいろな切断方法が利用でき,また配線の接続
も可能となった。さらに,フューズ形成のためのリソグ
ラフィ工程を1工程削減することができる。
Further, since the fuse forming position can be freely selected, various cutting methods can be used and wiring can be connected. Further, it is possible to reduce one lithography process for forming the fuse.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の実施例のフューズの説明図FIG. 1 is an explanatory view of a fuse according to an embodiment of the present invention.

【図2】 従来のフューズの説明図FIG. 2 is an explanatory view of a conventional fuse.

【符号の説明】[Explanation of symbols]

1 半導体基板 2 1層目層間絶縁膜 3 1層目配線 4 2層目層間絶縁膜 5, 6 層間接続導体(VIA) 7 2層目配線 8 最上層の保護膜 9 バリアメタル膜でTi/Pd積層膜, またはTi/Ni積層
膜 10 パッド 11 Au, PbSn等からなるバンプ
1 Semiconductor substrate 2 1st layer interlayer insulating film 3 1st layer wiring 4 2nd layer interlayer insulating film 5, 6 Interlayer connection conductor (VIA) 7 2nd layer wiring 8 Topmost protective film 9 Barrier metal film Ti / Pd Laminated film or Ti / Ni laminated film 10 Pad 11 Bump made of Au, PbSn, etc.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板(1) 上に被着された最上層の
絶縁膜(8) 上に形成された導電膜(9) からなるフューズ
を有することを特徴とする半導体装置。
1. A semiconductor device having a fuse made of a conductive film (9) formed on an uppermost insulating film (8) deposited on a semiconductor substrate (1).
【請求項2】 前記導電膜(9) がパッド(10)とバンプ(1
1)間に挿入するバリアメタル膜であることを特徴とする
請求項1記載の半導体装置。
2. The conductive film (9) comprises a pad (10) and a bump (1).
The semiconductor device according to claim 1, which is a barrier metal film inserted between 1).
JP2152194A 1994-02-18 1994-02-18 Semiconductor device Withdrawn JPH07231040A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2152194A JPH07231040A (en) 1994-02-18 1994-02-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2152194A JPH07231040A (en) 1994-02-18 1994-02-18 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH07231040A true JPH07231040A (en) 1995-08-29

Family

ID=12057268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2152194A Withdrawn JPH07231040A (en) 1994-02-18 1994-02-18 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH07231040A (en)

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Effective date: 20010508