JPH07231036A - Manufacture of semiconductor substrate - Google Patents
Manufacture of semiconductor substrateInfo
- Publication number
- JPH07231036A JPH07231036A JP2072994A JP2072994A JPH07231036A JP H07231036 A JPH07231036 A JP H07231036A JP 2072994 A JP2072994 A JP 2072994A JP 2072994 A JP2072994 A JP 2072994A JP H07231036 A JPH07231036 A JP H07231036A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor substrate
- single crystal
- film
- substrate
- polishing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体基板の製造方
法に関し、特にＳＯＩ（Ｓｉｌｉｃｏｎ Ｏｎ Ｉｎｓ
ｕｌａｔｏｒ）構造の半導体製造分野で利用できる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to SOI (Silicon On Ins).
It can be used in the field of semiconductor manufacturing of an ultor) structure.
【０００２】[0002]
【従来の技術】従来、この種の半導体基板の製造方法と
しては、特開平１−３０２８３７号公報記載の技術が知
られている。この従来技術は、半導体基板の表面に凹凸
部を形成し、次いで、この基板表面に絶縁膜を形成した
後、この絶縁膜上に表面が平坦な半導体層を形成し、さ
らに半導体層表面を貼り付け面として他の基板を貼り付
け、半導体基板を裏面から絶縁膜が露出するまで研磨し
てＳＯＩ基板を製造するというものである。2. Description of the Related Art Conventionally, as a method for manufacturing a semiconductor substrate of this type, a technique described in Japanese Patent Laid-Open No. 1-302837 is known. According to this conventional technique, an uneven portion is formed on the surface of a semiconductor substrate, an insulating film is formed on the surface of the substrate, a semiconductor layer having a flat surface is formed on the insulating film, and then the surface of the semiconductor layer is attached. Another substrate is attached as the attachment surface, and the semiconductor substrate is polished from the back surface until the insulating film is exposed to manufacture an SOI substrate.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな従来技術にあっては、研磨の負担を少なくするため
にストッパとしての絶縁膜の近くまで研削により半導体
基板を削っているが、裏面基準で行っているため精度良
く研削できたとしても、図７に示すように半導体基板１
の研磨で取り除かなければならない膜厚はウェハ面内で
大きくばらつく（ｄ1＜ｄ2）という問題があった。この
ように研磨取代がばらつくと、図８に示すように、絶縁
膜３が露出するタイミングが異なり、早く露出した絶縁
膜３近くのＳＯＩ層３Ａの膜厚が研磨底ずりによって薄
くなるという問題がある。この研磨底ずりとは、図９に
示すように、絶縁膜３が露出した状態で研磨を続けると
ＳＯＩ層３Ａの部分が絶縁膜３より研磨され易いため、
研磨クロス４が変形し絶縁膜基準面よりも研磨面が低く
なることをいう。However, in such a conventional technique, the semiconductor substrate is ground by near the insulating film as a stopper in order to reduce the burden of polishing. As shown in FIG. 7, the semiconductor substrate 1 can be ground accurately even if it is carried out.
There is a problem in that the film thickness that has to be removed by polishing is greatly varied within the wafer surface (d 1 <d 2 ). If the polishing stock removal varies in this way, as shown in FIG. 8, there is a problem in that the timing at which the insulating film 3 is exposed is different, and the SOI layer 3A near the insulating film 3 that is exposed earlier becomes thinner due to polishing bottom shear. is there. As shown in FIG. 9, when the polishing is continued with the insulating film 3 exposed, the portion of the SOI layer 3A is more easily polished than the insulating film 3 as shown in FIG.
It means that the polishing cloth 4 is deformed and the polishing surface becomes lower than the insulating film reference surface.
【０００４】この発明が解決しようとする課題は、薄膜
ＳＯＩ形成のための研磨において、その除去量がウェハ
面内で均一となり、研磨ストッパの露出のタイミングが
ウェハ面内で略同じとなる半導体基板の製造方法を得る
には、どのような手段を講じればよいかという点にあ
る。A problem to be solved by the present invention is that in polishing for forming a thin film SOI, the removal amount is uniform in the wafer surface, and the exposure timing of the polishing stopper is substantially the same in the wafer surface. What kind of means should be taken to obtain the manufacturing method of?
【０００５】[0005]
【課題を解決するための手段】そこで、この発明は、単
結晶半導体基板の表面に凹部を形成し、該凹部に絶縁物
でなる充填物を埋め込んだ後、表面を絶縁膜で覆った支
持基板を該単結晶半導体基板の表面に貼り合わせ、当該
単結晶半導体基板の裏面を前記充填物に達するまで研磨
して単結晶島領域を形成することを、その解決手段とし
ている。SUMMARY OF THE INVENTION Therefore, according to the present invention, a single crystal semiconductor substrate is provided with a concave portion on the surface thereof, a filling material made of an insulating material is embedded in the concave portion, and then the surface is covered with an insulating film. Is attached to the front surface of the single crystal semiconductor substrate, and the back surface of the single crystal semiconductor substrate is polished until it reaches the filling material to form a single crystal island region.
【０００６】また、具体的には、単結晶半導体基板の表
面に凹部を形成し、該凹部に絶縁物でなる充填物を埋め
込む工程と、表面を絶縁膜で覆った第１支持基板を該単
結晶半導体基板の表面に貼り合わせる工程と、前記単結
晶半導体基板の裏面を前記充填物に達するまで研磨する
工程と、前記単結晶半導体基板の研磨面にデバイス形成
領域を画成するための段差を形成し、該研磨面及び段差
面に沿って表面に研磨ストッパとしての酸化膜を形成す
る工程と、前記段差及び前記研磨面上に材料膜を付着さ
せ、該材料膜表面を平坦化する工程と、前記材料膜表面
に第２支持基板を貼り合わせる工程と、前記第１支持基
板側を前記絶縁膜に達するまで研磨する工程と、前記絶
縁膜及び前記充填物をエッチングして除去する工程と、
前記エッチングにより露出した単結晶半導体基板を前記
酸化膜に達するまで研磨して単結晶島領域を形成する工
程とを備える構成としている。ここで、材料膜とは、Ｂ
ＰＳＧ，ＰＳＧ等の不純物ドープの酸化シリコンを用い
る。Further, specifically, a step of forming a concave portion on the surface of the single crystal semiconductor substrate, filling the concave portion with a filling made of an insulating material, and the first supporting substrate whose surface is covered with an insulating film A step of adhering to the front surface of the crystal semiconductor substrate, a step of polishing the back surface of the single crystal semiconductor substrate until reaching the filling, and a step for defining a device formation region on the polished surface of the single crystal semiconductor substrate. Forming, and forming an oxide film as a polishing stopper on the surface along the polishing surface and the step surface; and a step of adhering a material film on the step and the polishing surface to flatten the material film surface. Bonding a second supporting substrate to the surface of the material film, polishing the first supporting substrate side until reaching the insulating film, and etching and removing the insulating film and the filler.
And a step of polishing the single crystal semiconductor substrate exposed by the etching until it reaches the oxide film to form a single crystal island region. Here, the material film is B
Impurity-doped silicon oxide such as PSG or PSG is used.
【０００７】また、前記単結晶半導体基板の裏面を前記
充填物に達するまで研磨する工程の後に、該充填物の一
部を表面よりエッチング除去しこの除去した部分に前記
充填物とエッチング選択比をとれる材料でなるエッチン
グストッパ層を埋め込む工程を備え、前記酸化膜を形成
した際に、前記充填物と該酸化膜を形成した際に、前記
充填物と該酸化膜との間にストッパ層が介在するように
したことを構成としている。Further, after the step of polishing the back surface of the single crystal semiconductor substrate until reaching the filling material, a part of the filling material is removed by etching from the front surface, and an etching selection ratio between the filling material and the filling material is applied to the removed portion. And a stopper layer interposed between the filling material and the oxide film when the filling film and the oxide film are formed when the oxide film is formed. It is configured to do so.
【０００８】[0008]
【作用】この発明においては、単結晶半導体基板表面の
凹部に埋め込んだ充填物が単結晶半導体基板の裏面側か
らの研磨のストッパとなる。また、（第１）支持基板の
表面に形成した絶縁膜は、第１支持基板の研磨のストッ
パとして作用する。In the present invention, the filling material embedded in the concave portion on the front surface of the single crystal semiconductor substrate serves as a stopper for polishing from the back surface side of the single crystal semiconductor substrate. Further, the insulating film formed on the surface of the (first) support substrate acts as a stopper for polishing the first support substrate.
【０００９】そして、単結晶半導体基板を裏面から充填
物が露出するまで研磨した状態で、充填物を一部除去し
て、この充填物（例えばＳｉＯ2）とエッチング選択比
をとれる材料（例えばポリシリコン等）でなるエッチン
グストッパ層を埋め込むことにより、絶縁膜及び充填物
をエッチングする際にストッパ層を残すことができる。
単結晶半導体基板の充填物の一部を除去してエッチング
ストッパ層を埋め込み、さらに単結晶半導体基板のスト
ッパ層を埋め込んだ面にデバイス形成領域（ＳＯＩ領
域）を画成するための段差を形成し、この段差面及び研
磨面に沿って表面酸化膜を形成すると、この表面酸化膜
と充填物との間にエッチングストッパ層を介在させるこ
とができる。上記したように、絶縁膜及び充填物をエッ
チングしてエッチングストッパ層を残した状態では、最
初に形成した凹部の深さ分だけの単結晶半導体基板が残
っている。この深さ寸法は、エッチングによって均一に
短く制御できるため、ウェハ面内均一性は良好となる。
この状態では研磨量は少なくてよく、表面酸化膜をウェ
ハ面内で略同時に露出させることができる。このため、
ＳＯＩ層（単結晶半導体）の膜厚は必要以上に研磨され
て膜減り（底ずり）することなく、ウェハ面内で均一に
することが可能となる。Then, while the single crystal semiconductor substrate is polished from the back surface until the filling is exposed, the filling is partially removed, and a material (for example, poly) which can obtain an etching selection ratio with the filling (for example, SiO 2 ). By embedding an etching stopper layer made of silicon or the like, the stopper layer can be left when the insulating film and the filling material are etched.
A part of the filling material of the single crystal semiconductor substrate is removed to fill the etching stopper layer, and a step for defining a device formation region (SOI region) is formed on the surface of the single crystal semiconductor substrate where the stopper layer is filled. When the surface oxide film is formed along the step surface and the polished surface, the etching stopper layer can be interposed between the surface oxide film and the filling material. As described above, in the state where the insulating film and the filling material are etched to leave the etching stopper layer, the single crystal semiconductor substrate remains by the depth of the first formed recess. Since this depth dimension can be uniformly controlled to be short by etching, the uniformity within the wafer surface becomes good.
In this state, the polishing amount may be small, and the surface oxide film can be exposed substantially at the same time on the wafer surface. For this reason,
The film thickness of the SOI layer (single crystal semiconductor) can be made uniform within the wafer surface without polishing (undesiring) due to polishing more than necessary.
【００１０】[0010]
【実施例】以下、この発明に係る半導体基板の製造方法
の詳細を図面に示す実施例に基づいて説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the method for manufacturing a semiconductor substrate according to the present invention will be described below with reference to the embodiments shown in the drawings.
【００１１】本実施例では、先ず図１（Ａ）に示すよう
に、単結晶半導体基板としてのシリコン基板１１の表面
に、フォトリソグラフィー技術及び異方性エッチング技
術を用いて凹部としてのトレンチ１１Ａを形成する。次
いで、図１（Ｂ）に示すように、シリコン基板１１表面
に絶縁物としてのＳｉＯ2膜１２を例えばＣＶＤ法によ
って堆積させ、トレンチ１１Ａを埋め込む。その後、シ
リコン基板１１面上のＳｉＯ2膜１２をエッチバックし
て除去し、トレンチ１１Ａ内のみに充填物としてのＳｉ
Ｏ2膜１２を残す。In this embodiment, first, as shown in FIG. 1A, a trench 11A as a recess is formed on the surface of a silicon substrate 11 as a single crystal semiconductor substrate by using photolithography technology and anisotropic etching technology. Form. Next, as shown in FIG. 1B, a SiO 2 film 12 as an insulator is deposited on the surface of the silicon substrate 11 by, for example, the CVD method to fill the trench 11A. Then, the SiO 2 film 12 on the surface of the silicon substrate 11 is etched back and removed, and only the trench 11A is filled with Si as a filling material.
The O 2 film 12 is left.
【００１２】次に、図１（Ｃ）に示すように、他のシリ
コン基板でなる第１支持基板１３の表面にシリコン酸化
膜１４を形成し、シリコン基板１１の表面に貼り合わせ
て図２（Ａ）に示すような構造とする。その後、シリコ
ン基板１１の裏面側から研磨を行い、図２（Ｂ）に示す
ように、ストッパとしてのＳｉＯ2膜１２が露出した時
点で研磨を停止させる。このとき、シリコン基板１１は
ＳｉＯ2膜１２に囲まれた構造となっている。Next, as shown in FIG. 1C, a silicon oxide film 14 is formed on the surface of the first support substrate 13 made of another silicon substrate, and the silicon oxide film 14 is attached to the surface of the silicon substrate 11 to form the silicon oxide film 14 shown in FIG. The structure is as shown in A). Then, polishing is performed from the back surface side of the silicon substrate 11, and as shown in FIG. 2B, polishing is stopped when the SiO 2 film 12 as a stopper is exposed. At this time, the silicon substrate 11 has a structure surrounded by the SiO 2 film 12.
【００１３】次に、シリコン基板１１の研磨面側をウェ
ットエッチング（例えばフッ酸（ＨＦ）溶液を用いる）
を行って、図２（Ｃ）に示すように、ＳｉＯ2膜１２を
約半分の膜厚となるように除去する。Next, the polished surface side of the silicon substrate 11 is wet-etched (for example, using a hydrofluoric acid (HF) solution).
Then, as shown in FIG. 2C, the SiO 2 film 12 is removed so that the film thickness becomes about half.
【００１４】その後、図３（Ａ）に示すように、シリコ
ン基板１１の研磨面側に、ポリシリコン膜１５をＣＶＤ
法により堆積させて前工程でＳｉＯ2膜１２を一部除去
した部分を埋め込む。次いで、ポリシリコン膜１５を研
磨し、図３（Ｂ）に示すように、シリコン基板１１の研
磨面を露出させる。このとき、トレンチ内には、エッチ
ングストッパ層としてのポリシリコン膜１５が埋め込ま
れた状態となる。Thereafter, as shown in FIG. 3A, a polysilicon film 15 is formed on the polishing surface side of the silicon substrate 11 by CVD.
And the SiO 2 film 12 is partially removed in the previous step to bury it. Next, the polysilicon film 15 is polished to expose the polished surface of the silicon substrate 11, as shown in FIG. At this time, the polysilicon film 15 as an etching stopper layer is buried in the trench.
【００１５】さらに、シリコン基板１１の研磨面側に、
リソグラフィー技術及びドライエッチング技術を用い
て、図３（Ｃ）に示すように、デバイス形成領域（ＳＯ
Ｉ層形成領域）を画成するための段差（凹部）１６Ａ，
１６Ｂを形成する。なお、段差１６Ａはシリコン基板１
１研磨面に形成した凹部であり、段差１６Ｂはポリシリ
コン膜１５の膜厚を減らして形成した凹部である。この
ような段差の形成には、例えばエッチングガスにＨＢｒ
を用いたドライエッチングを行う。Further, on the polishing surface side of the silicon substrate 11,
By using the lithography technique and the dry etching technique, as shown in FIG.
A step (recess) 16A for defining an I layer forming region,
16B is formed. The step 16A is formed on the silicon substrate 1
The recess 16B is a recess formed on one polished surface, and the step 16B is a recess formed by reducing the thickness of the polysilicon film 15. To form such a step, for example, HBr is used as an etching gas.
Dry etching is performed.
【００１６】次に、同図（Ｃ）に示すように、このよう
な段差１６Ａ，１６Ｂを形成した後に、表面酸化を行っ
て表面に沿ったシリコン酸化膜１７を形成する。Next, as shown in FIG. 1C, after forming such steps 16A and 16B, surface oxidation is performed to form a silicon oxide film 17 along the surface.
【００１７】次に、図４（Ａ）に示すように、シリコン
酸化膜１７上にポリシリコン膜１８をＣＶＤ法によって
堆積させ段差を埋め込み、その後、ポリシリコン膜１８
の表面を研磨して平坦にする。そして、図４（Ｂ）に示
すように、なお、本実施例では、ポリシリコンを用いた
がＢＰＳＧ，ＰＳＧなどの不純物ドープ酸化シリコンで
もよい。このポリシリコン膜１８の研磨面に、他のシリ
コン基板である第２支持基板１９を貼り合わせる。その
後、第１支持基板１３を裏面から研磨し、ストッパとし
てのシリコン酸化膜１４が露出したときに研磨を止め、
図５（Ａ）に示すような構造にする。ここで、シリコン
酸化膜１４はストッパとしての機能が十分であるため、
全面が露出するまで研磨を続けることが可能である。Next, as shown in FIG. 4A, a polysilicon film 18 is deposited on the silicon oxide film 17 by the CVD method to fill the step, and then the polysilicon film 18 is formed.
The surface of is polished and made flat. Further, as shown in FIG. 4B, although polysilicon is used in this embodiment, impurity-doped silicon oxide such as BPSG or PSG may be used. A second support substrate 19, which is another silicon substrate, is attached to the polished surface of the polysilicon film 18. Then, the first support substrate 13 is polished from the back surface, and when the silicon oxide film 14 as a stopper is exposed, the polishing is stopped,
The structure is as shown in FIG. Here, since the silicon oxide film 14 has a sufficient function as a stopper,
It is possible to continue polishing until the entire surface is exposed.
【００１８】次に、シリコン酸化膜１４及びＳｉＯ2膜
１２を除去し、ポリシリコン膜１５を除去しないような
エッチング選択比をとれるウェットエッチング（例えば
フッ酸溶液を用いる）を行って、図５（Ｂ）に示すよう
にポリシリコン膜１５でエッチングを止める。このた
め、ポリシリコン膜１５の下のシリコン酸化膜１７が消
失されることが防止でき、次工程でのシリコン基板１１
の研磨でのストッパとしてシリコン酸化膜１７を用いる
ことができる。図５（Ｃ）は、シリコン基板１１をシリ
コン酸化膜１７が露出するまで研磨を行って単結晶シリ
コンでなるＳＯＩ層１１Ｂを形成した状態を示してい
る。なお、本実施例によれば、図５（Ｂ）の状態ですで
にシリコン基板１１はかなり薄く且つ均一になっている
ため、シリコン酸化膜１７の露出は、略同時に起り、均
一な膜厚のＳＯＩ層１１Ｂが形成できる。Next, the silicon oxide film 14 and the SiO 2 film 12 are removed, and wet etching (for example, using a hydrofluoric acid solution) is performed so as to obtain an etching selection ratio such that the polysilicon film 15 is not removed. As shown in B), etching is stopped at the polysilicon film 15. Therefore, the silicon oxide film 17 under the polysilicon film 15 can be prevented from disappearing, and the silicon substrate 11 in the next step can be prevented.
The silicon oxide film 17 can be used as a stopper for polishing. FIG. 5C shows a state where the silicon substrate 11 is polished until the silicon oxide film 17 is exposed to form the SOI layer 11B made of single crystal silicon. According to the present embodiment, since the silicon substrate 11 is already quite thin and uniform in the state of FIG. 5B, the silicon oxide films 17 are exposed substantially at the same time, and the silicon oxide film 17 has a uniform film thickness. The SOI layer 11B can be formed.
【００１９】以上、実施例について説明したが、この発
明は、これに限定されるものではなく、構成の要旨に付
随する各種の設計変更，材料変更が可能である。Although the embodiment has been described above, the present invention is not limited to this, and various design changes and material changes accompanying the gist of the configuration can be made.
【００２０】例えば、上記実施例においては、図１
（Ｃ）に示したように、第１支持基板１３にシリコン酸
化膜１４を形成したが、図６に示すように、シリコン基
板１１側に形成しても勿論よい。For example, in the above embodiment, FIG.
Although the silicon oxide film 14 is formed on the first support substrate 13 as shown in FIG. 6C, it may be formed on the silicon substrate 11 side as shown in FIG.
【００２１】[0021]
【発明の効果】以上の説明から明らかなように、この発
明によればＳＯＩ層の膜層を基板（ウェハ）面内で均一
にする効果がある。また、貼り合わせによってＳＯＩを
形成するため結晶欠陥の少ない半導体基板を形成するこ
とが可能になる。As is apparent from the above description, the present invention has the effect of making the film layer of the SOI layer uniform in the plane of the substrate (wafer). Further, since SOI is formed by bonding, a semiconductor substrate with few crystal defects can be formed.
【図１】（Ａ）〜（Ｃ）はこの発明の実施例を示す工程
断面図。1A to 1C are process sectional views showing an embodiment of the present invention.
【図２】（Ａ）〜（Ｃ）はこの発明の実施例を示す工程
断面図。2A to 2C are process sectional views showing an embodiment of the present invention.
【図３】（Ａ）〜（Ｃ）はこの発明の実施例を示す工程
断面図。3A to 3C are process sectional views showing an embodiment of the present invention.
【図４】（Ａ）及び（Ｂ）はこの発明の実施例を示す工
程断面図。4A and 4B are process sectional views showing an embodiment of the present invention.
【図５】（Ａ）〜（Ｃ）はこの発明の実施例を示す工程
断面図。5A to 5C are process sectional views showing an embodiment of the present invention.
【図６】この発明の他の実施例を示す要部断面図。FIG. 6 is a cross-sectional view of essential parts showing another embodiment of the present invention.
【図７】従来例の要部断面図。FIG. 7 is a sectional view of a main part of a conventional example.
【図８】従来例の要部断面図。FIG. 8 is a sectional view of a main part of a conventional example.
【図９】従来例の要部断面図。FIG. 9 is a sectional view of a main part of a conventional example.
１１…シリコン基板（単結晶半導体基板） １１Ａ…トレンチ（凹部） １１Ｂ…ＳＯＩ層 １２…ＳｉＯ2膜（充填物） １３…第１支持基板 １４…シリコン酸化膜（絶縁膜） １５…ポリシリコン膜（エッチングストッパ層） １６Ａ，１６Ｂ…段差 １７…シリコン酸化膜 １８…ポリシリコン膜（材料膜） １９…第２支持基板11 ... Silicon substrate (single crystal semiconductor substrate) 11A ... Trench (recess) 11B ... SOI layer 12 ... SiO 2 film (filler) 13 ... First support substrate 14 ... Silicon oxide film (insulating film) 15 ... Polysilicon film ( Etching stopper layer) 16A, 16B ... Step 17 ... Silicon oxide film 18 ... Polysilicon film (material film) 19 ... Second support substrate
Claims (5)
し、該凹部に絶縁物でなる充填物を埋め込んだ後、表面
を絶縁膜で覆った支持基板を該単結晶半導体基板の表面
に貼り合わせ、当該単結晶半導体基板の裏面を前記充填
物に達するまで研磨して単結晶島領域を形成することを
特徴とする半導体基板の製造方法。1. A concave portion is formed on the surface of a single crystal semiconductor substrate, a filling material made of an insulating material is embedded in the concave portion, and a supporting substrate having a surface covered with an insulating film is attached to the surface of the single crystal semiconductor substrate. In addition, a method for manufacturing a semiconductor substrate, characterized in that the back surface of the single crystal semiconductor substrate is polished until it reaches the filling material to form a single crystal island region.
し、該凹部に絶縁物でなる充填物を埋め込む工程と、 表面を絶縁膜で覆った第１支持基板を該単結晶半導体基
板の表面に貼り合わせる工程と、 前記単結晶半導体基板の裏面を前記充填物に達するまで
研磨する工程と、 前記単結晶半導体基板の研磨面にデバイス形成領域を画
成するための段差を形成し、該研磨面及び段差面に沿っ
て表面に研磨ストッパとしての酸化膜を形成する工程
と、 前記段差及び前記研磨面上に材料膜を付着させ、該材料
膜表面を平坦化する工程と、 前記材料膜表面に第２支持基板を貼り合わせる工程と、 前記第１支持基板側を前記絶縁膜に達するまで研磨する
工程と、 前記絶縁膜及び前記充填物をエッチングして除去する工
程と、 前記エッチングにより露出した単結晶半導体基板を前記
酸化膜に達するまで研磨して単結晶島領域を形成する工
程と、を備えたことを特徴とする半導体基板の製造方
法。2. A step of forming a concave portion on the surface of a single crystal semiconductor substrate and filling a filling material made of an insulating material in the concave portion; and a step of forming a first supporting substrate whose surface is covered with an insulating film on the surface of the single crystal semiconductor substrate. And a step of polishing the back surface of the single crystal semiconductor substrate until reaching the filling, and forming a step for defining a device formation region on the polishing surface of the single crystal semiconductor substrate, Forming an oxide film as a polishing stopper on the surface along the surface and the step surface; depositing a material film on the step and the polishing surface to flatten the material film surface; A step of adhering a second support substrate to the substrate, a step of polishing the first support substrate side until the insulating film is reached, a step of etching and removing the insulating film and the filling, and a step of exposing by the etching. The method of manufacturing a semiconductor substrate, wherein a crystalline semiconductor substrate and a step of forming a single crystal island regions is polished until the oxide film.
ンでなる請求項２記載の半導体基板の製造方法。3. The method for manufacturing a semiconductor substrate according to claim 2, wherein the filling material and the insulating film are made of silicon oxide.
リコンでなる請求項２記載の半導体基板の製造方法。4. The method of manufacturing a semiconductor substrate according to claim 2, wherein the material film is made of silicon oxide doped with impurities.
物に達するまで研磨する工程の後に、該充填物の一部を
表面よりエッチング除去しこの除去した部分に前記充填
物とエッチング選択比をとれる材料でなるエッチングス
トッパ層を埋め込む工程を備え、前記酸化膜を形成した
際に、前記充填物と該酸化膜との間にストッパ層が介在
するようにした請求項２記載の半導体基板の製造方法。5. After the step of polishing the back surface of the single crystal semiconductor substrate to reach the filling material, a part of the filling material is removed by etching from the front surface, and an etching selection ratio between the filling material and the filling material is given to the removed portion. 3. The manufacturing of a semiconductor substrate according to claim 2, further comprising a step of burying an etching stopper layer made of a removable material, wherein the stopper layer is interposed between the filling material and the oxide film when the oxide film is formed. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2072994A JPH07231036A (en) | 1994-02-18 | 1994-02-18 | Manufacture of semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2072994A JPH07231036A (en) | 1994-02-18 | 1994-02-18 | Manufacture of semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07231036A true JPH07231036A (en) | 1995-08-29 |
Family
ID=12035280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2072994A Pending JPH07231036A (en) | 1994-02-18 | 1994-02-18 | Manufacture of semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07231036A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100388287B1 (en) * | 1999-06-07 | 2003-06-19 | 앰코 테크놀로지 코리아 주식회사 | back grinding method of wafer and semiconductor package thereof and its manufacturing method |
| JP2004040093A (en) * | 2002-07-05 | 2004-02-05 | Samsung Electronics Co Ltd | Soi wafer and method of manufacturing the same |
| KR100474075B1 (en) * | 1997-12-30 | 2005-05-24 | 주식회사 하이닉스반도체 | Bonded semiconductor substrate manufacturing method |
| JP2006332478A (en) * | 2005-05-30 | 2006-12-07 | Fuji Electric Device Technology Co Ltd | Semiconductor device and manufacturing method thereof |
| KR100668808B1 (en) * | 2000-06-01 | 2007-01-16 | 주식회사 하이닉스반도체 | Method for fabricating soi wafer |
| CN103247568A (en) * | 2013-05-14 | 2013-08-14 | 上海新傲科技股份有限公司 | Manufacturing method for substrate with graphical insulating buried layer |
| CN107457689A (en) * | 2017-10-03 | 2017-12-12 | 德清晶生光电科技有限公司 | Erratic star wheel for one side polishing |
-
1994
- 1994-02-18 JP JP2072994A patent/JPH07231036A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100474075B1 (en) * | 1997-12-30 | 2005-05-24 | 주식회사 하이닉스반도체 | Bonded semiconductor substrate manufacturing method |
| KR100388287B1 (en) * | 1999-06-07 | 2003-06-19 | 앰코 테크놀로지 코리아 주식회사 | back grinding method of wafer and semiconductor package thereof and its manufacturing method |
| KR100668808B1 (en) * | 2000-06-01 | 2007-01-16 | 주식회사 하이닉스반도체 | Method for fabricating soi wafer |
| JP2004040093A (en) * | 2002-07-05 | 2004-02-05 | Samsung Electronics Co Ltd | Soi wafer and method of manufacturing the same |
| US6884693B2 (en) | 2002-07-05 | 2005-04-26 | Samsung Electronics Co., Ltd. | Silicon-on-insulator wafer and method of manufacturing the same |
| KR100498446B1 (en) * | 2002-07-05 | 2005-07-01 | 삼성전자주식회사 | Silicon-0n-Insulator wafer and method for manufacturing the same |
| JP2006332478A (en) * | 2005-05-30 | 2006-12-07 | Fuji Electric Device Technology Co Ltd | Semiconductor device and manufacturing method thereof |
| CN103247568A (en) * | 2013-05-14 | 2013-08-14 | 上海新傲科技股份有限公司 | Manufacturing method for substrate with graphical insulating buried layer |
| CN107457689A (en) * | 2017-10-03 | 2017-12-12 | 德清晶生光电科技有限公司 | Erratic star wheel for one side polishing |
| CN107457689B (en) * | 2017-10-03 | 2024-04-05 | 德清晶生光电科技有限公司 | A star wheel that moves for single face is polished |
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