JPH0723035A - Frame phase matching circuit - Google Patents

Abstract

PURPOSE:To simplify the constitution of a write side at the time of allowing a frame phase to match an in-device timing with respect to data having frame information. CONSTITUTION:When read-out data 206 and a unique word 207 coincidide with each other, a unique word detecting signal 208 is sent out. In the case this detecting signal is not received, a shift control part 105 outputs a shift read-out control signal 211. When the shift read-out control signal is received, a head read-out address counter 106 executes one-count-up and sends out a head read- out address 212. Selectors 108 and 109 select the head read-out address and the shift read-out control signal by the shift read-out control signal and give them as a read-out address 214 and a read-out control signal 213 to a dual port memory 101. When the unique word is not detected, since the head read-out address is subjected to one-count-up, the constitution of a write side is simplified and data can be read out in an arbitrary frame phase.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame phase adjusting circuit for receiving a signal having a fixed length and periodic frame information and converting the phase thereof into a designated read phase.

[0002]

2. Description of the Related Art As this type of read phase control, for example, a phase locked loop circuit described in Japanese Patent Laid-Open No. 32-32644 is known.

When a transmission signal having a fixed length and periodic frame information is received from a transmission line and a required signal is separated, both the frequency and the phase of the transmission line are asynchronous with the timing of the receiving device. Therefore, it is necessary to perform timing conversion so that the frame head matches the internal timing of the receiving device.

Generally, when the frame heads are aligned, the frame heads are aligned by detecting the frame information and determining the frame heads.

A conventional frame alignment circuit will now be outlined with reference to FIG.

The write data 201 is the comparator 10
3 is compared with the unique word 207, and the comparator 103 outputs the unique word detection signal 208 when the unique word is detected. The frame synchronization protection unit 104 sends out the head write signal 216 when receiving the unique word detection signal 208 and the write control signal. Then, the head write signal 216 is given to the delay memory 111, the selector 113, and the phase monitoring circuit 114.

The head write signal 216 is delayed by a predetermined amount in the delay memory 111 and is output to the selector 113 as the head write signal 218. The selector 113 selects one of the head write signals 216 and 218 and outputs the head write signal 220 as described later. The head write signal 220 and the write control signal 202 are given to the write address counter 115, and the write address counter 115 generates the write address 221 and gives the write address 221 to the dual port memory 101.

The write data 201 is delayed by a predetermined amount in the delay memory 111, and is output as write data 217 from the delay memory 111. The write data 201 and 217 are given to the selector 112, and the selector 112 selects one of the write data 201 and 217 and outputs it as the write data 219 as described later. The write data 219 is stored in the dual port memory 10 based on the write address 221 and the write control signal 202.
Written to 1.

Here, since the write address 221 is synchronized with the frame phase of the write data 219, the in-phase data in the frame is always written in the same memory area.

When reading the data written in the dual port memory 101, the read address 203 is given to the dual port memory 101 together with the read control signal. As a result, the write data is read as the read data 206 from the dual port memory 101. In reading the write data, the write data can be read in an arbitrary frame phase according to the value of the read address.

By the way, the above read address 203 is also given to the head address detecting section 116, and the head address detecting section 116 receives the head read signal 22 based on the read address.
2 is output. The head write signal 2 is input to the phase monitoring circuit 114.
16 and the head read signal 222 are supplied, and when the phases of the head write signal 216 and the head read signal 222 come close to a predetermined amount, the phase monitoring circuit 114 outputs the switching signal 223 to the selectors 112 and 113. Supply. In the selectors 112 and 113, in response to the switching signal 223, the write data 217 and the head write signal 2 respectively.
Select 18.

[0012]

As described above, in the conventional frame phasing circuit, it is necessary to detect the frame phase of the write data 201 in advance and write the write data in a predetermined address of the memory. For this reason, it is necessary to provide a comparator and a frame synchronization circuit on the writing side. By the way, on the writing side, it is desirable to perform a simple process because it operates at the transmission timing of the transmission path, and there is a problem that the circuit configuration becomes complicated in the conventional frame phasing circuit.

An object of the present invention is to provide a frame phasing circuit whose circuit on the writing side is simple.

[0014]

According to the present invention, write data is written in a memory means according to a write control signal and a write address, and the write data is read according to a read control signal and a read address. A frame phase adjusting circuit for reading the data and adjusting the frame phase of the read data, and comparing means for comparing the read data with a preset unique word and transmitting a detection signal when they match. , A control means for transmitting a shift control signal when the detection signal is not received, a counter means for counting up by 1 when the shift control signal is received and outputting a leading read address, and a counter means when the shift control signal is received. A selector hand that sends the leading read address as a read address and the shift control signal as the read control signal. Frame phase matching circuit is obtained which is characterized by having and.

[0015]

EXAMPLES The present invention will be described below with reference to examples.

Referring to FIG. 1, write counter 102 receives write control signal 202 and outputs write address 203 in response to write control signal 202. The write address counter 102 is a counter having a write data frame length cycle, and the phase of the write address is independent of the phase of the write data 201. The write data 201 is the write control signal 2
02 and the write address 203 are written in the dual port memory 101. Therefore, here, the write data is written based on the write address 203 regardless of the frame phase of the write data and the memory address.

On the other hand, the adder (adder) 107 adds the read address 205 and the head read address output from the head read address counter 106. The addition output is given to the selector 108. The selector 108 selects one of the leading read address 212 and the above-mentioned addition output as described later and supplies it to the dual port memory 101 as the read address 214.

A read control signal 204 and a shift read control signal 211, which will be described later, are applied to the selector 109, and the selector 109 selects either the read control signal 204 or the shift read control signal 211 to read the read control signal 213.
To the dual port memory 101. And
The read control signal 213 is output from the dual port memory 101.
The read data 206 is read according to the read address 214.

This read data 206 is used as the comparator 10
3 is compared with a preset unique word 207. When the unique word in the read data matches the unique word 207, the comparator 103
Sends a unique word detection signal 208. The unique word detection signal 2 is sent to the frame synchronization protection unit 104.
A read address 205 is given together with 08. When the read address 205 indicates the beginning of the frame (= 0) and the unique word detection signal 208 has not been received, the frame synchronization protection unit 104 outputs the shift start signal 209. Then, the shift start signal 209 is given to the shift control unit 105. The shift control unit 105 further includes a unique word detection signal 208 and a read control signal 20.
4, and the shift control clock 210 is provided. Then, the shift control unit 105 sends out the shift read control signal 211.

FIG. 2 shows a time chart for normal reading. Referring to FIGS. 1 and 2, write data 201 includes a unique word (indicated by number 0) and a plurality of data (indicated by numbers 1 to 63) consecutive to the unique word in one frame. This write data 201 is written in the write address 2 by the write control signal 202 as described above.
It is written in the position (area) indicated by 03. In this example, the unique word is written at the write address “6”.

On the other hand, in the illustrated example, since the head read address is "6", the head read address indicates the head of the read data, that is, the unique word.
When the shift read control signal 211 is not received, the selectors 108 and 109 respectively select the output of the adder 107 and the read control signal 204 to select the memory read address 214.
And a read control signal to the dual port memory 101. Here, since the read address 205 is "0", the unique word is read from the dual port memory 101 as read data.

Since the read data is a unique word, the comparator 103 outputs a unique word detection signal. As a result, the shift control unit 105 enters the shift stop state.

Next, FIG. 3 shows a time chart for abnormal reading. Referring to FIGS. 1 and 3, if the leading read address 212 is abnormal (“3” in the illustrated example), the output of the adder 107 is “6” even if the read address 205 is “0”. As a result, the read data 206 from the dual port memory 101 does not become a unique word.

Since the read data 206 is not a unique word, the comparator 103 does not send a unique word detection signal. As a result, the frame synchronization protection circuit 104 sends the shift start signal 209, and the shift control unit 105 releases the shift stop. Shift control unit 10
In 5, the shift read control signal is sent in response to the shift start signal 209. In response to the shift read control signal 211, the selectors 108 and 109 select the head read address 212 and the shift read control signal 211, respectively, and output them as the read address 214 and the read control signal 213.
At this time, the head read address counter 106 increments the head read address 211 by 1 in response to the shift read control signal 211. That is, in the illustrated example, the head read address counter 106 sets the head read address 212 to "4".

As described above, the head read address 21
Dual port memory 10 even if 2 is incremented by 1
The read data 206 from 1 does not become a unique word. Therefore, the shift control unit 105 outputs the shift read control signal 211. Then, in the head read address counter 106, the shift read control signal 211
In response to, the leading read address 211 is incremented by 1 again (that is, the shift read control signal 211 is "5").
Will be).

In this way, the dual port memory 1
The leading read address 212 is incremented by 1 until the read data 206 from 01 becomes a unique word. When the leading read address 212 reaches a predetermined value (“6” in the illustrated example), the read data 206 from the dual port memory 101 becomes a unique word, and the comparator 103 sends a unique word detection signal. As a result, the frame synchronization protection unit 104 stops sending the shift start signal 209,
The shift control unit 105 is in the shift stop state (that is,
(Transmission of the shift read control signal 211 is stopped). In this way, the leading read address 212 is set to the read data 206.
Indicates the beginning of the frame, and the reading returns to the normal state.

[0027]

As described above, according to the present invention, no processing is performed when writing data to the memory, that is, when writing data, the data is written to an address that is not related to the frame phase of the write data. Since the data is read at an arbitrary frame phase at the time of reading, there is an effect that the circuit configuration on the writing side can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a frame phasing circuit according to the present invention.

FIG. 2 is a time chart for explaining the operation of the frame phase matching circuit shown in FIG. 1 during normal reading.

FIG. 3 is a time chart for explaining the operation of the frame phase matching circuit shown in FIG. 1 at the time of abnormal reading.

FIG. 4 is a block diagram showing a conventional frame phase matching circuit.

[Explanation of symbols]

 101 Dual Port Memory 102 Write Address Counter 103 Comparator 104 Frame Sync Protection Unit 105 Shift Control Unit 106 Start Read Address Counter 107 Adder (Adder) 108, 109 Selector

Claims (3)

[Claims] 1. The write data is written in a memory means according to a write control signal and a write address, the write data is read as read data according to a read control signal and a read address, and a frame phase of the read data is set. A frame phasing circuit adapted to adjust the read data and comparing the read data with a preset unique word and sending a detection signal when they match, and a shift control when the detection signal is not received. Control means for transmitting a signal,
When receiving the shift control signal, the counter means counts up by one and outputs the leading read address, and when receiving the shift control signal, the leading read address is sent as the reading address and the shift is performed as the reading control signal. A frame phase adjusting circuit comprising: selector means for transmitting a control signal. 2. The frame phasing circuit according to claim 1, further comprising adding means for adding an input read address and the leading read address to generate an added address, and the selector means is the A frame phasing circuit, characterized in that when the shift control signal is not received, the added address is sent as the read address and a read control signal inputted in advance is sent as the read control signal. 3. The frame synchronization circuit according to claim 2, wherein the control means sends a shift start signal when the detection signal is not received when the pre-input read signal is received. And a shift control unit for transmitting the shift control signal when receiving the shift start signal.