JP2000022674A - Protective system for clock transfer circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the protective system of a clock transfer circuit capable of outputting main signals without errors even when a write pulse or a read pulse fluctuates. SOLUTION: When the phases of a pulse for which the width of the write pulse is widened for a fixed amount and the read pulse are compared in a phase comparison part 6 and abnormality is detected, a PLO part 2 is reset and the read pulse 2 to be supplied to a buffer memory 4 is switched to a relief pulse outputted from a delay insertion part 5. Thus, the overlap with each other of the pulses used in the buffer memory is evaded and main signal data are outputted without the errors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a protection method for a clock transfer circuit, and more particularly to a protection method for a clock transfer method between packages of a digital transmission apparatus.

[0002]

2. Description of the Related Art In a digital transmission apparatus, various internal processes are performed after synchronizing the main signal data received from another apparatus or another package with an internal clock. For this reason, the clock transfer circuit is an important element for maintaining the quality of the transmission path, and the protection method of the circuit is also very important.

A conventional clock transfer circuit generates a write pulse from a write counter operated by an input clock, and generates a read pulse from a read counter operated by an output clock of a VCO to change clocks. . When the write pulse and the read pulse overlap with each other due to some trouble in this circuit, the read counter is forcibly reset and the read pulse is generated again. Japanese Patent Application Laid-Open No. 63-3630 discloses a conventional protection method for this type of clock transfer circuit.
There are those described in JP-A-16531 and JP-A-63-299421.

FIG. 3 is a block diagram showing a protection method of a conventional clock transfer circuit described in Japanese Patent Application Laid-Open No. 63-316531. Referring to FIG. 3, the buffer memory 31 switches clocks using an external input clock as a read-side clock and an internal clock generated by the PLO 32 as a write-side clock.

In the protection method of the clock transfer circuit, a clock read from the buffer memory is switched to an input clock or an output clock of a free-running PLL triggered by detection of an abnormal stuff ratio of main signal data or disconnection of an input clock. Do. That is, data is saved by switching to a clock other than the output clock of the phase-locked oscillator used in the normal operation.

FIG. 4 is a block diagram showing a protection method of a conventional clock transfer circuit described in Japanese Patent Application Laid-Open No. 63-299421. Referring to FIG. 4, in this circuit,
From the clock generation circuit 42, the write clock, PLO4
7, a read clock is generated, a clock change is performed, and a PLO abnormality is monitored by comparing a write clock to a buffer memory with a read clock.

[0007]

In the conventional protection method of the clock transfer circuit, when the input clock fluctuates, V
Since it takes time for the CO to follow the fluctuating clock, the read counter is reset many times, and a read pulse may be generated each time, and it is difficult to guarantee the transmission signal during that time. Will be.

The technique disclosed in Japanese Patent Application Laid-Open No. 63-316531 is a read clock clock control method when a main signal or higher-order group input clock error occurs. Therefore, the occurrence and detection of the main signal error is a condition of the control, so that the main signal data from the occurrence of the error until the control operates is uncertain.

The technique disclosed in Japanese Patent Application Laid-Open No. 63-299421 is aimed at detecting an abnormality in a PLO which is the basis of a read pulse from a buffer memory, and does not disclose any technique for relieving main signal data. Absent.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a protection method of a clock transfer circuit that can output a main signal without causing an error even if a write pulse or a read pulse fluctuates. With the goal.

[0011]

According to a first aspect of the present invention, there is provided a method for protecting a clock transfer circuit, wherein a phase of a write pulse and / or a read pulse is increased by a predetermined amount. When an abnormality is detected by comparison, the read pulse to the buffer memory is switched to a pulse obtained by delaying the write pulse by a fixed amount.

According to a second aspect of the present invention, there is provided a method for protecting a clock re-routing circuit, comprising: a write counter for generating a write pulse from an input clock; and a phase synchronization for outputting a clock having a phase and frequency synchronization with the input clock. In a clock transfer circuit including an oscillator, a read counter that generates a read pulse from an output clock of a phase-locked oscillator, and a buffer memory that writes and reads data based on a write pulse and a read pulse, a fixed number of write pulses are generated. A delay insertion unit that outputs a delayed rescue pulse, a selector that switches between the rescue pulse and the read pulse, and a pulse comparison of at least one of the write pulse and the read pulse by expanding the pulse width by a certain amount and performing phase comparison. Outputs an abnormal signal when detected A phase comparator for resetting the phase-locked oscillator when an abnormal signal is output from the phase comparator, and using a read pulse to the buffer memory as a relief pulse while the abnormal signal is output. And

According to a third aspect of the present invention, there is provided a protection method for a clock re-routing circuit, wherein the phase comparator outputs an abnormal signal until the phase-locked oscillator is stabilized.

According to the first aspect of the present invention, the read pulse is switched based on the result of the phase comparison performed in a state where the pulse width of at least one of the write pulse and the read pulse is expanded by a certain amount. Pulses used in the buffer memory can be prevented from overlapping each other.

According to the second and third aspects of the present invention, the read pulse is switched based on the result of the phase comparison performed while the pulse width of at least one of the write pulse and the read pulse is expanded by a certain amount. And resetting of the phase-locked oscillator prevents the pulses used in the buffer memory from overlapping each other, and further prevents the phase-locked oscillator from being reset many times.

[0016]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention. The write counter 1 generates a write pulse from an input clock, and compares the internal reference signal with the input clock to determine the phase of the input clock. A phase-locked oscillator (PLO) 2 that outputs a signal with frequency synchronization secured and is reset by an error signal from the phase comparator 6;
2, a read counter 3 for generating a read pulse from the output of the buffer 2, a buffer memory 4 for writing main signal data according to the write pulse, and outputting the main signal data according to the read pulse 2, and a relief pulse by delaying the write pulse by a certain amount. A delay insertion unit 5, a pulse comparison unit 6 that expands the pulse width of the write pulse, compares the phase with the read pulse 1, and outputs an error signal when both pulses overlap, and the read pulse 1 and the rescue pulse are input. And a selector 7 that outputs a rescue pulse when an input of an error signal is detected and outputs a read pulse 1 when detection of cancellation of the error signal is detected.

FIG. 2 is a flowchart showing the operation of the embodiment of the present invention, and shows the operation at the time of the normal operation and at the time of occurrence of the comparison result error.

Next, the operation of one embodiment of the present invention will be described with reference to FIGS. When the main signal data and an input clock synchronized with the main signal data are input from the outside, the input clock is input to the write counter 1 to generate a write pulse. Then, the main signal data is written into the buffer memory 4 in synchronization with the write pulse.

The input clock controls the PLO unit 2 to generate a clock, and the read counter 3 generates a read pulse 1 having a constant delay from a write pulse based on the clock. This delay amount is a delay for providing protection in consideration of jitter and the like.
And

The delay insertion unit 5 generates a relief pulse having a delay amount n from the write pulse, and
Output to The selector 7 selects the read pulse 1 as the read pulse 2 during normal operation, and reads main signal data from the buffer memory 4. This output signal becomes the main signal data output.

The phase comparator 6 generates a phase comparison internal write pulse in which the pulse width of the write pulse is increased by a certain amount in the front-rear direction, as shown in FIG. As a result, when the overlap between the two pulses is detected, the phase comparator 6 generates a comparison error signal.
In this embodiment, the write pulse width is widened, but the read pulse or both pulses may be widened to compare the pulses. At the same time, the PLO unit 2 is reset and re-controlled by the error signal, and at the same time, the selector 7 is switched to switch the read pulse 2 from the read pulse 1 to the relief pulse. Since the rescue pulse always has the delay amount n with respect to the write pulse, the main signal data can be reliably read. Since it takes several msec or more for the re-control of the PLO unit 2 to stabilize, the comparison result error signal is output for a sufficiently long time, for example, output for 1 second after occurrence.
When the error signal is released, the selector 7 switches the read pulse 2 from the rescue pulse to the pulse 1 to be read, and starts switching clocks again.

[0022]

According to the first aspect of the present invention, the pulses used in the buffer memory can be prevented from overlapping each other, and the main signal data can be output without error.

According to the second and third aspects of the present invention, it is possible to reset the phase-locked oscillator while avoiding the overlap of the pulses used in the buffer memory, and to reset the main signal even during re-control of the phase-locked oscillator. Data can be output without error.

[0024]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a protection method of a clock re-shunt circuit according to an embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of a clock re-schedule protection method according to an embodiment of the present invention.

FIG. 3 is a block diagram showing an example of a conventional clock transfer protection method.

FIG. 4 is a block diagram showing another example of the conventional clock transfer protection method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Write counter 2 PLO part 3 Read counter 4 Buffer memory 5 Delay insertion part 6 Phase comparison part 7 Selector

Claims (3)

[Claims] In a protection method of a clock transfer circuit, when an abnormality is detected by performing phase comparison with a pulse width of at least one of a write pulse and a read pulse being widened by a fixed amount, reading to a buffer memory is performed. A protection method for a clock transfer circuit, wherein a pulse is switched to a pulse obtained by delaying a write pulse by a fixed amount. 2. A write counter that generates a write pulse from an input clock, a phase-locked oscillator that outputs a clock that ensures phase and frequency synchronization with the input clock, and a read pulse from an output clock of the phase-locked oscillator In a clock transfer circuit including a read counter and a buffer memory for writing and reading data based on the write pulse and the read pulse, a delay insertion unit that outputs a relief pulse obtained by delaying a write pulse by a certain amount; A selector for switching between a rescue pulse and the read pulse; and a pulse comparison of at least one of the write pulse and the read pulse for a certain amount of time, and a phase comparison. A phase comparison unit, A clock resetting unit that resets the phase-locked oscillator when an abnormal signal is output from the phase comparison unit, and sets a readout pulse to the buffer memory as the rescue pulse while the abnormal signal is output. Circuit protection method. 3. The protection method according to claim 2, wherein the phase comparison unit outputs the abnormal signal until the phase locked oscillator is stabilized.