JPH0722931A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To adjust the duty ratio of an output signal in an output buffer circuit. CONSTITUTION:When a low level is imparted to an input terminal 11, an N- channel transistor 21 is turned off and a transfer gate 26 is turned on. As a result, voltage provided with the waveform according to the time constant stipulated by a resistor 31a and a capacitor 31b is imparted to a Schmitt trigger buffer 25 and when this voltage becomes a prescribed level, a high level appears in an output terminal 12. In the same way, when the high level is imparted to the input terminal 11, an N-channel transistor 22 is turned off and a transfer gate 30 is turned on. Voltage provided with the waveform according to the time constant stipulated by a resistor 32a and a capacitor 32b is imparted to a Schmitt trigger buffer 28, and when this voltage becomes a prescribed level, the low level appears in the output terminal 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit.

[0002]

2. Description of the Related Art Generally, an inverter circuit shown in FIG. 2 is used as an output buffer circuit. The illustrated output buffer circuit includes an input terminal 11 and an output terminal 12, and a P-channel transistor 13 and an N-channel transistor 14. The input terminal 11 is connected to the P-channel transistor 13 and N-channel in this output buffer circuit.
It is connected to the gate of the channel transistor 14.
The source of the P-channel transistor 13 is connected to the power supply, and the drain of the N-channel transistor 14 is grounded. The drain of the P-channel transistor 13 and the source of the N-channel transistor 14 are connected to each other and to the output terminal 12.

When a low level is applied to the input terminal 11, the P-channel transistor 13 is turned on, and as a result, a high level appears at the output terminal 12.
On the other hand, when a high level is applied to the input terminal 11,
The N-channel transistor 14 is turned on, and as a result, a low level appears at the output terminal 12.

By the way, in the output buffer circuit shown in FIG. 2, when switching is performed at high speed, unnecessary radiation radio waves are transmitted into the air through the wiring connected to the output terminals, which causes noise.

In order to prevent such a problem, for example, an output buffer circuit disclosed in Japanese Patent Laid-Open No. 60-62725 is known.

Referring to FIG. 3, a resistor 15 and a capacitor 16 are newly provided in the illustrated output buffer circuit, and the resistor 15 is connected to the input terminal 11 and also has a P-channel transistor 13 and an N-channel transistor. It is connected to 14 gates. Further, the capacitor 16 is connected to the gates of the P-channel transistor 13 and the N-channel transistor 14, and also connected to the drain of the P-channel transistor 13 and the source of the N-channel transistor 14. In the illustrated output buffer circuit, the rise time and the fall time of the output are limited by the time constants defined by the resistor 15 and the condenser 16, thereby suppressing unnecessary radiated radio waves.

[0007]

As is apparent from the above point, in the output buffer circuit shown in FIG. 2, the rising delay time of the output signal is determined by the operating speed of the P-channel transistor, while the falling delay time is decreased. Is N
It is determined by the operating speed of the channel transistor.

By the way, the P-channel transistor and the N-channel
Since the operating time of the channel transistor is determined by the operating speeds of holes and electrons, the P-channel transistor and the N-channel transistor have different parameters that define the operating time. As a result, in the output buffer circuit shown in FIG. 2, the rising delay time and the falling delay time may be different and the duty ratio of the output signal may fluctuate.

As described above, in the output buffer circuit shown in FIG. 3, the rising delay time and the falling delay time can be changed by the time constants defined by the resistors and capacitors, but the rising delay time and the falling delay time are changed. The time cannot be changed independently.

In consideration of the above points, when the duty ratio of the output signal in both the output buffer circuits shown in FIGS. 2 and 3 is greatly disturbed due to process factors and external factors, the duty ratio cannot be adjusted. You have to redesign.

In addition, in the conventional output buffer circuit, it is difficult to adjust the duty ratio as necessary. As a result, for example, when the integrated circuit is operated at a high speed, if the duty ratio is largely destroyed, the next stage There is a problem that the circuit malfunctions.

An object of the present invention is to provide an output buffer circuit capable of adjusting the duty ratio of an output signal.

[0013]

According to the present invention, an input terminal and an output terminal, first and second switch means which are turned on and off according to an input signal level inputted from the input terminal, and the first and second switch means are provided. And an output buffer circuit configured to send an output signal to the output terminal according to ON / OFF of the second switch means, a first voltage generating means having a variable time constant for generating a first voltage signal, and A second voltage generating means having a variable time constant for generating a second voltage signal and the first voltage signal when the first switch means is turned on, and the first voltage signal exceeds a predetermined level. At this time, a first pulse signal supply means for giving a first pulse signal to the output terminal as the output signal, and a second voltage signal for receiving the second voltage signal when the second switch means is turned on. Exceeded a certain level Output buffer circuit and having a second pulse signal supply means for providing a second pulse signal as the output signal to the output terminal is obtained.

[0014]

EXAMPLES The present invention will be described below with reference to examples.

Referring to FIG. 1, the illustrated output buffer circuit includes first and second N-channel transistors (hereinafter simply referred to as first and second transistors) 21 and 22, respectively. The gate of 21 is connected to the input terminal 11, and the gate of the second transistor 22 is connected to the input terminal 11 via the inverter 23.

The source of the first transistor 21 is connected to the first power supply terminal 24 and is also connected to the input terminal of the first transfer gate 26 via the first Schmitt trigger buffer 25, and the first transistor 21 is connected. The drain of is grounded. Similarly, the source of the second transistor 22 is connected to the second power supply terminal 27 and is also connected to the input terminal of the second transfer gate 30 via the second Schmitt trigger buffer 28 and the inverter 29. The drain of the transistor 22 is grounded.

First and second transfer gates 26
The control ends of 30 and 30 are connected to the input terminal 11 and also to the inverter 23. The output terminals of the first and second transfer gates 26 and 30 are connected to the output terminal 12.

A power supply is connected to the first power supply terminal 24 via a first power supply connector 31, and a power supply is connected to the second power supply angel 27 via a second power supply connector 32. .
As shown, the first and second power supply connectors 31 and 32 include resistors 31a and 32a and capacitors 31b and 32b, respectively. In the first power supply connector 31, the connection point between the resistor 31a and the capacitor 31b is the first
Is connected to the power supply terminal 24, the resistor 31a is connected to the power supply, and the capacitor 31b is grounded.
Similarly, in the second power supply connector 32, the resistor 32a
Is connected to the second power supply terminal 27, the resistor 32a is connected to the power supply, and the capacitor 32b is grounded.

When a low level ("0") signal is input from the input terminal 11, a high level ("1") appears at the output of the inverter 23, so that the first transfer gate 26 is turned on (ON). Then, the second transfer gate 30 is turned off. Also,
The first transistor 21 is turned off and the second transistor 22 is turned on. As a result, the resistor 31a and the capacitor 31 are included in the first Schmitt trigger buffer 25.
A voltage having a waveform corresponding to the time constant determined by b (hereinafter, this voltage will be referred to as a first voltage) is applied. When the first voltage exceeds a predetermined level, the output of the first Schmitt trigger buffer 25 becomes high level. As described above, the first transfer gate 26
Is on, a high level appears at the output terminal 12.

When a high level signal is input from the input terminal 11, the transfer gate 26 turns off and the transfer gate 30 turns on. Further, the first transistor 21 is turned on and the second transistor 22 is turned off. As a result, the second Schmitt trigger buffer 28 has a voltage having a waveform according to the time constant determined by the resistor 32a and the capacitor 32b.
Will be added). When the second voltage exceeds a predetermined level, the output of the second Schmitt trigger buffer 28 becomes high level, and the second transfer gate 30 is given low level. Therefore, a low level appears at the output terminal 12.

As described above, according to the present invention, the time constant is changed by adjusting the resistor 31a and the capacitor 31b, whereby the first Schmitt trigger buffer 2 is changed.
The output timing from 5 is changed. That is, the rising edge and the falling edge in the output of the first Schmitt trigger buffer 25 are adjusted. Similarly, the time constant is changed by adjusting the resistor 32a and the capacitor 32b, and thereby the output timing from the second Schmitt trigger buffer 28 is changed. That is, the second Schmitt trigger buffer 28
The rising and falling edges of the output of are adjusted. As a result, the rise time and fall time of the output signal from the output terminal 12 can be varied independently.

[0022]

As described above, according to the present invention, not only the time constant can be easily adjusted, but also the rise time and the fall time of the output signal can be adjusted independently. That is, there is an effect that the duty ratio of the output signal can be adjusted as needed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an output buffer circuit according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional output buffer circuit.

FIG. 3 is a block diagram showing another example of a conventional output buffer circuit.

[Explanation of symbols]

 11 Input Terminal 12 Output Terminal 13 P-Channel Transistor 14 N-Channel Transistor 15 Resistor 16 Capacitor 21,22 N-Channel Transistor 23,29 Inverter 24,27 Power Supply Terminal 25,28 Schmitt Trigger Buffer 26,30 Transfer Gate 31,32 Power Supply Connection vessel

Claims (5)

[Claims] 1. An input terminal and an output terminal, and a first ON / OFF switch according to an input signal level input from the input terminal.
And a second switch means, and an output buffer circuit configured to send an output signal to the output terminal in response to ON / OFF of the first and second switch means, a time constant for generating a first voltage signal. A variable first voltage generating means,
Second constant voltage variable voltage generating means for generating a second voltage signal, and the first switch means when the first switch means is turned on.
The first pulse signal supply means for applying the first pulse signal to the output terminal as the output signal when the first voltage signal exceeds a predetermined level, and the second switch means. Second pulse signal supplying means for receiving the second voltage signal when turned on and for applying the second pulse signal to the output terminal as the output signal when the second voltage signal exceeds a predetermined level. An output buffer circuit characterized by the above. 2. The output buffer circuit according to claim 1, wherein said first switch means is turned on when said input signal level is low level, and said second switch means is said input signal level being high level. Is turned on,
The first pulse signal supplying means is a first Schmitt trigger means for outputting a high level signal as the first pulse signal, and is turned on when the input signal level is a low level to output the high level signal to the output terminal. A second transfer means for supplying a low level signal as the second pulse signal, and a second Schmitt trigger means for supplying a low level signal as the second pulse signal, and the second supply means is turned on when the input signal level is high level. And a second transfer gate for supplying the low level signal to the output terminal. 3. The output buffer circuit according to claim 2, wherein first and second N-channel transistors are used as the first and second switch means, respectively, and the first N-channel transistor is The gate of the second N-channel transistor is connected to the input terminal, the gate of the second N-channel transistor is connected to the input terminal via an inverter, and the drains of the first and second N-channel transistors are respectively The source is grounded and the sources are connected to the first and second voltage generating means, and the input ends of the first and second Schmitt trigger means are the first and second N-channel transistors, respectively. An output buffer circuit, which is connected to the source of the. 4. The output buffer circuit according to claim 3, wherein the first and second voltage generating means include a time constant circuit composed of a resistor and a capacitor, respectively. circuit. 5. The output buffer circuit according to claim 1, wherein the input terminal, the output terminal, and the first
And the second switch means, and the first and the second
Of the pulse signal supply means, an output buffer is configured, the output buffer is provided with first and second power supply terminals, and the output buffer is provided with the first and second power supply terminals. And an output buffer circuit connected to the second voltage generating means.