JPH07226723A - Line test circuit - Google Patents

Abstract

PURPOSE:To simplify the control method and test setting processing in the firmware processing by reducing the scale of hardware. CONSTITUTION:A line setting control section 3 generates connection setting information 113 based on time slot information 111 and a HW number 112 from a control section 1 and sends the information 113 to a line connection time switch 5. A format conversion section 4 converts an internal direction HW signal groups 101, 102 from test equipments 2-1-2-m into parallel data 103 and sends the converted data into a line connection time switch 5. The line connection time switch 5 rearranges the parallel data 103 from the format conversion section 4 and outputs the parallel data 104 being the replacement result to a format inverse conversion section 6. The format inverse conversion section 6 converts the parallel data 104 from the line connection time switch 5 into external direction HW signal groups 105, 106 to the test equipments 2-1-2-m and transmits the signal groups 105, 106 to a line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line test circuit, and more particularly to a line test function in data transmission within and between transmission devices for digital communication and data transmission.

[0002]

2. Description of the Related Art A line test circuit for performing an insert test, a monitor test, a loop test, etc. is provided in a transmission device for each line to conduct a line opening test with an opposite device or a cause investigation when a failure occurs. ing.

Further, when the transmission apparatus is required to have a function of simultaneously executing a plurality of tests, a plurality of testers each composed of the above-mentioned line test circuit are used for control.

That is, in a transmission apparatus capable of simultaneously performing m tests when n transmission line [hereinafter referred to as HW (highway)] signals are connected, control is performed as shown in FIG. Part 1, a tester 7-i (i = 1, 2, ..., M) for simultaneously enabling m tests, and HW
HW signal control circuit 8-j (j = 1, 1) provided for each signal
2, ..., N).

Although only the configurations of the tester 7-1 and the HW signal control circuit 8-1 are shown in the figure, the other testers 7 are shown.
-2-7-m and HW signal control circuits 8-2 to 8-n also have the same configuration as the illustrated tester 7-1 and HW signal control circuit 8-1.

The test control pulse generator 71 of the tester 7-i
-I receives the test type information 131, the time slot information 132, the tester number 133, and the HW number 134 from the control unit 1, and insert pulse 141 that specifies the insert time slot and monitor pulse 142 that specifies the monitor time slot. And a loop pulse 143 designating a loop time slot, respectively.

The test data generator 72-i receives the insert pulse 141 during the insert test and generates the insert data 145. The HW selector 73-i is used for the inward HW signal group (HW signals # 1 to #n) 1 during the monitor test.
35, and the monitor HW signal 144 is generated by the HW number 134. The monitor circuit 74-i receives the monitor pulse 142 and the monitor HW signal 144, and outputs the monitor result 146.

The insert tester selector 81-j of the HW signal control circuit 8-j tests the tester 7-i during the insert test.
Insert pulse 141 and insert data 14 from
5, and the tester number 133 and HW from the control unit 1
The insert test pulse 151 and the insert test data 152 are output by the number 134.

The insert circuit 82-j outputs 1 of the inward HW signal group 135 by the insert test pulse 151.
The insert test data 152 is inserted into the inward HW signal 153, which is one HW signal, and the insert HW signal 15 is inserted.
4 is output.

The loop tester selector 83-j receives the loop pulse 143 from the tester 7-i during the loop test, and the tester number 133 and the HW number 134 from the control unit 1 are received.
The loop test pulse 155 is output by and.

The loop circuit 84-j outputs the inward HW signal 1
53 and the external direction HW signal 156 are input, and 1 in the external direction HW signal group 136 is generated by the loop test pulse 155.
The loop HW signal 157 is output as one HW signal.

Next, the operation of the tester 7-1 and the HW signal control circuit 8-1, for example, will be described. Tester 7
In -1, when the test control pulse generation unit 71-1 determines that it is a control request for its own tester by the tester number 133 from the control unit 1, a test pulse 142 that specifies a monitor time slot according to the test type information 131 is sent. The pulse signal is sent to the monitor circuit 74-1 and the insert pulse 141 designating the insert time slot or the loop pulse 143 designating the loop time slot is sent to the HW signal control circuit 8-j.

Insert pulse 1 at the time of insert test
The test data generation unit 72-1 that has received 41 receives insert data 145 according to the frame format of the HW signal.
Is sent.

During the monitor test, the inward HW signal group 13
The HW selector 73-1 receiving 5 selects the HW signal to be tested by the HW number 134, and outputs the monitor HW signal 144. The monitor circuit 74-1 extracts the time slot to be tested from the monitor HW signal 144 by the monitor pulse 142 and outputs the monitor result 146.

On the other hand, in the HW signal control circuit 8-1,
Insert tester selector 81-
1 determines that it is a control request for the HW signal # 1 by the HW number 134, the signal of the tester 7-1 corresponding to the tester number 133 from the insert pulse 141 and the insert data 145 received from the tester 7-i. And insert test pulse 151 and insert test data 152.
And output.

The insert circuit 82-1 uses the insert test pulse 151 to insert the insert test data 152 into the time slot to be tested by the inward HW signal 153.
Is inserted and output as an insert HW signal 154.

During the loop test, the loop tester selector 8
When the 3-1 judges by the HW number 134 that it is a control request to the HW signal # 1, the signal of the tester 7-1 corresponding to the tester number 133 is selected from the loop pulse 143 received from the tester 7-i. Then, the loop test pulse 155 is output.

The loop circuit 84-1 has a loop test pulse 1
The inward HW signal 153 is inserted into the time slot to be tested by the outward HW signal 156 by 55, and the loop HW signal 154 is output as the HW signal # 1 in the outward HW signal group 136.

As described above, the setting and cancellation of the line test in the conventional line test circuit is performed from the control unit 1 to the tester 7-i.
And HW signal control circuit 8-j is realized by sending various control signals.

[0020]

In the above-mentioned conventional line test circuit, an H circuit having an insert circuit and a loop circuit is provided.
Since the W signal control circuit is provided for each HW signal, if the number of HW signals is n, then n such circuits are required.

Further, when it is necessary to execute m tests at the same time, a test control pulse generator and a test data generator are required, and a monitor test requires m HW selectors and monitor circuits, respectively.

When attempting to realize the above-mentioned line test circuit, the hardware scale occupied by the tester and the HW signal control circuit becomes large, and the scale of the HW signal control circuit becomes very large especially in a device accommodating a large number of HW signals. It will be big.

Also, the number of interface signals between the respective functional blocks becomes very large depending on the method of dividing each functional block. Furthermore, not only the control of the test control pulse generation unit in firmware processing,
Since it is necessary to control various selectors in the tester and the HW signal control circuit, the control method becomes very complicated.

Therefore, an object of the present invention is to solve the above problems, provide a line test circuit capable of reducing the hardware scale, and simplifying the control method and the test setting process in the firmware processing. Especially.

[0025]

A line test circuit according to the present invention comprises a generation means for generating a control signal for line test according to an instruction signal from the outside, and an insert test for the line based on the control signal. Of the test data generating means for generating the test data of (1) and a monitor means for performing a monitor test for the line based on the control signal. According to the line connection time switch for connecting the input side line and the output of the tester and the output side line and the input of the tester, respectively, the line connection information is generated according to the instruction signal from the outside. And a line connection control means for controlling the line connection by the line connection time switch.

In addition to the above configuration, another line test circuit according to the present invention converts the output of the input side line and the tester into parallel data of predetermined bits and outputs the parallel data to the time switch for line connection. It is provided with a conversion means and a format reverse conversion means for converting the parallel data of the predetermined bit output from the time switch for line connection into the line on the output side and the input of the tester.

[0027]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the line setting controller 3 receives the time slot information 111 and the HW number 1 received from the controller 1.
12, the connection setting information 113 is sent to the line connection time switch (hereinafter, referred to as time switch) 5.

The format conversion section 4 includes a tester 2-i (i
= 1, 2, ..., M) from the m inward HW signal groups 101 and the n inward HW signal groups 102 are converted into 8-bit parallel data 103 and sent to the time switch 5.

The time switch 5 accommodates m inward HW signal groups 101 and n inward HW signal groups 102.
It can be processed. That is, the time switch 5 replaces the 8-bit parallel data 103 input from the format conversion unit 4, and outputs the 8-bit parallel data 104 that is the replacement result to the format inverse conversion unit 6.

The format reverse conversion unit 6 includes a time switch 5
Of 8-bit parallel data 104 from M to H-signals 105 to the tester 2-i
It is converted into the signal group 106 and transmitted.

In one embodiment of the present invention, in the line connection circuit composed of the line setting control unit 3, the format conversion unit 4, the time switch 5 and the format inverse conversion unit 6, the internal direction HW signal group 101 and the external direction HW signal. The functions of the insert test and the monitor test are added by assigning the group 105 and the line test HW signal to the tester 2-i, and the loop test function can be realized by the existing line connection function.

The tester 2-i comprises a test control pulse generator 21-i, a test data generator 22-i, and a monitor circuit 23-i. In addition, in the figure,
Although only the configuration of 1 is illustrated, other testers 2-2 to 2-2
-M also has the same configuration as the illustrated tester 2-1. Further, n represents the number of HW signals, and m corresponds to the required number of testers.

The operation of the circuit test according to the embodiment of the present invention will be described with reference to FIG. In this case, when the operator designates the tester, the HW signal, the test type, and the time slot for performing the line test, the control unit 1 causes the time slot information 111, the HW number 112, the test type information 114, and the tester number 115. And are output respectively.

The test control pulse generator 21-i is the controller 1
When the time slot information 111, the test type information 114, and the tester number 115 are received from, the tester number 115 determines whether or not the control request is for the own tester.

When the test control pulse generator 21-i determines that it is a control request for its own tester, it sends an insert pulse 121 designating an insert time slot or a monitor pulse 122 designating a monitor time slot according to the test type information 114. Occur.

Since the insert pulse 121 is output from the test control pulse generator 21-i during the insert test, the test data generator 22-i receiving this insert pulse 121 causes the insert data 123 to match the frame format of the HW signal. To occur. The test data generator 22-i sends the insert data 123 to the format converter 5 as one HW signal in the inward HW signal group 101.

At this time, when the line setting control unit 3 receives the time slot information 111 and the HW number 112 from the control unit 1, the internal direction HW is set in the same manner as the normal line connection setting.
The time slot of the signal is controlled to be connected to the time slot of the external HW signal of the insertion destination.

On the other hand, during the monitor test, the line setting control unit 3 which has received the time slot information 111 and the HW number 112 from the control unit 1 monitors the time slot of the internal direction HW signal as the monitor destination in the same manner as the normal line connection setting. External direction H
Control to connect to the time slot of the W signal.

At this time, the test control pulse generator 21-i
Since the monitor pulse 122 is output from the monitor circuit 23-i, the monitor circuit 23-i inputs one HW signal in the external direction HW signal group 105 output from the format inverse conversion unit 6 and the monitor pulse 122, and outputs the monitor result 124. Output.

Further, during the loop test, the line setting control unit 3 which has received the time slot information 111 and the HW number 112 from the control unit 1 sets the time slot of the internal direction HW signal to the external direction HW in the same manner as the normal line connection setting. Control to connect to the signal time slot.

As described above, the line test (insert, monitor,
The loop) is set and released by controlling the tester 2-i and sending the connection setting information 113 from the line setting control unit 3 which has received the time slot information 111 and HW number 112 to be tested to the time switch 5. By performing the above, it is possible to realize by the same method as in the case of performing the change setting of the normal line connection.

FIG. 2 is a diagram for explaining the operation of the time switch 5 of FIG. In the figure, the time switch 5 comprises a cycle counter 51, a data memory 52, and an address control memory 53.

The cycle counter 51 periodically outputs a counter value of "1" to "4" to the data memory 52 and the address control memory 53. The counter value from the cycle counter 51 is input to the data memory 52 as a data write address, and the address control memory 5
The counter value from the cycle counter 51 is input to 3 as a data read address.

The line connection information is written in advance in the address control memory 53, and the line connection information designated by the counter value from the cycle counter 51 is output to the data memory 52 as a data read address.

That is, the address control memory 5
The address 3 indicates the connection destination information, the line connection information written in the address indicates the connection source information, and the connection destination information and the connection source information refer to the connection setting information 113 from the line setting control unit 3. Shows.

In this case, the connection destination information is obtained by converting the HW number of the connection destination and the time slot number into the corresponding address of the address control memory 53, and the connection source information is the HW number of the connection source and the time slot number. Is converted into the corresponding address of the data memory 52.

Therefore, by writing the connection source information in the address control memory 53 using the connection destination information as a write address, the address control memory 53
Is set.

Input data 1 in the data memory 52
The input data is written in the arrival order (sequential) of each cycle, and the data is randomly read from the data memory 52 according to the read address output from the address control memory 53, whereby the order of the input data is changed.

As a result, the positions of the data on the time axis on the input side and the output side of the time switch 5 are exchanged, and the lines are connected. In the connection of the line, the data on the input side and the output side of the time switch 5 are converted into a frame format in which the data is arranged in time series for each data as a line connection unit.

That is, the time switch 5 is connected to the parallel data 10
The format conversion unit 4 that outputs 3 converts the in-direction HW signal group 101 and the in-direction HW signal group 102 into a frame format in which each data is arranged in time series, and the time switch 5 as 8-bit parallel data 103. Send to.

Also, from the time switch 5 to the parallel data 10
The format reverse conversion unit 6 which inputs 4 is the time switch 5
8-bit parallel data 104, that is, a frame format in which each data is arranged in time series is converted into an external direction HW signal group 105 and an external direction HW signal group 106 and transmitted.

Since the format conversion processing and the format inverse conversion processing in the format conversion unit 4 and the format inverse conversion unit 6 are well-known techniques, detailed description thereof will be omitted.

Here, the data of the connection source "1" is changed to "A",
The data of the connection source “2” is “B”, the data of the connection source “3” is “C”, the data of the connection source “4” is “D”, and the connection source is “1” in the address control memory 53. "4", connection destination "2" connection source "3", connection destination "3" connection source "1", connection destination "4" connection source "2"
The operation in the case where the line connection information is set so as to connect to each other will be described.

First, in the case of a normal line connection, the data on the input side of the time switch 5 are sequentially received in the data memory 52.
Therefore, in the data memory 52, the data “A” is stored in the address “1”, the data “B” is stored in the address “2”, the data “C” is stored in the address “3”, and the data “C” is stored in the address “4”. "D" is written respectively.

In this case, the address control memory 5
Since the line connection information as described above is set in 3, when the data is read from the address control memory 53 by the read address from the cycle counter 51, “4” and “3” are written to the data memory 52. ，
Read addresses are supplied in the order of "1" and "2".

Therefore, data is output from the output side of the time switch 5 in the order of "D", "C", "A", and "B", and the connection is made according to the setting of the line connection information. The data of the source "1" is connected to the destination "3", the data of the source "2" is connected to the destination "4", the data of the source "3" is connected to the destination "2", and the data of the source "4" is connected. The data will be output to the connection destination “1”, respectively.

Next, the connection sources "1" and "2" are the inward HW signal group 101 from the tester 2-i, and the connection sources "3" and "4" are the inward HW signal group 102, Various tests in one embodiment of the present invention, where the connection destinations "1" and "2" are the outward direction HW signal group 105 to the tester 2-i and the connection sources "3" and "4" are the outward direction HW signal group 106. Will be described.

During the insert test, the tester 2-i sends the insert data 123 as one HW signal in the inward HW signal group 101. Therefore, the line setting controller 3 addresses the address control memory 53 of the time switch 5. "3" or "1" at address "4"
Alternatively, write "2".

For example, the address control memory 53
If "1" is written to the address "3" of the connection source, the insert data from the connection source "1" is output to the external HW signal of the connection destination "3", and the time slot of the internal direction HW signal is inserted to the insert destination. Is connected to the time slot of the external HW signal.

Further, since one HW signal in the inward HW signal group 102 is taken into the tester 2-i during the monitor test, the line setting controller 3 causes the address "1" of the address control memory 53 of the time switch 5 to be read. , Or “3” or “4” is written in the address “2”.

For example, the address control memory 53
If "4" is written to the address "1" of the connection source, the data from the connection source "4" is output to the external direction HW signal group 105 of the connection destination "1" and is captured by the tester 2-i. . Therefore, the time slot of the internal HW signal group 102 is connected to the time slot of the monitored external HW signal group 105.

At this time, the test control pulse generator 21-i
Since the monitor pulse 122 is output from the monitor circuit 23-i, the monitor circuit 23-i inputs one HW signal in the external direction HW signal group 105 output from the format inverse conversion unit 6 and the monitor pulse 122, and outputs the monitor result 124. Output.

Further, during the loop test, one HW signal in the inward HW signal group 102 is sent to one HW signal in the outward HW signal group 106 to the same device, so that the line setting control unit 3 sets the time. "3" or "4" is written in the address "3" or the address "4" of the address control memory 53 of the switch 5.

For example, the address control memory 53
If "3" is written to the address "3" of the above, the data from the connection source "3" is output to the external direction HW signal group 106 of the connection destination "3", and the time slot of the internal direction HW signal is the same. It is connected to the time slot of the HW signal in the outward direction of the device and returned.

As described above, in the existing line connection circuit, the number of HW signals corresponding to the required number of the tester 2-i out of the number of HW signals that the time switch 5 can accommodate is set to the tester 2-.
By assigning it for i, the insert test, the monitor test, and the loop test can be performed in the same manner as the normal line connection.

Further, since all the HW signals are concentrated on the time switch 5 and the existing line connection circuit can be used, etc., the HW signal control which is required for each HW signal in the conventional technique is performed. No circuit is required, and the interface between the functional blocks can be reduced.

Therefore, the hardware scale is greatly reduced as compared with the conventional circuit, the existing line connection function can be used in the firmware processing, and the HW signal control circuit is not required. Can be simplified.

[0069]

As described above, according to the present invention, line connection information is generated according to an external instruction signal used for generating a control signal for line test, and input according to this line connection information. By controlling the insert test, the monitor test and the loop test in the line test circuit by connecting the output of the line and the tester of the output side and the input of the line and the tester of the output side with the time switch for line connection. ,
The hardware scale can be reduced, and the control method in firmware processing and the test setting processing can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a diagram showing an operation of the line connection time switch of FIG.

FIG. 3 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 control part 2-1 to 2-m tester 3 line setting control part 4 format conversion part 5 line connection time switch 6 format inverse conversion part 21-1 test control pulse generation part 22-1 test data generation part 23-1 Monitor circuit

Claims (3)

[Claims] 1. A generation unit for generating a control signal for line test according to an instruction signal from the outside, and a test data generation unit for generating test data for an insert test for the line based on the control signal. A line test circuit comprising a tester including a monitor means for performing a monitor test on the line based on the control signal, wherein the line on the input side and the output of the tester according to preset line connection information. And a line connection time switch for connecting the output side line and the input of the tester, respectively, and the line connection information is generated according to the instruction signal from the outside to connect the line connection by the line connection time switch. A line test circuit having a line connection control means for controlling. 2. A format conversion means for converting the line on the input side and the output of the tester into parallel data of predetermined bits and outputting the parallel data to the time switch for line connection, and the predetermined unit output by the time switch for line connection. 2. The line test circuit according to claim 1, further comprising format reverse conversion means for converting parallel data of bits into the line on the output side and the input of the tester. 3. The line connection control means is configured to control the line connection by the time switch for line connection at least in each of the insert test, the monitor test and the loop test. The line test circuit according to claim 2.