JPH0588930A - Simulating circuit - Google Patents

Abstract

PURPOSE:To realize the high-quality software evaluating device which secures the real time property without complicating the hardware configuration by generating a response in accordance with the analysis result of contents of a transmission buffer and the contents of a memory area and writing it in a reception buffer. CONSTITUTION:A CPU 1 is connected to an analysis part 4 through a serial interface transmission buffer part 2 which holds control data of packages 1 to N from an evaluation object software and a serial interface reception buffer part 3 which holds the response data from the analysis part 4. The analysis part 4 analyzes the control data from the evaluation object software held in the transmission buffer part 2 and uses a memory 5 to perform the processing corresponding to a command number. The analysis part 4 writes the response data as the processing result, namely, each frame of a packet for serial transmission of the reception data format in the reception buffer part 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulation circuit, and more particularly to a simulation circuit which uses a multipoint serial interface as an external interface with each of a plurality of packages constituting an apparatus and evaluates software for real-time control of each package. Regarding

[0002]

2. Description of the Related Art In new software development, real-time performance is required during control, and when evaluating new software for a device whose external interface is a multipoint serial interface, it is necessary to evaluate the software in an environment close to the actual device. There is.

Conventionally, in a simulation circuit for evaluating this kind of software, as shown in FIG.
A serial interface termination unit (hereinafter referred to as a termination unit) on the CPU 1 side connected to U1 via a serial interface transmission buffer unit (hereinafter referred to as a transmission buffer unit) 2 and a serial interface reception buffer unit (hereinafter referred to as a reception buffer unit) 3. ) 8 is connected to the multipoint serial interface (hereinafter referred to as a serial interface) 9 by arranging the simulation circuits 10-1 to 10-N at the end portions of the packages 1 to N (not shown) side. ing. This simulation circuit 10-1 to 10
-N is a multipoint serial interface termination unit (hereinafter referred to as termination unit) 10a-1 to 10a-N, a serial transmission packet analysis unit 10b-1 to 10b-N, and a memory unit 1.
It consists of 0c-1 to 10c-N.

The memory units 10c-1 to 10c-N hold the data in place of the registers or selectors to be controlled, and the contents thereof can be referred to or changed by using the packet for serial transmission. There is. In addition, the memory unit 10c-1
External inputs to -10c-N and inputs from the external input generation unit 12 are also possible via the OR circuits 11-1 to 11-N, and the contents of the memory units 10c-1 to 10c-N are directly changed. It is possible to do so, and it has a configuration that can respond to autonomous changes.

When evaluating new software, FIG.
As shown in, the evaluation target software is package 1
When N control data is output (step 30 in FIG. 5), C
PU1 writes the control data from the evaluation target software in the transmission buffer unit 2 (step 31 in FIG. 5).

The control data written in the transmission buffer unit 2 is transmitted from the terminating unit 8 through the serial interface 9 to the respective simulation circuits 10-1 to 10-1 corresponding to the packages 1 to N.
0-N (step 32 in FIG. 5).

In each of the simulation circuits 10-1 to 10-N, the control data received by the terminal units 10a-1 to 10a-N is analyzed by the analysis unit 10b-1 to 10b-N. That is, the analysis unit 10
b-1 to 10b-N are the package number of the address field in each frame in the serial transmission packet of the transmission data format shown in FIG. And the command No. Package No. Is N of own package
o. If so, capture that frame and enter the command No. Is performed (step 33 in FIG. 5).

At this time, the analysis units 10b-1 to 10b-N send the command No. Is a request for setting, the value of the data field of the frame (setting result data) is written in the memory units 10c-1 to 10c-N, and then the memory unit 10
The setting result data written in c-1 to 10c-N is written as the setting response data in the data field in each frame in the serial transmission packet of the reception data format shown in FIG. 6B, and the frame is terminated. -1 ~ 1
0a-N through the serial interface 9 to the terminal 8
(Step 34 in FIG. 5).

Further, the analysis units 10b-1 to 10b-N use the command No. Is a read request, the memory unit 1
The contents of 0c-1 to 10c-N are read, the read value is written as a read response in the data field in each frame of the serial transmission packet, and the frame is terminated.
Output from a-1 to 10a-N to the terminal unit 8 through the serial interface 9 (step 35 in FIG. 5).

Each frame of the serial transmission packet output from the terminating units 10a-1 to 10a-N of each of the simulation circuits 10-1 to 10-N via the serial interface 9 is received by the terminating unit 8 and received. It is written in the buffer unit 3 (step 36 in FIG. 5). When the response data from each of the simulation circuits 10-1 to 10-N is written in the reception buffer unit 3, the CPU 1 reads the response data from the reception buffer unit 3 (step 37 in FIG. 5), and the evaluation target software is the CPU 1 It operates by inputting the response data of the packages 1 to N read in (step 38 in FIG. 2).

In such a conventional simulation circuit,
Since the simulation circuits 10-1 to 10-N are installed at the end portions of the serial interface 9 on the side of the packages 1 to N, the package 1 is installed at the end portion of the serial interface 9.
A circuit similar to that for N is required, and the memory units 10c-1 to 1
0c-N is also required for each terminal unit, so package 1
There is a problem that the use efficiency of the memory units 10c-1 to 10c-N deteriorates when the data amount differs depending on the types of.

Further, in a device including a plurality of packages 1 to N to be controlled, if it is necessary to evaluate the mounting state of all packages, all the termination parts 10 are connected.
a-1 to 10a-N, analysis units 10b-1 to 10b-N, and memory units 10c-1 to 10c-N as a set.
There is a problem that 0-1 to 10-N must be arranged.

Further, when data is set in a memory of a certain package by a setting command to change the contents of the memory of another package different from the package, the contents of the memory of that package are synchronized with the setting command. To change the contents, provide an interface to connect the packages so that the contents of the memory of other packages can be changed, or after the creator confirms the state of a package set by the setting command, The contents of the memory of other packages need to be changed by external input. In the former case, an interface must be provided between the packages, so there is a problem that the hardware configuration becomes complicated, and in the latter case, there is a problem that the real-time property is impaired due to the intervention of the creator.

[0014]

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned problems of the conventional one, and to realize a high-quality software evaluation environment that guarantees real-time property without complicating the hardware configuration. The purpose is to provide a simulation circuit capable of

[0015]

The simulation circuit according to the present invention is a simulation circuit for evaluating software for performing real-time control of each of a plurality of packages constituting an apparatus through a serial interface, and is operated by the software. Central processing unit, transmission buffer means for holding serial transmission packets transmitted from the central processing unit to the plurality of packages, and holding serial transmission packets transmitted from the plurality of packages to the central processing unit Reception buffer means, storage means having an area corresponding to each of the plurality of packages and corresponding to a data field of the serial transmission packet, and contents of the area stored in other areas and external input Change based on at least one of the content The serial transmission packet held in the transmission buffer means, and the serial transmission packet is analyzed according to the analysis result and the contents of the area of the storage means corresponding to the destination package of the serial transmission packet. And an analyzing means for generating a response to the packet and writing the response in the reception buffer means.

[0016]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a CPU 1 holds a serial interface transmission buffer unit (hereinafter referred to as a transmission buffer unit) 2 that holds control data of packages 1 to N (not shown) from the evaluation target software, and response data from an analysis unit 4. It is connected to the analysis unit 4 via a serial interface reception buffer unit (hereinafter referred to as a reception buffer unit) 3.

The analysis unit 4 controls the control data from the evaluation target software held in the transmission buffer unit 2, that is, FIG.
The package number of the address field of each frame of the serial transmission packet having the transmission data format as shown in (a). And the command No. Is analyzed and the command No. Perform processing according to. The analysis unit 4 receives response data as a result of this processing, that is, FIG.
Each frame of the serial transmission packet having the reception data format as shown in (b) is written in the reception buffer unit 3.

The memory 5 is an area corresponding to each package 1-N (memory for package 1, memory for package 2,
.. (package N memory), and its contents can be changed by an external input input via the OR circuit 7 or an external input generated by the external input generation unit 6.

FIG. 2 is a flow chart showing the operation sequence of one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.

When evaluating new software, when the evaluation target software outputs the control data of the packages 1 to N (step 20 in FIG. 2), the CPU 1 writes the control data from the evaluation target software in the transmission buffer section 2 ( 2 step 21).

When the control data is written in the transmission buffer unit 2, the analysis unit 4 directly refers to the contents of the transmission buffer unit 2 and sequentially analyzes the control data of the packages 1 to N (step 22 in FIG. 2). In this case, since each frame of the serial transmission packet having the transmission data format as shown in FIG. 6A is written in the transmission buffer unit 2,
The analysis unit 4 determines the package number of the address field in each frame. And the command No. Parse the command N
o. Perform processing according to. The analysis unit 4 displays the result of the processing as the package number in the frame. Is written in the area of the memory 5 corresponding to (step 23 in FIG. 2).

At this time, the analysis unit 4 sends the command No. Is a request for setting, the value of the data field of the frame (setting result data) is set in the package N of the memory 5.
o. Then, the setting result data written in the memory 5 is written in the receiving buffer unit 3 as setting response data. In this case, FIG.
Each frame of the serial transmission packet having the reception data format as shown in (b) is written as setting response data (step 24 in FIG. 2).

Further, the analysis unit 4 uses the command No. Is a read request, the package number. The content of the area of the memory 5 corresponding to is read and the read value is written in the reception buffer unit 3 as a read response. In this case, each frame of the serial transmission packet having the reception data format as shown in FIG. 6B is written in the reception buffer unit 3 as a read response (step 25 in FIG. 2).

When the response data is written in the reception buffer unit 3, the CPU 1 reads the response data from the reception buffer unit 3 (step 26 in FIG. 2), and the evaluation target software is read by the CPU 1 and the responses of the packages 1 to N are read. It operates by inputting data (step 27 in FIG. 2).

FIG. 3 is a diagram showing state transitions in the memory 5 of FIG. The figure shows a case where the data of the memory of the package N is changed to the data 2a by setting the data a in the memory of the package 1 by the setting command.

In this case, when the data a is set in the area corresponding to the package 1 of the memory 5, the data 2a generated by the external input generation unit 6 corresponds to the package N of the memory 5 via the OR circuit 7. Written in the area. That is, the external input generation unit 6 monitors each area of the memory 5, and when detecting that the data a is set in the area corresponding to the package 1, generates the data 2a according to a preset operation sequence. The data 2a is output by designating an area corresponding to the package N.

Therefore, when the content of the area corresponding to the package N is changed to the data 2a in synchronization with the setting command for setting the data a in the area corresponding to the package 1,
It is not necessary to provide an interface for connecting the packages as in the conventional case, and it is not necessary to change the contents of the memory of the package N by external input again after the producer confirms the state of the package 1. This makes it possible to realize a high-quality software evaluation environment without complicating the hardware configuration and without impairing the real-time property.

In one embodiment of the present invention, when a plurality of packages 1 to N are controlled in the device-embedded software via the multipoint interface, the cut-off from the device-embedded software side is the transmission buffer and the reception buffer of the serial interface. Only. Further, on the transmission buffer and the reception buffer, since the data of the plurality of packages 1 to N are on the same memory, it is possible to access the data of the plurality of packages at the same time. Focusing on this, the control data from the device-embedded software is analyzed by the data on the transmission buffer unit 2, and the response of the analysis result is directly received by the reception buffer unit 3.
By writing in, the simulation of the software embedded in the device is realized.

With the above structure, C
When viewed from the PU1 side, the same operation as the conventional simulation circuit is performed on the transmission buffer unit 2 and the reception buffer unit 3, so that a pseudo device environment is realized in the same environment as the operation of the register and selector of the device unit. be able to. Also, it is possible to evaluate without affecting the number of controlled objects to be mounted.
Moreover, real-time performance can be realized, and evaluation of the software embedded in the device can be realized.

As described above, the control data from the evaluation target software written in the transmission buffer unit 2 from the CPU 1 is analyzed by the analysis unit 4 and the analysis result is stored in the areas corresponding to the packages 1 to N of the memory 5. Write the response data according to the analysis result via the reception buffer unit 3 to C
By sending to PU1, the simulation circuit conventionally arranged at each terminal of the multipoint serial interface becomes unnecessary, and the number of control target implementations is affected by the evaluation of the evaluation target software in the actual environment. It is possible to evaluate the evaluation target software without any trouble. In other words, the hardware configuration does not become large even in the evaluation of the mounting states of all packages, and the required number can be prepared according to the control target.

Further, as shown in FIG. 3, even when the data in the memory of the package N is changed to the data 2a by setting the data a in the memory of the package 1 by the setting command, the external input generation is performed. By setting the operation sequence in the unit 6 in advance, the contents of the memory of the package N can be changed to the data 2a in synchronization with the setting command, and the hardware configuration becomes complicated as in the conventional case, There is no loss of real-time performance. Therefore, it is possible to realize a high-quality software evaluation environment that guarantees real-time performance without complicating the hardware configuration.

[0033]

As described above, according to the present invention, the contents of the transmission buffer that holds the serial transmission packets transmitted from the central processing unit to the plurality of packages are analyzed, and the analysis result and the serial transmission packets are analyzed. By generating a response to the packet for serial transmission according to the contents of the memory area corresponding to the package of the packet transmission destination and writing the response in the reception buffer, real-time operation is realized without complicating the hardware configuration. There is an effect that it is possible to realize a high-quality software evaluation environment that guarantees.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a flowchart showing an operation sequence of an embodiment of the present invention.

FIG. 3 is a diagram showing state transitions in the memory of FIG.

FIG. 4 is a block diagram showing a configuration of a conventional example.

FIG. 5 is a flowchart showing an operation sequence of a conventional example.

FIG. 6 is a diagram showing an example of a data format of a serial interface.

[Explanation of symbols]

 1 CPU 2 Serial interface transmission buffer unit 3 Serial interface reception buffer unit 4 Analysis unit 5 Memory 6 External input generation unit

Claims (1)

[Claims] 1. A simulation circuit for evaluating software for performing real-time control of each of a plurality of packages constituting the apparatus through a serial interface, the central processing unit operating by the software, and the central processing unit. Transmission buffer means for holding serial transmission packets transmitted from the device to the plurality of packages; reception buffer means for holding serial transmission packets transmitted from the plurality of packages to the central processing unit; Storage means corresponding to each package and having an area corresponding to the data field of the serial transmission packet, and the content of the area to at least one of the content held in another area and the content of external input Change means for changing based on the transmission buffer means The held serial transmission packet is analyzed, a response to the serial transmission packet is generated and received in accordance with the analysis result and the contents of the area of the storage means corresponding to the package of the transmission destination of the serial transmission packet. A simulation circuit comprising: an analysis means for writing in a buffer means.