JPH07226531A - Manufacture of photodetector - Google Patents
Manufacture of photodetectorInfo
- Publication number
- JPH07226531A JPH07226531A JP6017113A JP1711394A JPH07226531A JP H07226531 A JPH07226531 A JP H07226531A JP 6017113 A JP6017113 A JP 6017113A JP 1711394 A JP1711394 A JP 1711394A JP H07226531 A JPH07226531 A JP H07226531A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- type
- mesa
- organic compound
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
Description
【発明の詳細な説明】Detailed Description of the Invention
【０００１】[0001]
【産業上の利用分野】本発明は、大容量，高速光伝送・
通信用の受光素子の製造方法に係り、特に、実装及び配
線に必要となる電極・配線或いは該パッド部に起因する
寄生容量の小さい受光素子の製造方法に関する。BACKGROUND OF THE INVENTION The present invention relates to large capacity, high speed optical transmission.
The present invention relates to a method for manufacturing a light receiving element for communication, and more particularly to a method for manufacturing a light receiving element having a small parasitic capacitance due to electrodes / wirings required for mounting and wiring or the pad portion.
【０００２】[0002]
【従来の技術】光ファイバを用いた光伝送用の受信デバ
イスとしてＩｎＧａＡｓ／ＩｎＰ系のｐ−ｉ−ｎフォト
ダイオード（ｐｉｎ−ＰＤ）、特にアレー状に配置され
たｐ−ｉ−ｎ ＰＤが注目されている。フォトダイオー
ドにより変換された電気信号は電子回路部に入力され
る。受光素子と電子回路部の接続は、例えば、ジャーナ
ルオブ ライトウェーブ テクノロジ 第８巻 第６号
（１９９０年）８８３−８８７頁に記載されているよう
に受光素子の電極パッドと電子回路部或いは中継用マウ
ント上のパッドを実装技術を用いてワイヤにより接続し
ている。受光素子側のパッド部はメサ形状のダイオード
構造に被覆した絶縁膜上に設けられている。2. Description of the Related Art As a receiving device for optical transmission using an optical fiber, an InGaAs / InP-based pin photodiode (pin-PD), particularly a pin PD arranged in an array, is noted. Has been done. The electric signal converted by the photodiode is input to the electronic circuit unit. The connection between the light receiving element and the electronic circuit section is performed, for example, as described in Journal of Light Wave Technology Vol. 8, No. 6 (1990), pages 883-887, and the electrode pad of the light receiving element and the electronic circuit section or for relaying. The pads on the mount are connected by wires using mounting technology. The pad portion on the side of the light receiving element is provided on the insulating film that covers the mesa-shaped diode structure.
【０００３】[0003]
【発明が解決しようとする課題】上述した従来技術で
は、絶縁膜上に設けたパッド部に起因する容量がフォト
ダイオードの寄生容量として加わる。このようなフォト
ダイオードの寄生容量は次世代の高速光伝送システムを
実現する上で大きな障害となるため、極力低減する必要
がある。In the above-mentioned conventional technique, the capacitance due to the pad portion provided on the insulating film is added as the parasitic capacitance of the photodiode. Since the parasitic capacitance of such a photodiode becomes a major obstacle in realizing a next-generation high-speed optical transmission system, it is necessary to reduce it as much as possible.
【０００４】[0004]
【課題を解決するための手段】上記課題を解決するため
に、半導体基板上に形成したｐｎ接合を含む半導体層を
形成し、第１の絶縁膜マスクを用いて前記半導体層をエ
ッチングすることによりメサ形状のダイオード構造を形
成する。その後、前記第１の絶縁膜マスクを含む前記メ
サ形状ダイオード上に珪素の有機化合物の分解酸化反応
を用いて第２の絶縁膜を形成する。その後、前記メサ形
状のフォトダイオードの周辺上の前記第２の絶縁膜上に
電極・配線及びパッドの一部を形成する。In order to solve the above problems, a semiconductor layer including a pn junction formed on a semiconductor substrate is formed, and the semiconductor layer is etched using a first insulating film mask. A mesa-shaped diode structure is formed. Then, a second insulating film is formed on the mesa-shaped diode including the first insulating film mask by using a decomposition and oxidation reaction of an organic compound of silicon. After that, a part of electrodes / wirings and pads is formed on the second insulating film on the periphery of the mesa-shaped photodiode.
【０００５】[0005]
【作用】本発明では、珪素の有機化合物の分解酸化反応
を用いて形成した第２の絶縁膜の膜内応力は小さいた
め、通常のＳｉＨ4 ガス等を用いたＣＶＤによる絶縁膜
に比べ厚い絶縁膜の形成（１〜２μｍ以上）が可能にな
る。従って、第２の絶縁膜上に設けたパッド部に起因す
る寄生容量は第２の絶縁膜の膜厚に反比例して低減す
る。また、珪素の有機化合物を用いた第２の絶縁膜の形
成を第１の絶縁膜マスクを含むメサ形状ダイオード上に
対して行っている。このとき第２の絶縁膜の堆積速度
は、メサ周辺の半導体層が露出した領域上の方が第１の
絶縁膜上に比べて大きいことが実験的に確かめられてい
る。そのため、メサ周辺上の第２の絶縁膜が第１の絶縁
膜上の第２の絶縁膜に比べて相対的に厚くでき、第２の
絶縁膜を用いてメサ形状のダイオード構造を埋込み、自
己平坦化することが可能になる。In the present invention, since the second insulating film formed by the decomposition and oxidation reaction of the organic compound of silicon has a small stress in the film, the second insulating film is thicker than the insulating film formed by ordinary CVD using SiH 4 gas or the like. A film can be formed (1 to 2 μm or more). Therefore, the parasitic capacitance due to the pad portion provided on the second insulating film is reduced in inverse proportion to the film thickness of the second insulating film. Further, the formation of the second insulating film using the organic compound of silicon is performed on the mesa-shaped diode including the first insulating film mask. At this time, it is experimentally confirmed that the deposition rate of the second insulating film is higher on the exposed region of the semiconductor layer around the mesa than on the first insulating film. Therefore, the second insulating film on the periphery of the mesa can be made relatively thicker than the second insulating film on the first insulating film, and the second insulating film is used to embed the mesa-shaped diode structure. It becomes possible to flatten.
【０００６】[0006]
（実施例１）本発明の一実施例として、ＩｎＧａＡs／
ＩnＰ系のｐ−ｉ−ｎ型ＰＤの製造に適用した例を図１
および図２に示す素子断面の工程図を用いて説明する。
ＩｎＰ基板１００上にＭＯＣＶＤ法を用いてｎ型ＩｎＰ
層１０１，低濃度ＩｎＧａＡｓ層１０２及び低濃度Ｉｎ
Ｐ層１０３を順次積層した（図１(ａ)）。次いで、ｐ型
ドーパントとなるＺｎを低濃度ＩｎＰ層１０３の所望の
領域に選択的に導入してｐ型ＩｎＰ層１０４を形成した
（図１(ｂ)）。Ｚｎの導入方法は通常、気相拡散法或い
はイオン注入法が一般的に用いられる。次に通常のＣＶ
Ｄ法を用いて第１の絶縁膜１０５を形成した（図１
(ｃ)）。次いで、通常のリソグラフィとエッチング技術
を用いてｐ型ＩｎＰ層１０４を含む領域に第１の絶縁膜
１０５よりなるマスク１０６を形成した（図１(ｄ)）。(Example 1) As one example of the present invention, InGaAs /
FIG. 1 shows an example applied to the production of an InP-based pin PD.
And it demonstrates using the process drawing of the element cross section shown in FIG.
N-type InP is formed on the InP substrate 100 using the MOCVD method.
Layer 101, low concentration InGaAs layer 102 and low concentration In
P layers 103 were sequentially laminated (FIG. 1A). Then, Zn serving as a p-type dopant was selectively introduced into a desired region of the low-concentration InP layer 103 to form a p-type InP layer 104 (FIG. 1B). As a method for introducing Zn, a vapor phase diffusion method or an ion implantation method is generally used. Then a normal CV
The first insulating film 105 was formed by using the D method (see FIG. 1).
(c)). Then, a mask 106 made of the first insulating film 105 was formed in the region including the p-type InP layer 104 by using ordinary lithography and etching techniques (FIG. 1 (d)).
【０００７】次に、第１の絶縁膜１０５よりなるマスク
１０６を用いて低濃度ＩｎＰ層103及び低濃度ＩｎＧａ
Ａｓ層１０２をエッチングしてメサ形状のダイオードを
形成した（図２(ａ)）。次いで、通常のリソグラフィと
エッチング技術をｎ型ＩｎＰ層１０１の所望の領域を除
去して素子間の分離を行った（図２(ｂ)）。その後、Ｔ
ＥＯＳ(tetraethoxysilane)とＯ3ガスを原料とした常圧
ＣＶＤ法を用いて第２の絶縁膜１０７を堆積して、メサ
形状を埋め込み平坦化した（図２(ｃ)）。このときのメ
サ周辺上の第２の絶縁膜１０７の厚さは約４μｍであ
る。また、ＣＶＤ原料ガスはＴＥＯＳガスは液体原料を
バブリングして供給し、Ｏ3 はオゾン発生装置を用いて
２〜６％濃度のＯ3をＯ2ベースで供給した。このときの
基板温度は３００〜３５０℃と低温でありＩｎＰ表面の
損傷・劣化は起こらない。次いで通常のリソグラフィ、
エッチング及びリフトオフ技術を用いてｐ型電極及びパ
ッド１０８とｎ型電極及びパッド１０９を形成する（図
２(ｄ)）。Next, the low-concentration InP layer 103 and the low-concentration InGa are formed using the mask 106 made of the first insulating film 105.
The As layer 102 was etched to form a mesa-shaped diode (FIG. 2A). Then, the desired regions of the n-type InP layer 101 were removed by the usual lithography and etching techniques to separate the elements (FIG. 2B). Then T
A second insulating film 107 was deposited by the atmospheric pressure CVD method using EOS (tetraethoxysilane) and O 3 gas as raw materials, and the mesa shape was embedded and flattened (FIG. 2C). At this time, the thickness of the second insulating film 107 on the periphery of the mesa is about 4 μm. Further, CVD source gas TEOS gas is supplied by bubbling a liquid raw material, O 3 is the O 3 2-6% strength by using the ozone generator was fed at a O 2 basis. At this time, the substrate temperature is as low as 300 to 350 ° C., and the InP surface is not damaged or deteriorated. Then normal lithography,
The p-type electrode and pad 108 and the n-type electrode and pad 109 are formed by using the etching and lift-off technique (FIG. 2D).
【０００８】本実施例では、厚さ約４μｍの第２の絶縁
膜１０７上にｐ型電極及びパッド１０８とｎ型電極及び
パッド１０９を形成しており、電極及びパッドに起因す
る寄生容量は通常のＳｉＨ4 ガスを用いた絶縁膜（厚さ
０.５〜０.７μｍ）上に形成された場合に比べて一桁程
度小さくできる。In this embodiment, the p-type electrode and pad 108 and the n-type electrode and pad 109 are formed on the second insulating film 107 having a thickness of about 4 μm, and the parasitic capacitance due to the electrode and pad is usually It can be reduced by about an order of magnitude as compared with the case where it is formed on an insulating film (thickness of 0.5 to 0.7 μm) using SiH 4 gas.
【０００９】また、ＴＥＯＳ(tetraethoxysilane)とＯ3
ガスを原料とした常圧ＣＶＤ法で形成した第２の絶縁膜
１０７の膜厚は半導体の露出したメサ周辺上（約４μ
ｍ）に比べて第１の絶縁膜１０５よりなるマスク１０６
上では２μｍと小さくなる。即ち、第２の絶縁膜１０７
の堆積速度の下地材料依存性によりメサ形状が自己平坦
化埋め込みされている。このような素子表面の平坦化は
特に後に続くリソグラフィ工程を容易にする。In addition, TEOS (tetraethoxysilane) and O 3
The film thickness of the second insulating film 107 formed by the atmospheric pressure CVD method using gas as a raw material is about 4 μm above the exposed mesa of the semiconductor.
The mask 106 made of the first insulating film 105 as compared with FIG.
Above, it becomes as small as 2 μm. That is, the second insulating film 107
The mesa shape is embedded by self-planarization due to the dependency of the deposition rate of the underlayer on the underlying material. Such planarization of the device surface facilitates especially the subsequent lithography process.
【００１０】本実施例ではＴＥＯＳ／Ｏ3 系の常圧ＣＶ
Ｄ法により第２の絶縁膜１０７を形成してメサ形状を埋
め込み平坦化しているが、その他のＳｉを含む有機化合
物、例えば、Ｂ〔ＯＳｉ(ＣＨ3)3〕3 を用いたＣＶＤ法
を用いても同様にメサ形状の埋め込み平坦化が可能であ
る。また、第２の絶縁膜１０７用のＣＶＤ原料ガスとし
てＳｉを含む有機化合物とＯ3を用いているが、さらに
Ｆ系ガス、例えば、ＣＦ4 等を添加することにより第２
の絶縁膜１０７の膜質の向上を図ることが可能である。
また、上述した実施例では第２の絶縁膜１０７の形成は
ＴＥＯＳ／Ｏ3 系の常圧ＣＶＤ法の一方式で形成してい
るが、ＴＥＯＳガスを用いたプラズマＣＶＤ法等も併用
した複数方式による多層絶縁膜よりなる第２の絶縁膜１
０７の形成が可能である。In this embodiment, the TEOS / O 3 system atmospheric pressure CV is used.
Although the second insulating film 107 is formed by the D method and the mesa shape is embedded and planarized, a CVD method using another organic compound containing Si, for example, B [OSi (CH 3 ) 3 ] 3 is used. However, the mesa shape can be similarly embedded and flattened. Further, although an organic compound containing Si and O 3 are used as a CVD source gas for the second insulating film 107, it is possible to add a F-based gas such as CF 4 to obtain a second
It is possible to improve the film quality of the insulating film 107.
Further, although the second insulating film 107 is formed by one method of the TEOS / O 3 -based atmospheric pressure CVD method in the above-described embodiment, a plurality of methods are also used together with the plasma CVD method using TEOS gas. Second insulating film 1 made of a multi-layer insulating film
It is possible to form 07.
【００１１】（実施例２）本発明の第２の実施例とし
て、ＩｎＧａＡｓ／ＩｎＰ系のｐ−ｉ−ｎ型ＰＤの製造
に適用した例を図３および図４に示す素子断面の工程概
略図を用いて説明する。ＩｎＰ基板２００上にＭＯＣＶ
Ｄ法を用いてｎ型ＩｎＰ層２０１，低濃度ＩｎＧａＡｓ
層２０２及び低濃度ＩｎＰ層２０３を順次積層した(図
３(ａ))。次いで、ｐ型ドーパントとなるＺｎを低濃度
ＩｎＰ層２０３の所望の領域に選択的に導入してｐ型Ｉ
ｎＰ層２０４を形成した（図３(ｂ)）。Ｚｎの導入方法
は通常、気相拡散法或いはイオン注入法が一般的に用い
られる。次に通常のリソグラフィとリフトオフ法を用い
てｐ型ＩｎＰ層２０４を含む領域に第１の絶縁膜２０５
よりなるマスク２０６を形成した(図３(ｃ))。次に、第
１の絶縁膜２０５よりなるマスク２０６を用いて低濃度
ＩｎＰ層２０３及び低濃度ＩｎＧａＡｓ層２０２２０２
をエッチングしてメサ形状のダイオードを形成した(図
３(ｄ))。(Embodiment 2) As a second embodiment of the present invention, an example applied to the manufacture of an InGaAs / InP-based pin type PD is shown in FIG. 3 and FIG. Will be explained. MOCV on InP substrate 200
N-type InP layer 201, low concentration InGaAs using the D method
The layer 202 and the low-concentration InP layer 203 were sequentially stacked (FIG. 3A). Then, Zn serving as a p-type dopant is selectively introduced into a desired region of the low-concentration InP layer 203 to p-type I.
An nP layer 204 was formed (FIG. 3 (b)). As a method for introducing Zn, a vapor phase diffusion method or an ion implantation method is generally used. Next, the first insulating film 205 is formed in the region including the p-type InP layer 204 by using ordinary lithography and lift-off method.
To form a mask 206 (FIG. 3C). Next, the low-concentration InP layer 203 and the low-concentration InGaAs layer 202202 are formed by using the mask 206 made of the first insulating film 205.
Was etched to form a mesa-shaped diode (FIG. 3D).
【００１２】次いで、通常のリソグラフィとエッチング
技術をｎ型ＩｎＰ層２０１の所望の領域を除去して素子
間の分離を行った（図４(ａ)）。その後、ＴＥＯＳ（te
traethoxysilane)とＯ3 ガスを原料とした常圧ＣＶＤ法
を用いて第２の絶縁膜２０７を堆積して、メサ形状を埋
め込み平坦化した（図４(ｂ)）。このときのメサ周辺上
の第２の絶縁膜２０７の厚さは約４μｍである。また、
ＣＶＤ原料ガスはＴＥＯＳガスは液体原料をバブリング
して供給し、Ｏ3 はオゾン発生装置を用いて２〜６％濃
度のＯ3をＯ2ベースで供給した。このときの基板温度は
３００〜３５０℃と低温でありＩｎＰ表面の損傷・劣化
は起こらない。次いで通常のリソグラフィ，エッチング
及びリフトオフ技術を用いてｐ型電極及びパッド２０８
とｎ型電極及びパッド２０９を形成する（図４(ｃ)）。Then, the desired regions of the n-type InP layer 201 were removed by the usual lithography and etching technique to separate the elements (FIG. 4A). After that, TEOS (te
The second insulating film 207 was deposited by the atmospheric pressure CVD method using traethoxysilane) and O 3 gas as raw materials, and the mesa shape was embedded and flattened (FIG. 4B). At this time, the thickness of the second insulating film 207 on the periphery of the mesa is about 4 μm. Also,
CVD source gas TEOS gas is supplied by bubbling a liquid raw material, O 3 is the O 3 2-6% strength by using the ozone generator was fed at a O 2 basis. At this time, the substrate temperature is as low as 300 to 350 ° C., and the InP surface is not damaged or deteriorated. Then p-type electrodes and pads 208 are formed using conventional lithography, etching and lift-off techniques.
Then, the n-type electrode and the pad 209 are formed (FIG. 4C).
【００１３】本実施例では、厚さ約４μｍの第２の絶縁
膜２０７上にｐ型電極及びパッド２０８とｎ型電極及び
パッド２０９を形成しており、電極及びパッドに起因す
る寄生容量は通常のＳｉＨ4 ガスを用いた絶縁膜（厚さ
０.５〜０.７μｍ）上に形成された場合に比べて一桁程
度小さくできる。In this embodiment, the p-type electrode and pad 208 and the n-type electrode and pad 209 are formed on the second insulating film 207 having a thickness of about 4 μm, and the parasitic capacitance due to the electrode and the pad is usually It can be reduced by about an order of magnitude as compared with the case where it is formed on an insulating film (thickness of 0.5 to 0.7 μm) using SiH 4 gas.
【００１４】また、ＴＥＯＳ(tetraethoxysilane)とＯ3
ガスを原料とした常圧ＣＶＤ法で形成した第２の絶縁膜
２０７の膜厚は半導体の露出したメサ周辺上（約４μ
ｍ）に比べて第１の絶縁膜２０５よりなるマスク２０６
上では２μｍと小さくなる。即ち、第２の絶縁膜２０７
の堆積速度の下地材料依存性によりメサ形状が自己平坦
化埋め込みされている。このような素子表面の平坦化は
後に続くリソグラフィ工程を容易にする。In addition, TEOS (tetraethoxysilane) and O 3
The film thickness of the second insulating film 207 formed by the atmospheric pressure CVD method using gas as a raw material is about 4 μm above the exposed mesa of the semiconductor.
The mask 206 made of the first insulating film 205 as compared with FIG.
Above, it becomes as small as 2 μm. That is, the second insulating film 207
The mesa shape is embedded by self-planarization due to the dependency of the deposition rate of the underlayer on the underlying material. Such planarization of the device surface facilitates the subsequent lithography process.
【００１５】上述した実施例ではＴＥＯＳ／Ｏ3 系の常
圧ＣＶＤ法により第２の絶縁膜２０７を形成してメサ形
状を埋め込み平坦化しているが、その他のＳｉを含む有
機化合物、例えば、Ｂ〔ＯＳｉ（ＣＨ3)3〕3 を用いた
ＣＶＤ法を用いても同様にメサ形状の埋め込み平坦化が
可能である。また、第２の絶縁膜２０７用のＣＶＤ原料
ガスとしてＳｉを含む有機化合物とＯ3 を用いている
が、さらにＦ系ガス例えばＣＦ4 等を添加することによ
り第２の絶縁膜２０７の膜質の向上を図ることが可能で
ある。また、上述した実施例では第２の絶縁膜２０６の
形成はＴＥＯＳ／Ｏ3 系の常圧ＣＶＤ法の一方式で形成
しているが、ＴＥＯＳガスを用いたプラズマＣＶＤ法等
も併用した複数方式による多層絶縁膜よりなる第２の絶
縁膜２０６の形成が可能である。In the above-mentioned embodiment, the second insulating film 207 is formed by the TEOS / O 3 -based atmospheric pressure CVD method to fill the mesa shape and flatten it. However, other organic compounds containing Si, for example, B Even if the CVD method using [OSi (CH 3 ) 3 ] 3 is used, the mesa shape can be similarly embedded and flattened. Although an organic compound containing Si and O 3 are used as the CVD source gas for the second insulating film 207, the quality of the second insulating film 207 can be improved by further adding an F-based gas such as CF 4 . It is possible to improve. Further, although the second insulating film 206 is formed by one method of the TEOS / O 3 -based atmospheric pressure CVD method in the above-described embodiments, a plurality of methods are also used together with the plasma CVD method using TEOS gas. It is possible to form the second insulating film 206 made of a multi-layer insulating film.
【００１６】（実施例３）本発明の第３の実施例とし
て、マッハ・ツェンダー型光変調器の製造への適用例を
図５および図６に示したマッハ・ツェンダー型光変調器
の電極形成部断面の工程図を用いて説明する。ｎ型Ｉｎ
Ｐ基板３００上にｎ型ＩｎＡｌＡｓ層３０１,ＧａＡｓ
／ＡｌＧａＡｓ系の多重量子井戸層３０２,ｐ型ＩｎＡ
ｌＡｓ層３０３及びｐ型ＩｎＧａＡｓ層３０４を順次積
層した（図５(ａ)）。次に通常のＣＶＤ法を用いて第１
の絶縁膜３０５を形成した（図５(ｂ)）。次いで通常の
リソグラフィとエッチング技術を用いて第１の絶縁膜３
０５よりなるマスク３０６を形成した（図５(ｃ)）。(Third Embodiment) As a third embodiment of the present invention, an example of application to manufacture of a Mach-Zehnder interferometer type optical modulator shown in FIGS. 5 and 6 is used to form electrodes of the Mach-Zehnder interferometer type optical modulator. The process will be described with reference to process drawings of cross sections. n-type In
N-type InAlAs layer 301, GaAs on P substrate 300
/ AlGaAs multiple quantum well layer 302, p-type InA
The 1As layer 303 and the p-type InGaAs layer 304 were sequentially laminated (FIG. 5A). Next, using the normal CVD method, the first
The insulating film 305 was formed (FIG. 5B). Then, the first insulating film 3 is formed by using ordinary lithography and etching techniques.
A mask 306 made of No. 05 was formed (FIG. 5C).
【００１７】その後、マスク３０６を用いてリアクティ
ブ・イオン・ビーム・エッチング(ＲＩＢＥ)法によりｐ
型ＩｎＧａＡｓ層３０４，ｐ型ＩｎＡｌＡｓ層３０３及
びＧａＡｓ／ＡｌＧａＡｓ系の多重量子井戸層３０２を
エッチングして垂直断面形状を有する導波路を形成した
(図６(ａ))。次に、ＴＥＯＳ(tetraethoxysilane)とＯ
3 ガスを原料とした常圧ＣＶＤ法を用いて第２の絶縁膜
３０７を堆積して、導波路を埋め込み平坦化した（図６
(ｂ)）。このときの導波路周辺上の第２の絶縁膜３０７
の厚さは約２μｍである。次いで、通常のリソグラフィ
とリフトオフ技術によりｐ型ＩｎＧａＡｓ層３０４上に
ｐ型電極３０８形成し、通常の蒸着法によりｎ型ＩｎＰ
基板３００の裏面にｎ型電極３０９を形成した（図６
(ｃ)）。After that, using the mask 306, p-type etching is performed by the reactive ion beam etching (RIBE) method.
-Type InGaAs layer 304, p-type InAlAs layer 303, and GaAs / AlGaAs-based multiple quantum well layer 302 were etched to form a waveguide having a vertical cross-sectional shape.
(FIG. 6 (a)). Next, TEOS (tetraethoxysilane) and O
A second insulating film 307 was deposited by the atmospheric pressure CVD method using 3 gas as a raw material, and the waveguide was buried and flattened (FIG. 6).
(b)). The second insulating film 307 on the periphery of the waveguide at this time
Has a thickness of about 2 μm. Next, a p-type electrode 308 is formed on the p-type InGaAs layer 304 by a normal lithography and lift-off technique, and an n-type InP is formed by a normal vapor deposition method.
An n-type electrode 309 was formed on the back surface of the substrate 300 (see FIG. 6).
(c)).
【００１８】本実施例ではｐ型電極３０８の一部及びパ
ッド部が厚い第２の絶縁膜（膜厚２μｍ）３０７上に形
成されるためｐ型電極３０８に起因する寄生容量が小さ
くできる。In this embodiment, a part of the p-type electrode 308 and the pad portion are formed on the thick second insulating film (film thickness 2 μm) 307, so that the parasitic capacitance due to the p-type electrode 308 can be reduced.
【００１９】また、本実施例ではマッハ・ツェンダー型
光変調器の製造に適用した例を説明したが、類似の構造
を有する導波路型デバイスにおける電極寄生容量の低減
に有効である。In addition, although the example applied to the manufacture of the Mach-Zehnder type optical modulator has been described in the present embodiment, it is effective for reducing the electrode parasitic capacitance in the waveguide type device having a similar structure.
【００２０】[0020]
【発明の効果】本発明によれば、第１の絶縁膜マスクを
具備したメサ形状或いは導波路形状の周辺を厚い第２の
絶縁膜で埋め込み自己平坦化しているため、第２の絶縁
膜上に形成された電極或いはパッド部に起因する寄生容
量を大幅に低減できる。その結果、メサ形状或いは導波
路形状を有するデバイス及びデバイスを採用したシステ
ムの高速・高性能化を図ることが可能である。また、第
２の絶縁膜により自己平坦化されたデバイス表面は引き
続く工程、特にリソグラフィ工程を容易にする。According to the present invention, since the periphery of the mesa shape or the waveguide shape having the first insulating film mask is filled with the thick second insulating film and is self-planarized, the second insulating film is formed on the second insulating film. It is possible to significantly reduce the parasitic capacitance due to the electrode or the pad portion formed on. As a result, it is possible to achieve high speed and high performance of a device having a mesa shape or a waveguide shape and a system employing the device. In addition, the device surface self-planarized by the second insulating film facilitates subsequent steps, particularly lithography steps.
【図１】本発明の実施例１の第１工程の断面図。FIG. 1 is a sectional view of a first step of Example 1 of the present invention.
【図２】本発明の実施例１の第２工程の断面図。FIG. 2 is a sectional view of a second step of the first embodiment of the present invention.
【図３】本発明の実施例２の第１工程の断面図。FIG. 3 is a sectional view of a first step of Example 2 of the present invention.
【図４】本発明の実施例２の第２工程の断面図。FIG. 4 is a sectional view of a second step of the second embodiment of the present invention.
【図５】本発明の実施例３の第１工程の断面図。FIG. 5 is a sectional view of a first step of Example 3 of the present invention.
【図６】本発明の実施例３の第２工程の断面図。FIG. 6 is a sectional view of a second step of Example 3 of the present invention.
１００…ＩｎＰ基板、１０１…ｎ型ＩｎＰ層、１０２…
低濃度ＩｎＧａＡｓ層、１０３…低濃度ＩｎＰ層、１０
４…ｐ型ＩｎＰ層、１０５…第１の絶縁膜、１０６…マ
スク、１０７…第２の絶縁膜、１０８…ｐ型電極及びパ
ッド、１０９…ｎ型電極及びパッド。100 ... InP substrate, 101 ... n type InP layer, 102 ...
Low concentration InGaAs layer, 103 ... Low concentration InP layer, 10
4 ... p-type InP layer, 105 ... first insulating film, 106 ... mask, 107 ... second insulating film, 108 ... p-type electrode and pad, 109 ... n-type electrode and pad.
Claims (5)
層を形成する工程、前記ｐ型及びｎ型を含む半導体層上
に第１の絶縁膜よりなるマスクパターンを形成する工
程、前記第１の絶縁膜よりなるマスクパターンを用いて
前記ｐ型及びｎ型を含む半導体層の少なくとも一部をエ
ッチングしてメサ形状の受光領域を形成する工程、前記
第１の絶縁膜よりなるマスクパターンと前記メサ形状の
受光領域の周辺上に珪素の有機化合物の分解酸化反応を
用いて第２の絶縁膜を形成する工程、その後、前記メサ
形状の受光領域周辺上の前記第２の絶縁膜上に電極・配
線及びパッドの一部を形成する工程を含むことを特徴と
する受光素子の製造方法。1. A step of forming a semiconductor layer containing p-type and n-type on a semiconductor substrate, a step of forming a mask pattern made of a first insulating film on the semiconductor layer containing p-type and n-type, A step of etching at least a part of the semiconductor layer containing p-type and n-type using a mask pattern made of a first insulating film to form a mesa-shaped light-receiving region; and a mask pattern made of the first insulating film And a step of forming a second insulating film on the periphery of the mesa-shaped light receiving region by using a decomposition and oxidation reaction of an organic compound of silicon, and then on the second insulating film on the periphery of the mesa-shaped light receiving region. A method of manufacturing a light-receiving element, comprising the step of forming a part of an electrode / wiring and a pad.
なるマスクパターンと前記メサ形状の受光領域の周辺上
に珪素の有機化合物の分解酸化反応を用いて前記第２の
絶縁膜を形成する工程において、珪素の有機化合物を原
料ガスとして用いた化学気相堆積法により前記第２の絶
縁膜を形成する受光素子の製造方法。2. The second insulating film according to claim 1, wherein the second insulating film is formed on the periphery of the mask pattern made of the first insulating film and the mesa-shaped light receiving region by using a decomposition and oxidation reaction of an organic compound of silicon. In the step of, the method for producing a light receiving element, wherein the second insulating film is formed by a chemical vapor deposition method using an organic compound of silicon as a source gas.
なるマスクパターンと前記メサ形状の受光領域周辺上に
珪素の有機化合物の分解酸化反応を用いて第２の絶縁膜
を形成する工程において、珪素の有機化合物及びＯ3 を
原料ガスとして用いた化学気相堆積法により前記第２の
絶縁膜を形成する受光素子の製造方法。3. The process according to claim 1, wherein the second insulating film is formed on the mask pattern made of the first insulating film and on the periphery of the mesa-shaped light receiving region by using a decomposition and oxidation reaction of an organic compound of silicon. 2. A method for manufacturing a light-receiving element, wherein the second insulating film is formed by a chemical vapor deposition method using an organic compound of silicon and O 3 as source gases.
なるマスクパターンと前記メサ形状の受光領域周辺上に
珪素の有機化合物の分解酸化反応を用いて第２の絶縁膜
を形成する工程において、前記珪素の有機化合物として
Ｓｉ(ＯＣ2Ｈ5)4 或いはＢ〔ＯＳｉ(ＣＨ)3〕3を用いた
化学気相堆積法により前記第２の絶縁膜を形成する受光
素子の製造方法。4. The process according to claim 1, wherein a second insulating film is formed on the mask pattern made of the first insulating film and on the periphery of the mesa-shaped light receiving region by using a decomposition and oxidation reaction of an organic compound of silicon. 2. A method for manufacturing a light-receiving element, wherein the second insulating film is formed by a chemical vapor deposition method using Si (OC 2 H 5 ) 4 or B [OSi (CH) 3 ] 3 as the organic compound of silicon.
ＩｎＧａＡｓ層及び低濃度ＩｎＰ層をエピタキシャル成
長する工程，前記低濃度ＩｎＰ層に対して選択的にｐ型
ドーパントの導入を行う工程，前記ｐ型ドーパントを導
入したｐ型ＩｎＰ層を含む領域上に第１の絶縁膜よりな
るマスクパターンを形成する工程，前記第１の絶縁膜よ
りなるマスクパターンを用いて前記ｐ型ＩｎＰ層の領域
周辺の前記低濃度InP層を含む半導体層をエッチングし
てメサ形状の受光領域を形成する工程，前記第１の絶縁
膜よりなるマスクパターンと前記メサ形状の受光領域の
周辺上に珪素の有機化合物の分解酸化反応を用いて第２
の絶縁膜を形成する工程、次いで、前記ｐ型ドーパント
を導入した前記低濃度ＩｎＰ層上にオーミック電極を形
成する際に前記オーミック電極の配線或いはパッド部を
前記メサ形状の受光領域の周辺上の前記第２の絶縁膜上
に形成する工程を含むことを特徴とする受光素子の製造
方法。5. A step of epitaxially growing a high-concentration n-type InP layer, a low-concentration InGaAs layer and a low-concentration InP layer on a semiconductor substrate, a step of selectively introducing a p-type dopant into the low-concentration InP layer, forming a mask pattern made of a first insulating film on a region including a p-type InP layer into which a p-type dopant is introduced, and using the mask pattern made of the first insulating film, a region around the p-type InP layer Of etching the semiconductor layer including the low-concentration InP layer to form a mesa-shaped light receiving region, a mask pattern made of the first insulating film, and an organic compound of silicon on the periphery of the mesa-shaped light receiving region. Second using decomposition oxidation reaction
The step of forming an insulating film, and then, when forming an ohmic electrode on the low-concentration InP layer into which the p-type dopant is introduced, the wiring or pad portion of the ohmic electrode is formed on the periphery of the mesa-shaped light receiving region. A method of manufacturing a light-receiving element, comprising the step of forming on the second insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6017113A JPH07226531A (en) | 1994-02-14 | 1994-02-14 | Manufacture of photodetector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6017113A JPH07226531A (en) | 1994-02-14 | 1994-02-14 | Manufacture of photodetector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07226531A true JPH07226531A (en) | 1995-08-22 |
Family
ID=11934987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6017113A Pending JPH07226531A (en) | 1994-02-14 | 1994-02-14 | Manufacture of photodetector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07226531A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6319844B1 (en) | 1999-04-09 | 2001-11-20 | Nec Corporation | Method of manufacturing semiconductor device with via holes reaching interconnect layers having different top-surface widths |
| US7307250B2 (en) | 2003-02-06 | 2007-12-11 | Seiko Epson Corporation | Light-receiving element and manufacturing method of the same, optical module and optical transmitting device |
-
1994
- 1994-02-14 JP JP6017113A patent/JPH07226531A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6319844B1 (en) | 1999-04-09 | 2001-11-20 | Nec Corporation | Method of manufacturing semiconductor device with via holes reaching interconnect layers having different top-surface widths |
| US7307250B2 (en) | 2003-02-06 | 2007-12-11 | Seiko Epson Corporation | Light-receiving element and manufacturing method of the same, optical module and optical transmitting device |
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