JPH07226506A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the generation of the operation delay of an insulated-gate type semiconductor device, which is miniaturized, by a method wherein the gap parts between source and drain electrodes and a first field oxide film are filled with a second field oxide film. CONSTITUTION:n<+> source and drain regions 8S and 8D, which respectively come into contact to the bottoms, of source and drain electrodes 7S and 7D formed by a solid-phase diffusion of impurities from the electrodes 7S and 7D and self-align, are provided in a p-type Si substrate 1 directly under the electrodes 7S and 7D. Moreover, the peripheries of the electrodes 7S and 7D are covered with a second field SiO2 film 9 formed on an element region 2 and a silicified layer 10 consisting of TiSi2 is formed on the surface parts of the electrodes 7S and 7D. Thereby, an interfacial area between the regions 8S and 8D is reduced and a sheet resistivity of each of the regions 8S and 8D is also reduced. As a result, the operation delay of an insulated-gate type semiconductor device is also never actualized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing method, and more particularly to an insulated gate type semiconductor device and its manufacturing method.

Insulated gate type semiconductor devices such as MOSF
In ET, deterioration of element performance due to parasitic capacitance and parasitic resistance has become a problem due to miniaturization of elements due to high integration, and development of a technique for reducing parasitic capacitance and parasitic resistance is desired. .

[0003]

2. Description of the Related Art In miniaturized MOSFETs,
The source and drain junctions are becoming shallower in order to suppress degradation of device performance due to the short channel effect.

For this reason, the sheet resistance of the source and drain regions increases and the operating speed decreases. Conventionally, the source / drain regions are lined with a silicide (the surface of the source / drain regions) as a means for preventing the decrease in the operating speed. In general, a silicide layer is formed on the substrate) to suppress an increase in the sheet resistance value of the source / drain regions.

FIG. 6 shows such a MOSFET.
FIG. In the figure, 51 is, for example, p-type silicon
(Si) substrate, 52 is element region, 53 is field silicon oxide
(SiO ₂ ) film, 54 a gate SiO ₂ film, 55 a gate electrode made of poly-Si or polycide, 56S a low concentration (n ⁻ type) source region, 56D a low concentration (n ⁻ type) drain region, 57 Is an insulating film sidewall, 58S is a high-concentration (n ⁺ type) source region, 58D is a high-concentration (n ⁺ type) drain region, 59 is a silicidation layer made of, for example, titanium silicide (TiSi ₂ ), 60
Is an interlayer insulating film, 61S is a source contact window, 61D is a drain contact window, 62S is a source electrode wiring, and 62D is a drain electrode wiring.

[0006]

A silicide layer is formed on the surface of the source and drain regions 58S and 58D as shown in FIG.
In the conventional structure for forming 59, when the junction between the source and drain regions 58S and 58D becomes thinner, the silicidation of the surface of the source and drain regions 58S and 58D breaks through the junction and the device characteristics deteriorate. In addition, the silicide layer 59 is thinned to prevent the junction breakdown, and the sheet resistance of the source / drain regions 58S and 58D cannot be sufficiently reduced, which causes a delay in the operation of the device.

Further, the contact between the source / drain regions 58S and 58D and the electrode wirings 62S and 62D (contact window 61S).
, 61D) is taken on top of these regions, the area of the source / drain regions 58S, 58D becomes large, and the operating speed decreases due to the increase in the junction capacitance, resulting in especially high integration and large scale. There is also a problem that the junction capacitance is further increased and the influence on the operation delay is further increased along with the purpose of suppressing an increase in power consumption accompanying it and the lowering of the power supply voltage for the purpose of battery operation.

Therefore, the present invention provides a structure of an insulated gate semiconductor device capable of forming the source and drain regions shallow and having a small junction area and reducing the sheet resistance of the source and drain regions, and a method of manufacturing the same. Offer to,
It is an object of the present invention to prevent an operation delay of a miniaturized insulated gate semiconductor device.

[0009]

A solution to the above problems is an insulated gate type semiconductor device, in which a gate insulating film is provided on an element region defined by a first field oxide film of a one conductivity type semiconductor substrate. Of the gate electrode, the side wall-shaped portion of which the bottom surface is in contact with the surface of the semiconductor substrate, and the side wall-shaped portion of the side surface of the gate electrode which contacts the both sides of the gate electrode in the gate length direction with an insulating film interposed therebetween. A source electrode and a drain electrode of opposite conductivity type silicon having an electrode lead-out portion which is integral with the sidewall-shaped portion and extends from a part of the bottom surface to the semiconductor substrate surface and extends above the element region; A source and drain region of opposite conductivity type formed in contact with and aligned with the bottom surface of the source and drain electrodes in the semiconductor substrate immediately below the drain electrode, and A semiconductor device according to the present invention, wherein the gap between the rain electrode and the first field oxide film is filled with a second field oxide film, or the semiconductor device, further comprising the gate electrode, the source electrode and the drain. A semiconductor device according to the present invention in which a silicidation layer is formed on the surface of an electrode, or a gate insulating film is formed on an element region defined by a first field oxide film of a one conductivity type semiconductor substrate, and then the gate is formed. On the insulating film,
Forming a gate electrode made of silicon and having a first oxidation resistant film on its upper surface, then forming insulating film sidewalls on both side surfaces of the gate electrode so as to cover respective side surfaces, and then the semiconductor substrate After forming a second silicon film and a second oxidation resistant film in this order on the semiconductor substrate, the second oxidation resistant film and the second silicon film are collectively etched to select the element region on the semiconductor substrate. Step of forming a second silicon film pattern having a second oxidation resistant film on the upper surface of the mask material pattern, and then using a mask material pattern having a pattern shape corresponding to the lead-out portions of the source and drain electrodes. Of the oxidation resistant film and the second silicon film pattern thereunder are collectively etched, and are deposited on both side surfaces of the gate electrode in a sidewall shape through the insulating film sidewall, and the bottom surface is The sidewall-shaped portions of the source and drain electrodes made of the second silicon which are in contact with the surface of the conductor substrate, and the bottom surface of the sidewall of the element region that is in contact with the semiconductor substrate surface and is exposed above the element region from a part of the sidewall-shaped portions. A step of forming an electrode lead-out portion of the source and drain electrodes made of the second silicon having a second oxidation resistant film, and then forming a side surface of the side wall-like portion of the source and drain electrode and a side surface of the electrode lead-out portion. 3 step of forming an oxidation resistant film side wall, selective oxidation is performed by using the first oxidation resistant film, the second oxidation resistant film and the third oxidation resistant film sidewall as a mask, and the source and drain electrodes of The semiconductor according to the present invention, which has a step of forming a second field oxide film on the surface of the semiconductor substrate exposed between the sidewall-shaped portion and the electrode lead-out portion and the first field oxide film. A method of manufacturing of the device,
Alternatively, in the method of manufacturing a semiconductor device described above, after the step of forming the second field oxide film, the sidewall-shaped portions of the source and drain electrodes and the first and second field oxide films are used as masks. A step of ion-implanting an impurity of opposite conductivity type into the electrode lead-out portion, and the ion-implanted impurity is redistributed in the source and drain electrodes by heat treatment, and solid-phase diffused in the semiconductor substrate to directly under the source and drain electrodes. A method of manufacturing a semiconductor device according to the present invention, comprising the step of forming source and drain regions of opposite conductivity type self-aligned with the bottom surface of the source and drain electrodes on the surface of a semiconductor substrate, or a method of manufacturing the semiconductor device, After forming the second field oxide film, the first, second oxidation resistant film and the third oxidation resistant film sidewall are removed. Exposing the surface of the source and drain electrodes, then depositing a refractory metal film on the source and drain electrodes, and then performing heat treatment to selectively expose the surface portions of the source and drain electrodes. This is achieved by the method for manufacturing a semiconductor device according to the present invention, which has a step of silicidation.

[0010]

The principle of the present invention will be described below with reference to FIG.
As shown in the figure, in the insulated gate semiconductor device according to the present invention, the source electrode 7S and the drain electrode 7D made of polycrystalline Si have the minimum required wiring contact parts (electrode lead-out parts) 7Sc, 7Dc. Is formed along the side surface of the gate electrode 5 in the gate length direction with a very narrow contact area with the semiconductor substrate (Si substrate) 1 in a sidewall shape (7Ss, 7Ds is a sidewall portion) through the insulating film sidewall 6. To be done. Then, the source region 8S and the drain region 8D are separated into the source electrode 7S and the drain electrode 7D in the semiconductor substrate 1 immediately below the source electrode 7S and the drain electrode 7D by solid phase diffusion of impurities from the source electrode 7S and the drain electrode 7D. Since it is self-aligned with the bottom surface and formed along the channel region 13 with a very small junction area, the junction capacitance can be made extremely small.

Further, according to the present invention, the source electrode 7S and the drain electrode 7D are surrounded by a second electrode which is defined around the second electrode.
The field insulating film 9 is provided, which makes it possible to selectively silicify the surface portions of the source electrode 7S and the drain electrode 7D (10 is a silicidation layer). Then, by forming the silicidation layer 10 on the surface portions of the source electrode 7S and the drain electrode 7D, the source electrode 7S and the drain electrode 7D are formed into the narrow sidewall shape (7Ss and 7Ds are the sidewall portions) as described above. Even if formed to be long, a sufficiently low wiring resistance of the electrodes, that is, sheet resistance of the source and drain regions 8S and 8D immediately thereunder can be obtained.

Therefore, according to the present invention, an insulated gate semiconductor device having an extremely small junction capacitance and a small operating resistance can be formed, and the insulated gate semiconductor element is miniaturized to form a shallow source / drain junction. The operation delay of the LSI or the like is prevented.

[0013]

EXAMPLES The present invention will be described in detail below with reference to illustrated examples. FIG. 1 is a schematic view of an embodiment of a semiconductor device according to the present invention. (A) is a plan view, (b) is a sectional view taken along line AA ', (c) is a sectional view taken along line BB', (d). Is a sectional view taken along line CC ′. Also,
2 and 3 are process plan views of an embodiment of a method of manufacturing a semiconductor device according to the present invention, and FIGS. 4 and 5 are process cross-sectional views corresponding to the process plan views. The same object is denoted by the same reference numeral throughout the drawings.

MOSFE which is a semiconductor device according to the present invention
In FIG. 1 showing one embodiment of T, 1 is a p-type Si substrate, 2
Is an element region, 3 is a first field SiO ₂ film, 4 is a gate
SiO ₂ film, 5 is an n ⁺ -type polycrystalline Si gate electrode, 5c is a wiring contact portion of the electrode, 6 is a SiO ₂ film sidewall, and 7S is n
⁺ Type polycrystalline Si source electrode, 7Ss is the side wall portion of the electrode, 7Sc is the electrode lead-out portion of the electrode, 7D is n ⁺ type polycrystalline Si drain electrode, 7Ds is the side wall portion of the electrode, and 7Dc is An electrode lead-out portion of the same electrode, 8S is an n ⁺ type source region, 8D is an n ⁺ type drain region, and 9 is a second field Si.
An O ₂ film, 10 is a silicidation layer (TiSi ₂ layer), 11 is an interlayer insulating film, and 12G, 12S, and 12D are wiring contact windows.

As shown in this figure, the MOSFET according to the present invention
In the first field Si of the p-type Si substrate 1,
On the device region 2 defined by the O ₂ film 3, the gate Si is normally formed.
For example, an n ⁺ -type polycrystalline Si gate electrode 5 is provided so as to extend across the same element region 2 via the O ₂ film. Then, the bottom surface is exposed to the element region 2 on both side surfaces of the gate electrode 5 in the gate length direction along the extending direction of the gate electrode 5 via the SiO ₂ film sidewall 6 which is an insulating film. Source n ⁺ type polycrystalline Si source electrode 7S in direct contact with the surface of Si substrate 7S
And the sidewall-shaped portions 7Ss and 7Ds of the n ⁺ -type polycrystalline Si drain electrode 7D are provided, and the sidewall-shaped portions 7Ss and
The source electrode 7S and the drain electrode 7D which have a minimum area necessary for wiring contact in a part of 7Ds, and whose bottom surface is in direct contact with the surface of the Si substrate 1 are integrally formed with the sidewall-shaped portions 7Ss and 7Ds. The electrode lead-out portions 7Sc and 7Dc are provided in the element region 2.

Further, the source electrode 7S and the drain electrode 7D
In the p-type Si substrate 1 immediately below, an n ⁺ -type source which is formed by solid phase diffusion of impurities from the source electrode 7S and the drain electrode 7D and is in contact with the bottom surfaces of the source electrode and the drain electrode and which is self-aligned A second field SiO ₂ film 9 having a region 8S and a drain region 8D, and the periphery of the source electrode 7S and the drain electrode 7D is selectively formed on the device region 2.
Covered by the above source electrode 7S and drain electrode 7D
Has a structure in which a silicidation layer 10 made of, for example, TiSi ₂ is formed on the surface of the.

In the MOSFET having such a structure, the gate width (channel width) is formed along the gate electrode 5 in a self-aligned manner with the sidewall-shaped portions 7Ss and 7Ds of the source and drain electrodes 7S and 7D. Source regions 8S and 8D immediately below the sidewall-shaped portions 7Ss and 7Ds
Since a large current drivability can be obtained because of the large current holding capacity, the junction area of the source and drain regions 8S and 8D is also greatly reduced, so that the problem of operation delay due to the junction capacitance is greatly reduced. Further, in the structure of the present invention, as shown in the figure, the source and drain electrodes 7S and 7D are formed long by the thin sidewall-shaped portions 7Ss and 7Ds, but the silicided layer is formed on the surface portions of these electrodes 7S and 7D. Since the sheet resistance of the source and drain regions 8S and 8D is also reduced by forming 10 and the lining of the low resistance wiring, the operation delay due to the increase of the operation resistance is not actualized.

The M according to the present invention which produces the above effects
The OSFET is manufactured, for example, by a process such as one embodiment described below with reference to the process plan views of FIGS. 2 and 3 and the process sectional views of FIGS.

2 (a) and 4 (a) That is, as usual, for example, the first region for defining the element region 2 of a predetermined area is defined on the surface of the p-type Si substrate 1 by the selective oxidation means (LOCOS method). A field SiO ₂ film 3 is formed, and then a gate SiO ₂ film 4 having a thickness of, for example, about 80 Å is formed on the element region 2 by thermal oxidation, and then chemical vapor deposition (CVD) is performed on this substrate.
A first polycrystalline Si film having a thickness of, for example, about 2000 Å is formed by means, and then an n-type impurity is introduced to this first polycrystalline Si film at a high concentration to impart conductivity, and then the first polycrystalline Si film is formed. A first silicon nitride (Si ₃ N ₄ ) film 13 having a thickness of about 1000 Å which is a first oxidation resistant film is formed on the polycrystalline Si film of No. 1 by CVD means, and then an ordinary photolithography means and anisotropy are used. by collectively patterning the first Si ₃ N ₄ film 13 and the first polycrystalline Si film by using a reactive ion etching (RIE) process is a dry etching means, through the gate SiO ₂ film 4 A polycrystalline Si gate electrode 5 having a first Si ₃ N ₄ film 13 is formed on the device region 2 so as to cross the device region 2. In the RIE process, a fluorine (F) -based gas such as carbon tetrafluoride (CF ₄ ) is used for the Si ₃ N ₄ film, and carbon tetrachloride (CCl ₄ ) is used for the polycrystalline Si. ) Chlorine
A (Cl) -based gas is used as an etching gas.

2 (b) and 4 (b). Then, a thickness of, for example, 1000 is formed on the substrate by CVD means.
A SiO ₂ film of about Å is deposited, and then the entire surface is etched by the RIE process using F-based gas such as methane trifluoride (CHF ₃ ) as an etching gas, and the gate electrode 5 and the first Si on the upper surface thereof are etched. 1000 N Å selectively on the side of ₃ N ₄ membrane 13
The SiO ₂ film side wall 6 having a thickness of about 5 is left. The gate SiO ₂ film 4 exposed in the RIE process is completely removed.

2 (c) and 4 (c). Then, a CVD method is performed to form a film having a thickness of 2000, for example.
A non-doped second polycrystalline Si film having a thickness of about Å is formed, and then a second Si ₃ N ₄ film having a thickness of about 1000 Å that serves as a second oxidation-resistant mask is formed on the second Si ₃ N ₄ film. The Si ₃ N ₄ film and the second polycrystalline Si film are collectively patterned by anisotropic and isotropic etching means through the same mask to selectively cover the upper part of the device region 2 and to form the second Si ₃ N ₄ film 16
A second polycrystalline Si film pattern 15 having is formed. Here, by using the isotropic etching means, the second polycrystalline Si film deposited on the outside of the element region 2 is completely removed without leaving a sidewall-like residue in the step portion.

A wet etching method, for example, is used as the isotropic etching means, a phosphoric acid (HPO ₄ ) boiling method is used for etching the second Si ₃ N ₄ film, and a second polycrystalline Si film is used. For the etching, the immersion etching method using a fluorinated nitric acid-based solution is used.

Referring to FIGS. 2D and 4D, the second Si ₃ N ₄ film 16 is then aligned with another mask.
For example, the second Si ₃ N ₄ film is selectively patterned on the second polycrystalline Si film pattern 15 by dry etching using F 2 gas to selectively cover the regions corresponding to the electrode lead-out portions of the source and drain. Patterns 16S and 16D are formed.

2 (e) and 4 (e). Then, using the second Si ₃ N ₄ film patterns 16S and 16P as a mask, a RIE process using a Cl-based gas is performed to perform a second polycrystalline Si process. The exposed portion of the film pattern 15 is selectively removed by etching, and the gate electrode 5 having the SiO ₂ film sidewall 6 is formed.
Second polycrystalline Si sidewalls 15Ss and 15Ds having a thickness of about 2000 Å are formed on both side surfaces of the second Si ₃ N layer.
The electrode lead-out portions 15Sc and 15Dc integrated with the respective Si sidewalls are left under the _four film patterns 16S and 16P.

3 (a) and 5 (a), a third Si ₃ N ₄ film having a thickness of about 1000Å which is an oxidation resistant film is formed on the substrate by the CVD method, and then this third film is formed. Si ₃ N ₄ film is completely etched by RIE treatment with F type gas, and the second polycrystalline Si side wall 15Ss,
A third Si ₃ N ₄ film sidewall 17 is left on the surface of 15Ds and the side surfaces of the electrode lead-out portions 15Sc and 15Dc.
_{A 3} N ₄ film sidewall 17 covers those surfaces.

3B and 5B, the first Si ₃ N ₄ film 13, the second Si ₃ N ₄ film patterns 16S and 16P, and the third Si ₃ N ₄ film side are then formed. Si substrate exposed around the second polycrystalline Si sidewalls 15Ss, 15Ds and the second polycrystalline Si electrode lead-out portions 15Sc, 15Dc in the element region 2 by performing selective oxidation using the wall 17 as a mask. A second field SiO ₂ film 9 is formed on one surface.

Next, referring to FIGS. 3C and 5C, the second field SiO ₂ film 9 is used as a mask to cover the surface of the element region 2 and the second polysilicon side wall 15Ss,
For example, n-type impurities such as arsenic (As) are selectively ion-implanted into the 15Ds and the electrode lead-out portions 15Sc, 15Dc at a high dose of about 1.0 × 10 ¹⁵ cm ^-2 , and then the arsenic is heated at a temperature of about 950 ° C. Activated polycrystalline Si sidewalls 15Ss, 15Ds and the electrode lead-out portions 15Sc, 15Dc are uniformly redistributed, and the sidewalls 15Ss, 15Ds and electrode lead-out portions 15Sc, 15Dc are solid-phase diffused in the substrate immediately below, It is in contact with the bottom surface of the side wall and the electrode lead-out portion and self-aligns, for example, 1000Å
Shallow n ⁺ type source region 8S and n ⁺ type drain region
Form 8D.

By this step, the polycrystalline Si sidewalls 15Ss, 15Ds and the electrode lead-out portions 15Sc, 15Dc are made conductive and the source electrode 7S and the sidewall-like portion 7Ss and the electrode lead-out portion 7Sc are provided. The drain electrode 7D is composed of 7Ds and the electrode lead-out portion 7Dc.

In the above-mentioned ion implantation, As is also implanted into the gate electrode 5, but this does not matter since it has the effect of further reducing the wiring resistance of the gate electrode 5. See FIG. 3 (d) and FIG. 5 (d) Next, the source electrode 7S and the drain electrode made of polycrystalline Si
After removing the third Si ₃ N ₄ film side wall 17 that covers the surface of 7D and the first Si ₃ N ₄ film 13 that covers the upper surface of the gate electrode 5 by dry etching using CF ₄ or the like or phosphoric acid boiling treatment , A thickness of 5
A titanium (Ti) film of about 00Å is deposited, and then, for example, nitrogen (N)
₂ ) Anneal at 800 ℃ for 30sec in the above Ti
The thickness (depth) 600 to 70 is selectively applied to the surface portions of the source electrode 7S and the drain electrode 7D and the upper surface portion of the gate electrode 5 which are in contact with the film.
A silicidation layer (TiSi ₂ layer) 10 of about 0 Å is formed, and then, for example, ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ) and water.
The unreacted Ti film that did not contribute to silicidation was selectively removed by wet etching with a mixed solution of (H ₂ O), and as shown in the figure, the side formed especially along the side surface of the gate electrode 5. It consists of the wall-shaped part 7Ss and the electrode lead-out part 7Sc from part of it, and the thickness (depth) of the surface is 600 to 70.
A polycrystalline Si source electrode 7S having a silicidation layer 10 made of TiSi _{2 of} about 0 Å, a sidewall-like portion 7Ds formed along the side surface of the gate electrode 5 on the side opposite to the above, and an electrode from a part thereof It has a polycrystalline Si source electrode 7D having a silicided layer 10 made of TiSi ₂ and having a thickness (depth) of about 600 to 700 Å on the surface made up of the lead-out portion 7Dc. The source electrode 7S and the drain electrode 7D are directly underneath. The p-type Si substrate 1 has a shallow n ⁺ -type source region 8S and a drain region 8D which are in ohmic contact with the source electrode 7S and the drain electrode 7D and self-align with the bottom surfaces of the source electrode 7S and the drain electrode 7D, respectively. A MOSFET is formed.

In the above manufacturing method, when the surface portions of the polycrystalline Si source electrode and drain electrode are silicided, refractory metals such as chromium, tungsten and tantalum are used in addition to titanium.

Then, as shown in FIG. 1, thereafter, an interlayer insulating film 11 is formed on the substrate as usual, and contact windows 12G, 12S, 12D to the respective electrodes are formed.
Etc., and the contact 12G is formed on the interlayer insulating film 11.
, 12S, 12D, etc., gate electrode 5 and source electrode 7
A wiring such as aluminum (not shown) connected to the S and drain electrodes 7D and the like is formed, and the MOS type semiconductor device according to the present invention is completed.

The MOSFET according to the present invention manufactured by the method according to the present invention as shown in the above embodiment has the source region 8S and the drain region as described above with reference to FIG.
8D is self-aligned with the sidewall-shaped portions 7Ss and 7Ds of the source and drain electrodes 7S and 7D and is formed long along the gate electrode 5, so that the total area of the source and drain regions 8S and 8D, that is, the total junction area is A large channel width is obtained despite a significant reduction. Therefore, it is possible to significantly reduce the delay of the element operation by reducing the parasitic capacitance while maintaining the large current driving capability. In addition, the shallow source region 8S and drain region 8D are formed along the gate electrode 5 to be elongated as described above.
And a silicide layer on the surface on the drain region 8D.
The sidewall-shaped portions 7Ss and 7Ds of the source electrode 7S and the drain electrode 7D, which have a low resistance with 10, are provided, and the source-drain regions 8S and 8D are lined by these sidewall-shaped portions. Because it becomes a structure,
The sheet resistance of the source and drain regions 8S and 8D does not increase, and the operation delay due to the increase of the sheet resistance is avoided.

[0033]

As described above, according to the present invention, the junction capacitance of the source and drain regions can be increased without decreasing the current driving capability of the miniaturized insulated gate semiconductor device and increasing the sheet resistance. Can be significantly reduced.

Therefore, the present invention largely contributes to the miniaturization of LSIs and the like, and the reduction of the driving ability of the highly integrated insulated gate semiconductor device and the prevention of the operation delay due to the parasitic capacitance.

[Brief description of drawings]

FIG. 1 is a schematic diagram of an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a process plan view (1) of an embodiment of a manufacturing method according to the present invention.

FIG. 3 is a process plan view of an embodiment of a manufacturing method according to the present invention (No. 2)

FIG. 4 is a process sectional view (1) of an embodiment of a manufacturing method according to the present invention.

FIG. 5 is a process sectional view of an example of the manufacturing method according to the present invention (No. 2)

FIG. 6 is a schematic sectional view of a conventional MOSFET.

[Explanation of symbols]

1 p-type Si substrate 2 element region 3 first field SiO ₂ film 4 gate SiO ₂ film 5 n ⁺ type polycrystalline Si gate electrode 5C gate electrode wiring contact 6 SiO ₂ film side wall 7S n ⁺ type polycrystalline Si Source electrode 7Ss Source electrode sidewall portion 7Sc Source electrode electrode lead portion 7D n ⁺ type polycrystalline Si drain electrode 7Ds Drain electrode sidewall portion 7Dc Drain electrode electrode lead portion 8S n ⁺ type source region 8D n ⁺ Type drain region 9 Second field SiO ₂ film 10 Silicide layer (TiSi ₂ layer) 11 Interlayer insulating film 12G, 12S, 12D Wiring contact window

Claims (5)

[Claims] 1. An insulated gate semiconductor device, comprising: a first field oxide film (3) of a one conductivity type semiconductor substrate (1).
A gate electrode (5) provided on the device region (2) defined by the gate insulating film (4), and an insulating film (5) on each side of the gate electrode (5) in the gate length direction. 6) the semiconductor substrate (1)
The side wall-like portion (7Ss, 7Ds) in contact with the surface, and the bottom surface from a part of the side wall-like portion (7Ss, 7Ds) are in contact with the surface of the semiconductor substrate (1) and extend onto the element region (2). Source electrode (7S) and drain electrode (7D) of opposite conductivity type having electrode lead-out portions (7Sc, 7Dc) integrated with the sidewall-shaped portions (7Ss, 7Ds), and the source and drain electrodes (7D). 7S, 7D) a source and drain region (8S, 8D) of opposite conductivity type formed in contact with and aligned with the bottom surface of the source and drain electrodes (7S, 7D) in the semiconductor substrate (1) immediately below. A semiconductor characterized in that the gap between the first source and drain electrodes (7S, 7D) and the first field oxide film (3) is filled with the second field oxide film (9). apparatus. 2. The semiconductor device according to claim 1, wherein a silicidation layer (10) is formed on the surfaces of the gate electrode (5), the source electrode (7S) and the drain electrode (7D). 3. A gate insulating film is formed on a device region defined by a first field oxide film of a one-conductivity-type semiconductor substrate, and then a first silicon film is formed on the gate insulating film and is made of a first silicon. Forming a gate electrode having an oxidation resistant film, then forming insulating film sidewalls on both side surfaces of the gate electrode so as to cover respective side surfaces, and then forming a second silicon film on the semiconductor substrate. After the second oxidation resistant film is sequentially formed, the second oxidation resistant film and the second silicon film are collectively etched to selectively cover the element region on the semiconductor substrate and to form the second upper film on the semiconductor substrate. A step of forming a second silicon film pattern having an oxidation resistant film, and a second mask film pattern having a pattern shape corresponding to the lead-out portions of the source and drain electrodes.
The oxidation resistant film and the second silicon film pattern thereunder are collectively etched, and are deposited on both side surfaces of the gate electrode in a sidewall shape through the insulating film sidewalls, and the bottom surface is the semiconductor substrate surface. Second sidewalls of the source and drain electrodes that are in contact with the second silicon, and second sidewalls of the sidewalls of the sidewalls that are in contact with the semiconductor substrate surface and have a second acid resistance A step of forming an electrode lead-out portion of the source and drain electrodes made of the second silicon having an oxide film, and then a third acid-resistant layer on the surface of the sidewall-like portion of the source and drain electrodes and the side surface of the electrode lead-out portion. A step of forming an oxide film side wall, selective oxidation is performed using the first oxidation resistant film, the second oxidation resistant film and the third oxidation resistant film sidewall as a mask, Manufacture of a semiconductor device, comprising a step of forming a second field oxide film on a semiconductor substrate surface exposed between the first field oxide film and the sidewall-shaped part of the drain electrode and the electrode extraction part. Method. 4. The method of manufacturing a semiconductor device according to claim 3, wherein after the step of forming the second field oxide film, the first and second field oxide films are used as masks and the source and A step of ion-implanting an impurity of opposite conductivity type into the sidewall-shaped part of the drain electrode and the electrode lead-out part, redistribute the ion-implanted impurity into the source and drain electrodes by heat treatment, and perform solid phase diffusion into the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: forming a source / drain region of opposite conductivity type self-aligning with a bottom surface of the source / drain electrode on a surface of the semiconductor substrate immediately below the source / drain electrode. 5. The method of manufacturing a semiconductor device according to claim 3, wherein after forming the second field oxide film, the first,
A step of removing the second oxidation resistant film and the third oxidation resistant film side wall to expose the surfaces of the source electrode and the drain electrode, and then depositing a refractory metal film on the source and drain electrodes, and A method of manufacturing a semiconductor device, comprising a step of performing heat treatment to selectively silicify the surface portions of the source electrode and the drain electrode.