JPH07226409A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a MESFET provided with a T-shaped gate electrode which has its excellent processability and less variation and deterioration in its electric characteristic. CONSTITUTION:In a silicon oxide film 111a formed on the surface of an operation layer 102, an opening part 121a is formed, and a silicon nitride film 131 is formed extensively. By the etching-back of the same through an anisotropic etching, a sidewall spacer 131a comprising the silicon nitride film 131 is formed, and after the formation of a gate electrode 151a, the silicon oxide film 111a is removed selectively by a wet etching.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a gate electrode of MESFET.

[0002]

2. Description of the Related Art In recent years, due to higher frequency of MESFET,
There is a demand for a high-performance and highly reliable gate electrode with a short gate length and reduced parasitic capacitance. MESFE
Referring to FIG. 5, which is a cross-sectional view of the manufacturing process of T, the T-shaped (or Y-shaped) gate electrode of the conventional MESFET is manufactured by the following method.

First, an operating layer 202 made of n-type GaAs is formed on the surface of a GaAs substrate 201 by an epitaxial growth method or the like. Subsequently, a silicon oxide film 211 that covers the entire surface of the operating layer 202 is formed by the CVD method. An opening 221 is formed in the silicon oxide film 211 by using a known photolithography technique and a known dry etching technique [FIG. 5 (a)]. next,
The second silicon oxide film 23 is formed on the entire surface by the CVD method again.
1 is formed [FIG. 5 (b)]. This silicon oxide film 2
31 is etched back by anisotropic etching to form a sidewall spacer 231a made of a second silicon oxide film on the sidewall of the opening 221 [FIG.
(C)]. Next, a tungsten silicide film and a gold film are sequentially formed on the entire surface. The tungsten silicide film is
It is provided to form a Schottky junction with the GaAs substrate 201. The gold film is provided to reduce wiring resistance. The gold film and the tungsten silicide film are patterned by using a known photolithography technique and a known dry etching technique, and a T-shaped (or Y-shaped) gate electrode 251 including the gold film 242 and the tungsten silicide film 241 is formed. Are formed [Fig. 5
(D)]. After that, the silicon oxide film 211 including the sidewall spacers 231a is entirely removed for the purpose of preventing the deterioration of reliability due to the interfacial reaction between the silicon oxide film and the operating layer 202 and reducing the gate capacitance [FIG. 5
(E)].

[0004]

DISCLOSURE OF THE INVENTION The above-mentioned conventional MESF
In the ET manufacturing method, the silicon oxide film 211 and the sidewall spacers 231a are removed by a hydrofluoric acid-based etchant. There are two problems associated with this process.

The first problem is related to the electrical characteristics of the MESFET. At this time, depending on the composition ratio of the tungsten silicide film 241, this tungsten silicide film 241 is etched by hydrofluoric acid. If this etching occurs only in the eaves portion or the side wall portion of the gate electrode 251, the electrical characteristics of the MESFET are not significantly affected. G
When this etching occurs at the portion where the aAs substrate 201 and the gate electrode 251 are in direct contact with each other, the gate length at that portion is locally short, and the electrical characteristics vary.
And it will deteriorate.

The second problem relates to the workability of the gate electrode. The T-shaped (or Y-shaped) gate electrode 251 is required to reduce the resistance value of the gate electrode 251 even though the gate length is extremely short. From this, the width of the tungsten silicide film 241 at the portion where the GaAs substrate 201 and the gate electrode 251 are in direct contact is extremely short. The entire gate electrode 251 is supported by this portion. As a result, at the stage of the structure shown in FIG. 5E, the gate electrode 251 is easily broken or peeled off.

Therefore, an object of the present invention is to provide a method of manufacturing a MESFET having a T-shaped (or Y-shaped) gate electrode which is excellent in workability, has less variation in electrical characteristics, and has less deterioration in electrical characteristics. To provide.

[0008]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming an insulating film on a surface of a compound semiconductor substrate having an operation layer provided in a predetermined region, and a predetermined width. A step of forming an opening in the insulating film that reaches at least a region including the gate electrode formation planned region on the surface of the compound semiconductor substrate, and depositing a thin film on the surface of the compound semiconductor substrate including the insulating film. And a step of forming a sidewall spacer made of the thin film on the sidewall of the opening by an etchback method using anisotropic etching, and at least on the surface of the compound semiconductor substrate including the insulating film. The step of forming a metal film whose bottom layer is a refractory metal silicide film and the patterning of the metal film have a width wider than the predetermined width and the opening Forming a gate electrode covering the, by isotropic etching, characterized in that a step of selectively removing the insulating film.

Preferably, the insulating film is a silicon nitride film and the thin film is a silicon oxide film. Alternatively,
The insulating film is a silicon oxide film, and the thin film is one of a silicon nitride film, an amorphous silicon film, a polycrystalline silicon film, and a refractory metal film.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 which is a cross-sectional view of the manufacturing process of the MESFET, the first embodiment of the present invention is as follows.

First, a GaAs substrate 1 which is a semi-insulating substrate.
01 surface, n-type GaA by epitaxial growth method
The s layer is formed. By ion implantation of boron or the like, the n-type GaAs layer in a region other than a predetermined region is converted to semi-insulating, and the operating layer 102 made of this n-type GaAs layer is left in the predetermined region. Subsequently, this operation layer 10
The silicon oxide film 111a having a film thickness of about 500 nm (which is an insulating film) covering the entire surface of 2 is formed by low pressure vapor deposition (LPCV).
D) method. This silicon oxide film 101a
Then, the opening 121a is formed by using a known photolithography technique and a known dry etching technique. The (opening) width at the portion of the opening 121a reaching the operation layer 102 is, for example, 0.5 μm (predetermined width).
When the opening 121a is formed, for example, if anisotropic plasma etching is performed after performing isotropic etching (wet or dry etching), the (opening) width of the upper end of the opening 121a is larger than the predetermined width. It becomes wider [Fig. 1 (a)]. The opening 121a is also formed in a region in which the n-type GaAs layer is converted to semi-insulating. The (opening) width of the opening 121a in this region is
It is preferable to set the width wider than the predetermined width.

Next, a (thin film) silicon nitride film 131 is formed on the entire surface by a method such as sputtering (or plasma-enhanced chemical vapor deposition (PECVD)). The thickness of the silicon nitride film 131 is about 200 nm on the upper surface of the silicon oxide film 111a, and the opening 1
It is about 120 nm on the side wall of 21a (in the case of PECVD, the film thicknesses of both are almost equal) [FIG.
(B)]. Silicon nitride film 1 on the side wall of the opening 121a
The film thickness of 31 is smaller than 1/2 of the predetermined width of the opening 121a. T obtained by this embodiment
The gate length of the V-shaped (or Y-shaped) gate electrode is determined by the predetermined width of the opening 121a and the film thickness of the silicon nitride film 131.

Subsequently, the silicon nitride film 131 is etched back by known anisotropic etching to form sidewall spacers 131a made of a silicon nitride film. The width of the sidewall spacer 131a is approximately equal to the film thickness of the silicon nitride film 131 (1
20 nm) (FIG. 1 (c)).

Next, 1 is formed on the entire surface by a method such as sputtering.
A tungsten silicide film having a thickness of about 00 nm is formed, and a gold film having a thickness of about 400 nm is further formed by a method such as a plating method. The tungsten silicide film is
It is provided to form a Schottky junction with the operating layer 102. The gold film is provided to reduce wiring resistance. The gold film and the tungsten silicide film are sequentially patterned by using the well-known photolithography technique and the well-known dry etching technique to form a gate electrode 151a composed of (a laminated film) of the tungsten silicide film 141a and the gold film 142a. . The width of the gate electrode 151a is a predetermined width of the opening 121a (and the opening 121a).
The width of the gate electrode 151a is wider than the upper end of the gate electrode 151a, and the gate electrode 151a completely covers the opening 121a. Therefore, in the region that covers the opening 121a in the portion reaching the operation layer 102 (the region where the gate electrode 121a functions as the gate electrode itself, not as a simple wiring), the cross-sectional shape of the gate electrode 121a is T-shaped. (Or Y-shaped) [Fig. 1 (d)].

Subsequently, the silicon oxide film 111a is selectively removed by wet etching with buffered hydrofluoric acid. The etching rate of the silicon nitride film by the buffered hydrofluoric acid is lower than 1/10 of that of the silicon oxide film 111a in the case of the above-mentioned sputtering, although it depends on the manufacturing method. Therefore, in this wet etching, the sidewall spacers 131a made of the silicon nitride film are etched by at most about 50 nm.
This width does not become thinner than about 70 nm. Therefore, the tungsten silicide film 141a particularly at the lower end portion of the leg portion of the gate electrode 151a is protected from this etching [FIG. 1 (e)]. After that, an n ⁺ type source / drain region (not shown), a passivation film (not shown), a source / drain electrode (not shown), etc. are formed to complete the MESFET adopted in this embodiment. To do.

As described above, in the first embodiment, the tungsten silicide film 141a at the portion forming the side wall at the lower end of the leg of the gate electrode 151a is not exposed to etching. Therefore, it is possible to prevent the gate length of the gate electrode 151a from being locally short, and to prevent the electrical characteristics from varying and deteriorating. Furthermore, since the sidewalls of the leg portions of the gate electrode 151a are covered with the sidewall spacers 131a in this way,
It is also suppressed that 1a easily breaks or peels off.

In the first embodiment, the metal film is the laminated film of the tungsten silicide film and the gold film.
It is not limited to this. Instead of the tungsten silicide film, another refractory metal silicide film such as a molybdenum silicide film or a titanium-tungsten silicide film can be used. Further, although the predetermined width of the opening 121a was 0.5 μm, it is not limited to this value, and it is preferably a value in the range of 0.25 to 1.0 μm. Depending on this value, the silicon nitride film 131 (as the case may be, the tungsten silicide film 141a, the gold film 1
The film thickness of 42a, etc.) is also changed appropriately.

Referring to FIG. 2 which is a sectional view of the manufacturing process of the MESFET, the second embodiment of the present invention is different from the first embodiment in that the insulating film and the thin film are a silicon nitride film and a silicon oxide film, respectively. It consists of the following:

First, in the same manner as in the first embodiment, the surface of the GaAs substrate 101, which is a semi-insulating substrate, is
The operating layer 102 made of n-type GaAs is formed by the epitaxial growth method or the like. Subsequently, this operation layer 102
A silicon nitride film 112 having a film thickness of about 500 nm (which is an insulating film) covering the entire surface of is formed by, for example, the PECVD method. The opening 121b is formed in the silicon nitride film 112 by a known photolithography technique and a known anisotropic plasma etching technique. (Opening) of the opening 121b at the portion reaching the operation layer 102
The width is 0.5 μm (predetermined width) [FIG. 2 (a)].

Next, a thin silicon oxide film 1 is formed on the entire surface.
32 is formed by, for example, the LPCVD method [FIG.
(B)]. The film thickness of the silicon oxide film 132 is approximately equal to 100 nm on the upper surface of the silicon nitride film 112 and the sidewall of the opening 121b, and is smaller than 1/2 of the predetermined width of the opening 121b. The gate length of the T-shaped (or Y-shaped) gate electrode obtained in this embodiment is also determined by the predetermined width of the opening 121b and the thickness of the silicon oxide film 132.

Subsequently, the silicon oxide film 132 is etched back by known anisotropic etching to form sidewall spacers 132b made of a silicon oxide film. The width of the sidewall spacer 132b is approximately equal to the film thickness of the silicon oxide film 132 [FIG. 2 (c)].

Next, as in the first embodiment, a tungsten silicide film having a film thickness of about 100 nm and 4 are formed on the entire surface.
A gold film having a thickness of about 00 nm is sequentially formed, and the gold film and the tungsten silicide film are sequentially patterned, so that the tungsten silicide film 141b and the gold film 14 are formed.
A gate electrode 151b composed of 2b is formed. In a region covering at least the opening 121b (at least in a portion reaching the operating layer 102), the cross-sectional shape of the gate electrode 151b is T-shaped (or Y-shaped) [FIG.
(D)].

Subsequently, the silicon nitride film 112 is selectively removed by wet etching with phosphoric acid. The temperature of this wet etching with phosphoric acid is 50 to 70.
℃ is suitable. At this time, the etching rate of the silicon oxide film is sufficiently lower than that of the silicon nitride film 112. Therefore, the tungsten silicide film 141b at the leg portion of the gate electrode 151b is protected from this etching by the sidewall spacer 132b made of a silicon oxide film [FIG. 2 (e)].
Thereafter, similarly to the first embodiment, an n ⁺ type source / drain region (not shown), a passivation film (not shown), a source / drain electrode (not shown), etc. are formed, and The MESFET according to the example is completed.

The second embodiment has the effects of the first embodiment. In addition, the parasitic capacitance of the gate electrode is reduced in this embodiment as compared with the first embodiment, although it is slight.

Referring to FIG. 3 which is a sectional view of the manufacturing process of the MESFET, the third embodiment of the present invention is different from the first embodiment in that the thin film is an amorphous silicon film. , Is as follows.

First, by the same method as in the first embodiment, an operating layer 102 made of n-type GaAs is formed on the surface of a GaAs substrate 101 by an epitaxial growth method or the like, and the entire surface of the operating layer 102 is covered (insulation). It is a film) 5
A silicon oxide film 111c having a film thickness of about 00 nm is formed, and an opening 121c is formed in this silicon oxide film 111c. The (opening) width of the opening 121c at the portion reaching the operation layer 102 is 0.5 μm (predetermined width) [FIG. 3 (a)].

Next, an amorphous silicon film 133 (which is a thin film) is formed on the entire surface by a method such as sputtering. The film thickness of the amorphous silicon film 133 is about 200 nm on the upper surface of the silicon oxide film 111c and about 120 nm on the side wall of the opening 121c [FIG.
(B)]. The film thickness of the amorphous silicon film 133 on the side wall of the opening 121c is smaller than ½ of the predetermined width of the opening 121c. The gate length of the T-shaped (or Y-shaped) gate electrode obtained in this example is also
It is determined from the predetermined width of the opening 121c and the film thickness of the amorphous silicon film 133. Note that the amorphous silicon film 133
Alternatively, a polycrystalline silicon film may be formed.

[0029] Subsequently, this example SF ₆ relative to the amorphous silicon film 133 is etched back by anisotropic etching using the etching gas are performed, sidewall spacer 133c made of an amorphous silicon film is formed To be done. The width of this sidewall spacer 131c is
Thickness of the amorphous silicon film 133 (about 120 nm)
Is equal to [Fig. 3 (c)].

Then, a tungsten silicide film with a thickness of about 100 nm and a gold film with a thickness of about 400 nm are formed on the entire surface by the same method as in the first embodiment, and these gold film and tungsten silicide film are formed. Are patterned to form the tungsten silicide film 141c and the gold film 14.
2c to form a gate electrode 151c [FIG.
(D)].

Then, similarly to the first embodiment, the silicon oxide film 111c is selectively removed by wet etching with buffered hydrofluoric acid. The etching rate of the amorphous silicon film by the buffered hydrofluoric acid is about 1/100 of that of the silicon oxide film 111c.
Therefore, in this wet etching, the sidewall spacers 133c made of the amorphous silicon film are hardly etched. Therefore, especially in the leg portion of the gate electrode 151c, the tungsten silicide film 1 is formed.
41c is protected from this etching [Fig.
(E)]. After that, an n ⁺ type source / drain region (not shown), a passivation film (not shown), a source / drain region
A drain electrode (not shown) and the like are formed, and the MESFET adopted in this embodiment is completed.

The third embodiment has the same effect as the first embodiment. Further, the present embodiment has an effect peculiar to this embodiment. That is, the coefficient of thermal expansion (2.6 × 10 ⁻⁶ ° C. ⁻¹ ) of the amorphous silicon film 133 (compared to a silicon nitride film or a silicon oxide film) is the GaAs substrate 101.
Since it is close to the coefficient of thermal expansion (5 × 10 ⁻⁷ ° C. ⁻¹ ) of Example 1, stress with respect to temperature is smaller in this example than in the first and second examples.

Referring to FIG. 4 which is a cross-sectional view of the manufacturing process of the MESFET, the fourth embodiment of the present invention is different from the first embodiment in that the thin film is made of a tungsten film. It is like this.

First, by the same method as in the first embodiment, the operating layer 102 made of n-type GaAs is formed on the surface of the GaAs substrate 101 by the epitaxial growth method or the like, and the entire surface of the operating layer 102 is covered (insulation). It is a film) 5
A silicon oxide film 111d having a film thickness of about 00 nm is formed, and an opening 121d is formed in this silicon oxide film 111d. The (opening) width of the opening 121d at the portion reaching the operation layer 102 is 0.5 μm (predetermined width) [FIG. 4 (a)].

Next, a tungsten film 134 (a thin film and a refractory metal film) is formed on the entire surface by a method such as sputtering. This tungsten film 134
Has a thickness of 200 n on the upper surface of the silicon oxide film 111d.
and about 120 nm on the side wall of the opening 121d [FIG. 4 (b)]. The thickness of the tungsten film 134 on the side wall of the opening 121d is set to the above-mentioned opening 121d.
Is less than ½ of the predetermined width of. The gate length of the T-shaped (or Y-shaped) gate electrode obtained in this embodiment is also determined by the predetermined width of the opening 121d and the film thickness of the tungsten film 134.

Subsequently, the tungsten film 134 is etched back by anisotropic etching using, for example, SF ₆ as an etching gas, and sidewall spacers 131d made of an amorphous silicon film are formed. The width of the sidewall spacer 131d is approximately equal to the film thickness (about 120 nm) of the tungsten film 134 [FIG. 4 (c)].

Then, a tungsten silicide film having a film thickness of about 100 nm and a gold film having a film thickness of about 400 nm are formed on the entire surface by the same method as in the first embodiment. The gold film and the tungsten silicide film are formed. Are patterned to form the gold film 142d and the tungsten silicide film 14.
A gate electrode 151d composed of 1d is formed [FIG.
(D)].

Then, similarly to the first embodiment, the silicon oxide film 111d is selectively removed by wet etching with buffered hydrofluoric acid. With this buffered hydrofluoric acid, the tungsten film (sidewall spacer 131d made of) is hardly etched. Therefore, the tungsten silicide film 141d particularly at the lower end portion of the leg portion of the gate electrode 151d is protected from this etching [FIG. 4 (e)]. afterwards,
An n ⁺ type source / drain region (not shown), a passivation film (not shown), a source / drain electrode (not shown), etc. are formed, and the ME used in this embodiment is adopted.
SFET is completed.

The fourth embodiment has the effects of the first embodiment. Further, in the present embodiment, the sidewall spacer 131d left on the side surface of the leg portion of the gate electrode 151d is not an insulating film, so that the first and second
Also, the parasitic capacitance of the gate electrode is reduced as compared with the third embodiment.

Although the tungsten film and the tungsten silicide film are adopted as the refractory metal film and the refractory metal silicide film in the fourth embodiment, the invention is not limited to this. For example, even when the refractory metal silicide film is a tungsten silicide film, a refractory metal film other than the tungsten film may be used. On the contrary, even when the refractory metal film is a tungsten film, a refractory metal silicide film other than the tungsten silicide film may be used.

[0041]

As described above, according to the method of manufacturing the semiconductor device of the present invention, the T-shape of the MESFET or the Y-shape.
The workability of the V-shaped gate electrode is excellent, there is little variation in the electrical characteristics of the obtained gate electrode, and there is less deterioration in the electrical characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the manufacturing process of the second embodiment of the present invention.

FIG. 3 is a cross-sectional view of the manufacturing process of the third embodiment of the present invention.

FIG. 4 is a cross-sectional view of the manufacturing process of the fourth embodiment of the present invention.

FIG. 5 is a cross-sectional view of the manufacturing process of the gate electrode of the conventional MESFET.

[Explanation of symbols]

101, 201 GaAs substrate 102, 202 Working layer 111a, 111c, 111d, 132, 211, 211
31 Silicon Oxide Film 112, 131 Silicon Nitride Film 121a to 121d, 221 Opening 133 Amorphous Silicon Film 134 Tungsten Film 131a, 132b, 133c, 134d, 231a
Side wall spacers 141a to 141d, 241 Tungsten silicide film 142a to 142d, 242 Gold film 151a to 151d, 251 Gate electrode

Claims (5)

[Claims] 1. A step of forming an insulating film on a surface of a compound semiconductor substrate having an operation layer provided in a predetermined region, and a step of forming at least a gate electrode on the surface of the compound semiconductor substrate with a predetermined width. A step of forming an opening in the insulating film, which reaches a region including a region, a step of depositing a thin film on the surface of the compound semiconductor substrate including the insulating film, and an etchback method by anisotropic etching, Forming a sidewall spacer made of the thin film on the sidewall of the opening, and on the surface of the compound semiconductor substrate including the insulating film,
Forming a metal film having at least the lowermost layer of a refractory metal silicide film; and patterning the metal film to form a gate electrode having a width wider than the predetermined width and covering the opening. And a step of selectively removing the insulating film by isotropic etching. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film, and the thin film is a silicon nitride film. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a silicon nitride film, and the thin film is a silicon oxide film. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film, and the thin film is an amorphous silicon film or a polycrystalline silicon film. 5. The insulating film is a silicon oxide film, and the thin film is a refractory metal film.
A method for manufacturing a semiconductor device as described above.