JPH07226407A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make the depths of the recesses of both power and monitor FETs equal to each other and make the values of the currents of both the power and monitor FETs each of which flows in between the source and drain of each FET equal to each other, by providing an electrode which is contacted in an ohmic way with a part of the n-type semiconductor layer extended from the n-type active layer of the power FET, and by recess-etching the surface of the n-type semiconductor layers of both the power and monitor FETs. CONSTITUTION:In the method of manufacturing a semiconductor device, by the use of an ion implanting method, on the surface of a semi-insulation GaAs substrate, n-type active layers 1, 3 and high-concentration n<+>-contact layers 2, 4 of both power and monitor FETs are formed respectively, and further, an n-type semiconductor layer 1a is formed. Moreover, source electrodes 5, 7 an drain electrodes 6, 8 of both the power and monitor FETs are formed respectively, and further, a third electrode 5a is formed. In the recess-etching process of the manufacturing method, regarding both the power and monitor FETs, the regions to be recess-etched and the AuGe electrodes connected respectively with the n-type active layers are dipped into an etching liquid, and therefore, the so-called battery effect acts equally on both the power and monitor FETs, and as a result, the recess-etching quantities of both the power and monitor FETs are made equal to each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a method for manufacturing a field effect transistor, and more particularly to a method for manufacturing a power FET having a so-called recess gate structure in which a gate electrode is provided in a concave portion on the surface of an n-type active layer.

[0002]

2. Description of the Related Art GaAs field effect transistors (hereinafter G
The aAs FET is abbreviated) and is widely used in microwave communication devices because it has excellent high frequency characteristics. GaA
In order to increase the output of the s FET and improve the high frequency characteristics, a high drain breakdown voltage and a low source resistance are required, and a recess gate structure is generally adopted to realize this. The recess gate structure is the source electrode,
A structure in which a groove is provided in a part of the n-type active layer between the drain electrodes and the gate electrode is provided in the groove (recess). In a GaAs FET adopting this structure, a low source resistance can be realized because the thickness of the n-type active layer other than the recessed portion can be made sufficiently thick, and the high electric field region applied between the gate and the drain is only at the gate electrode edge. High drain withstand voltage can be realized because it is distributed to the recess edge instead.

A process called a recess etching process is used in manufacturing the recess gate structure GaAs FET. This step is a step of forming a groove (recess) on the surface of the n-type active layer in a region where a gate electrode will be provided later, and the depth of this groove is adjusted so that the source-drain current has a desired current value. It Generally, in manufacturing a power FET having a structure in which a large number of gate electrodes are arranged in parallel,
Since it is impossible to directly measure the source-drain current in-process, the power FET to be manufactured
A monitor FET having a small gate width and having a basic structure almost the same as that of (1) is simultaneously formed, and the etching amount of the recess is determined while checking the current value of this FET.

An example of a conventional method for manufacturing a recess gate structure FET will be described below with reference to FIGS.

The n-type active layer 201 of the power FET, the high-concentration n ⁺ contact layer 202, and the n-type active layer 20 of the monitor FET are formed on the surface of the semi-insulating GaAs substrate by the ion implantation method.
3. A high concentration n ⁺ contact layer 204 is formed (FIG. 3).

Next, the source electrode 205 and the drain electrode 206 of the power FET made of AuGe are formed by using the lift-off method.
Then, the source electrode 207 and the drain electrode 208 of the monitor FET are formed, and the SiO ₂ film 209 is further formed on the entire surface by the chemical vapor deposition method (FIG. 4A).

Next, a photoresist film 210 is deposited, and an opening 211 is provided in a region where a gate electrode will be formed. In the monitor FET, in addition to the opening 211, an opening 212 is provided on the source electrode and the drain electrode, and the SiO ₂ film is etched using the photoresist film as a mask to form a gate electrode on the GaAs surface. The monitor FET source electrode 207 and the drain electrode 208 are exposed (FIG. 4B).

Next, using a phosphoric acid-based etching solution, GaAs
The surface is etched to form the recess 213 (FIG. 4).
(C)). At this time, the etching is performed while checking the current between the exposed source electrode 207 and drain electrode 208 of the monitor FET, and the etching is terminated when the desired current value is reached.

Next, after depositing a metal for the gate electrode, for example, an Al film on the entire surface, the gate electrode 2 is formed by the lift-off method.
14 is formed. At this time, the source electrode 2 of the monitor FET
The Al film 215 is also deposited on 07 and the drain electrode 208 (FIG. 5). Next, the bonding pad metal Au /
Pt / Ti is formed using the lift-off method to complete the FET (not shown).

However, GaA produced by the above manufacturing method
The s FET has the following problems. That is, the source / drain current values of the monitor FET and the completed power FET do not necessarily correspond as expected. This is a monitor FET when performing recess etching.
Then, while the n-type active layer is etched in a state where the ohmic electrode made of AuGe is exposed to the etching solution, in the power FET, the ohmic electrode made of AuGe is etched in the state where the n-type active layer is not exposed to the etching solution. This is because the conditions are different, such as being done. That is, in the recess etching of the monitor FET, the active layer and the AuGe electrode connected to the active layer are simultaneously immersed in the etching solution, and a so-called battery effect is exerted. For this reason, the depth of the recess of the monitor FET does not match the depth of the recess of the power FET, and generally the depth of the recess of the monitor FET becomes deeper. Therefore, the current value of the power FET is expected from the monitor FET. It is larger than the value.

In order to eliminate the inconvenience, the electric power F
It is sufficient to prevent the ohmic electrode made of AuGe of the monitor FET from being exposed to the etching solution as in the case of ET. In this case, however, the ohmic electrode made of AuGe of the monitor FET is covered with SiO ₂ so that the source electrode is formed. -It becomes difficult to bring a probe for current measurement into contact with the drain electrode.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and the recess etching of the monitor FET and the power FET is performed under the same condition. It is an object of the present invention to provide a method for manufacturing MESFETs in which the drain current values are the same.

[0013]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a GaAs power FET.
In forming the same on the same semiconductor substrate, an electrode that makes ohmic contact with a part of the n-type semiconductor layer extending from the n-type active layer of the power FET is provided, and the electrode of the power FET is exposed with the electrode exposed to the etching solution. The method is characterized by including a step of recess etching the surface of the n-type active layer.

[0014]

According to the FET manufacturing method of the present invention, the recess etching of the power FET and the monitor FET are both performed under the same condition in which the battery effect occurs.
The recess depth of the power FET and the monitor FET and the current value between the source and the drain are the same, and the accuracy of current control by the monitor FET is significantly improved.

[0015]

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 and 2.

Using the ion implantation method, the n-type active layer 1 of the power FET, the high-concentration n ⁺ contact layer 2, and the n-type semiconductor layer 1a extending from the high-concentration n ⁺ contact layer are formed on the surface of the semi-insulating GaAs substrate. Then, the n-type active layer 3 and the high-concentration n ⁺ contact layer 4 of the monitor FET are formed (FIG. 1).
(A)).

Then, the AuGe thin film is lifted off, so that the source electrode 5 and the drain electrode 6 of the power FET, the third electrode 5a which makes an ohmic contact with the n-type semiconductor layer 1a, and the source electrode 7 and the drain of the monitor FET. After forming the electrode 8, a SiO ₂ film 9 is deposited on the entire surface by chemical vapor deposition (FIG. 1B).

Next, a photoresist film 10 is deposited, and an opening 11 is provided in a region where a gate electrode will be formed. In this step, in addition to the opening 11 in the monitor FET, the opening 12 is also provided on the source electrode 7 and the drain electrode 8. Further, the opening 12a is formed on the third electrode 5a, which is a feature of the present invention.
To provide. Next, using the photoresist film 10 as a mask, the SiO ₂ film is etched to expose the GaAs surface in the region where the gate electrode is to be formed, the monitor FET source electrode 7 and the drain electrode 8, and the third electrode 5a (FIG. 1). (C)).

Next, using a phosphoric acid type etching solution, GaAs
The surface is etched to form the recess 13 (see FIG. 2).
(A)). At this time, the etching is performed while etching the current between the exposed source electrode 7 and drain electrode 8 of the monitor FET, and the etching is terminated when the desired current value is reached.

In this recess etching step, power FE is used.
In both T and the monitor FET, since the region to be recess-etched and the AuGe electrode connected to the active layer are immersed in the etching solution, the so-called battery effect works equally and the recess etching amounts of the power FET and the monitor FET become equal.

Next, after depositing a metal for the gate electrode, for example, an Al film on the entire surface, the gate electrode 1 is formed by the lift-off method.
4 is formed. At this time, the source electrode 7 of the monitor FET
Al film 1 also on the drain electrode 8 and the third electrode 5a.
5 is attached (FIG. 2 (b)).

Next, the bonding pad metal Au /
FET is completed by forming Pt / Ti using the lift-off method (not shown). The n-type semiconductor layer 1a and the third electrode 5a joined to the n-type semiconductor layer 1a do not substantially affect the characteristics of the power FET. Further, n-type semiconductor layer was formed in the same n layer and the active layer in the above embodiments may be formed in the same n ⁺ layer and n ⁺ contact layer.

[0023]

As described above, according to the present invention, the precision of the source / drain current control in the manufacture of the power FET having the recess gate structure using the monitor FET is improved, the quality is improved, and the yield in the manufacturing is improved. Can be significantly improved.

[Brief description of drawings]

1A to 1C are cross-sectional views showing a part of a manufacturing method of an embodiment of a recess gate structure GaAs power FET according to the present invention in the order of steps.

2 (a) and 2 (b) are cross-sectional views showing a part of a manufacturing method of an embodiment of a recess gate structure GaAs power FET according to the present invention, following FIG. 1 in the order of steps.

FIG. 3 is a GaAs power F having a recess gate structure according to a conventional example.
Sectional drawing of the one part process of the manufacturing method of one Example of ET.

4 (a) to 4 (c) are cross-sectional views each showing a part of a method of manufacturing a recess gate structure GaAs power FET according to a conventional example, following FIG.

FIG. 5: Recess gate structure GaAs power F according to a conventional example
Sectional drawing which shows a part of the manufacturing method of one Example of ET following FIG. 4 in order of process.

[Explanation of symbols]

1,201 n-type active layer of power FET 2,202 n ⁺ contact layer of power FET 1a n-type semiconductor layer extending from active layer 3,203 active layer of monitor FET 4,204 n ⁺ contact layer of monitor FET 5 , 205 source electrode of power FET 5a third electrode 6,206 drain electrode of power FET 7,207 source electrode of monitor FET 8,208 drain electrode of monitor FET 9,209 SiO ₂ film 10, 210 photoresist film 11, 12, 12a, 111, 112 Opening 13, 113 Recess 14, 114 Gate electrode

Claims (2)

[Claims] 1. A Schottky junction FET having a source electrode and a drain electrode which form an ohmic contact with an n-type active layer, and a gate electrode in a recess provided on the surface of the n-type active layer sandwiched between the two electrodes, The FET,
A step of forming a monitor FET for determining the recess etching amount of this FET and a step of forming an electrode which makes ohmic contact with a part of the n-type semiconductor layer extending from the n-type active layer of the FET, and an etching solution for the electrode. 1. A method of manufacturing a semiconductor device, comprising the step of: immersing the semiconductor substrate in the substrate and performing recess etching on the n-type active layer of the FET. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the FET is a power FET.