JPH07226301A - Resistor - Google Patents

Resistor

Info

Publication number
JPH07226301A
JPH07226301A JP6037846A JP3784694A JPH07226301A JP H07226301 A JPH07226301 A JP H07226301A JP 6037846 A JP6037846 A JP 6037846A JP 3784694 A JP3784694 A JP 3784694A JP H07226301 A JPH07226301 A JP H07226301A
Authority
JP
Japan
Prior art keywords
substrate
thin film
resistor
resistance value
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6037846A
Other languages
Japanese (ja)
Inventor
Satoru Ikeda
悟 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tama Electric Co Ltd
Original Assignee
Tama Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tama Electric Co Ltd filed Critical Tama Electric Co Ltd
Priority to JP6037846A priority Critical patent/JPH07226301A/en
Publication of JPH07226301A publication Critical patent/JPH07226301A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To manufacture a metal thin film resistor of high resistance value by a method wherein a pattern is formed on both surfaces of a substrate and they are coupled by a recessed type terminal. CONSTITUTION:A ceramic substrate is used as an electrically insulated substrate. A nickrome resistance thin film 2 and an electrode thin film 3 are coated on both surfaces of the substrate 1 by a magnetron sputtering method, and the above-mentioned thin films 2 and 3 are formed into patterns using a phtoetching method. Then, after a heat treatment is conducted on the pattern-formed substrate 1 at 300 to 400 deg.C for one hour, it is cut by a dicer. A recessed type lead frame 4 is inserted into an electrode pad, surface is adjusted by trimming using a laser beam, an encopsvlation 6 is provided and a resistor is completed. As a result, the resistance value of about twice of the conventional resistance value can be obtained without changing the external shape of the resistor.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、電子回路に活用される
抵抗器に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistor used in electronic circuits.

【0002】[0002]

【従来の技術】従来、ニクロムあるいはタンタル系の金
属薄膜を用いた抵抗器は、基板片面にパ ターン形成を
行ない作製していた。
2. Description of the Related Art Conventionally, a resistor using a nichrome or tantalum-based metal thin film has been manufactured by forming a pattern on one surface of a substrate.

【0003】[0003]

【発明が解決しようとする課題】従来の作製法では、パ
ターンの有効面積から抵抗値上限が限定されていた。
In the conventional manufacturing method, the upper limit of the resistance value is limited by the effective area of the pattern.

【0004】[0004]

【課題を解決するための手段】基板両面にパターン形成
を行ない凹型の端子で連結することにより、同形状であ
れば約2倍の面積を利用することが出来、同一面積抵
抗値で完成抵抗値を従来の 約2倍まで上げることが可
能となった。
[Means for Solving the Problems] By forming a pattern on both sides of a substrate and connecting them with concave terminals, it is possible to use about twice the area of the same shape. It has become possible to increase the value to about twice that of the conventional value.

【0005】[0005]

【実施例1】この実施例においては、電気的絶縁基板と
して50mm×60mm,厚みが0. 635mmのセ
ラミック基板を用いた。該基板両面にマグネトロンスパ
ッタ法に よりニクロム系の抵抗薄膜及び電極薄膜を着
膜し、該薄膜をフォトエッチング法 で図1(2)及び
(3)の如くパターン形成した。次いで該パターン形成
済み基 板に300〜400℃で1時間以上の熱処理を
施した後、図2の如くダイサーで 切断した。図2−
1)は表面、2−2)は裏面である。次いで電極パット
に凹型のリードフレーム(4)を挿入し、はんだ(5)
付けを 行い表面をレーザ光でトリミングし抵抗値を調
整した後、外装(6)を施して図 3の如く完成した。
本製品の仕様は1〜3ピン間2MΩ、精度±0.1%で
ある。
Example 1 In this example, an electrically insulating substrate was 50 mm × 60 mm and had a thickness of 0. A 635 mm ceramic substrate was used. Nichrome-based resistance thin films and electrode thin films were deposited on both surfaces of the substrate by magnetron sputtering, and the thin films were patterned by photoetching as shown in FIGS. 1 (2) and (3). Then, the patterned substrate was heat-treated at 300 to 400 ° C. for 1 hour or more, and then cut with a dicer as shown in FIG. Figure 2-
1) is the front surface and 2-2) is the back surface. Then insert the concave lead frame (4) into the electrode pad and solder (5)
After attaching and trimming the surface with laser light to adjust the resistance value, the exterior (6) was applied to complete the product as shown in FIG.
The specifications of this product are 2MΩ between pins 1 and 3 and accuracy ± 0.1%.

【0006】[0006]

【実施例2】この実施例は、実施例1をネットワーク抵
抗に応用したものである。実施例1と同様に絶縁基板と
して50mm×60mm,厚みが0.635mmの セ
ラミック基板を用い、該基板両面にマグネトロンスパッ
タ法によりニクロム系 の抵抗薄膜及び電極薄膜を着膜
し、該薄膜をフォトエッチング法でパターン形成 し
た。次いで該パターン形成済み基板に熱処理を施した
後、図4の如くダイサー で切断した。図4−1)は表
面、4−2)は裏面である。次いで電極パットに凹型の
リードフレーム(4)を挿入し、はんだ(5)付けを
行い表面をレーザ光でトリミングし抵抗値を調整した
後、外装(6)を施して図 5の如く完成した。本製品
の仕様は1〜3及び4〜6ピン間2MΩ、精度±0.1
%である。
Second Embodiment This embodiment is an application of the first embodiment to a network resistor. As in Example 1, a ceramic substrate having a size of 50 mm × 60 mm and a thickness of 0.635 mm was used as an insulating substrate, and a nichrome-based resistance thin film and electrode thin film were deposited on both surfaces of the substrate by magnetron sputtering, and the thin film was photoetched. The pattern was formed by the method. Next, the patterned substrate was heat-treated and then cut with a dicer as shown in FIG. 4-1) is the front surface and 4-2) is the back surface. Next, insert a concave lead frame (4) into the electrode pad and attach solder (5).
After trimming the surface with laser light and adjusting the resistance value, the exterior (6) was applied to complete the process as shown in FIG. The specifications of this product are 2MΩ between pins 1 to 3 and 4 to 6 and accuracy ± 0.1.
%.

【0007】[0007]

【発明の効果】本発明により製品の外形形状を変えるこ
となく、従来の約2倍の抵抗値を得るこ とが可能とな
った。
According to the present invention, it is possible to obtain a resistance value about twice that of the conventional one without changing the outer shape of the product.

【0008】[0008]

【図面の簡単な説明】[Brief description of drawings]

【図1】膜の構成を示した断面図である。FIG. 1 is a cross-sectional view showing the structure of a film.

【図2】金属薄膜単体抵抗のパターン構成を示した上面
図である。
FIG. 2 is a top view showing a pattern configuration of a metal thin film single resistor.

【図3】本発明の製造法で製造した薄膜単体抵抗器を示
す全体図である。
FIG. 3 is an overall view showing a thin film single resistor manufactured by the manufacturing method of the present invention.

【図4】金属薄膜ネットワーク抵抗のパターン構成を示
した上面図である。
FIG. 4 is a top view showing a pattern configuration of a metal thin film network resistor.

【図5】本発明の製造法で製造した薄膜ネットワーク抵
抗器を示す全体図である。
FIG. 5 is an overall view showing a thin film network resistor manufactured by the manufacturing method of the present invention.

【符号の説明】[Explanation of symbols]

1:セラミック基板 2:ニクロム系抵抗膜 3:電極膜 4:凹型リードフレーム 5:はんだ 6:外装 1: Ceramic substrate 2: Nichrome resistance film 3: Electrode film 4: Recessed lead frame 5: Solder 6: Exterior

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】基板両面にパターン形成を行ない凹型の端
子で連結することにより、 高抵抗値作成を
可能とした金属薄膜抵抗器。
1. A metal thin film resistor capable of producing a high resistance value by forming a pattern on both surfaces of a substrate and connecting them with concave terminals.
JP6037846A 1994-02-10 1994-02-10 Resistor Pending JPH07226301A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6037846A JPH07226301A (en) 1994-02-10 1994-02-10 Resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6037846A JPH07226301A (en) 1994-02-10 1994-02-10 Resistor

Publications (1)

Publication Number Publication Date
JPH07226301A true JPH07226301A (en) 1995-08-22

Family

ID=12508908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6037846A Pending JPH07226301A (en) 1994-02-10 1994-02-10 Resistor

Country Status (1)

Country Link
JP (1) JPH07226301A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002075754A3 (en) * 2001-03-19 2003-03-20 Delphi Tech Inc An independently housed trim resistor and a method for fabricating same
US8395091B2 (en) 2008-02-06 2013-03-12 H.E.F. Method for fabricating a heating element by depositing thin layers on an insulating substrate and the element thus obtained
JP2019160980A (en) * 2018-03-13 2019-09-19 ミクロン電気株式会社 Cement resistor
US11307159B2 (en) 2017-05-18 2022-04-19 Delphi Technologies Ip Limited Ionic-conducting resistor for exhaust constituent sensors

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002075754A3 (en) * 2001-03-19 2003-03-20 Delphi Tech Inc An independently housed trim resistor and a method for fabricating same
US8395091B2 (en) 2008-02-06 2013-03-12 H.E.F. Method for fabricating a heating element by depositing thin layers on an insulating substrate and the element thus obtained
US11307159B2 (en) 2017-05-18 2022-04-19 Delphi Technologies Ip Limited Ionic-conducting resistor for exhaust constituent sensors
JP2019160980A (en) * 2018-03-13 2019-09-19 ミクロン電気株式会社 Cement resistor

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