JPH0722618A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0722618A
JPH0722618A JP15233093A JP15233093A JPH0722618A JP H0722618 A JPH0722618 A JP H0722618A JP 15233093 A JP15233093 A JP 15233093A JP 15233093 A JP15233093 A JP 15233093A JP H0722618 A JPH0722618 A JP H0722618A
Authority
JP
Japan
Prior art keywords
film
polycrystalline
amorphous
gate oxide
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP15233093A
Other languages
Japanese (ja)
Inventor
Hiroyuki Morii
啓之 森井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Steel Corp
Original Assignee
Kawasaki Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kawasaki Steel Corp filed Critical Kawasaki Steel Corp
Priority to JP15233093A priority Critical patent/JPH0722618A/en
Publication of JPH0722618A publication Critical patent/JPH0722618A/en
Withdrawn legal-status Critical Current

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To form a gate electrode of low resistance by a method wherein a first amorphous Si film and a polycrystalline Si film are formed on a gate oxide film, a second amorphous Si film is formed by implanting impurity ions, and the first and the second amorphous Si films are turned into polycrystalline Si films. CONSTITUTION:A gate oxide film 12 is formed on the surface of an Si substrate 10, and a first amorphous Si film 22 is formed on the film 12. A polycrystalline Si film 24 is formed, and a second amorphous Si film 26 is formed by doping the polycrystalline Si film 24 with P. The first and the second amorphous Si films 22, 26 are turned into a polycrystalline Si film 28 having large crystal grains. In the polycrystalline Si film 28, crystal grain boundary where P is segregated becomes little, and uniform diffusion into Si crystal grains is obtained. Thereby the resistance of a gate electrode is reduced, and throughput can be improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ゲート酸化膜の上にゲ
ート電極を形成する半導体装置の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a gate electrode is formed on a gate oxide film.

【0002】[0002]

【従来の技術】MOSFET(MOSトランジスタ)の
基本構造は、Si基板の表面に厚さ数100Åのゲート
酸化膜(SiO2 )を介してゲート電極が形成され、こ
れらの左右にソースとドレインが形成された構造であ
り、一般にゲート電極は多結晶Siで形成されている。
図2を参照してゲート電極の従来の形成方法を説明す
る。
2. Description of the Related Art In the basic structure of a MOSFET (MOS transistor), a gate electrode is formed on the surface of a Si substrate through a gate oxide film (SiO 2 ) having a thickness of several hundred liters, and a source and a drain are formed on the left and right of these. The gate electrode is generally made of polycrystalline Si.
A conventional method of forming a gate electrode will be described with reference to FIG.

【0003】図2は、ゲート電極の従来の形成方法を示
す断面図である。先ず、Si基板10の表面に、厚さ数
100Åのゲート酸化膜12を介して、多結晶Si膜1
4を形成する(図2(a))。多結晶Siの抵抗を低下
させるために、多結晶Si膜14にP(燐)をドープ
し、Pを高濃度に含有した多結晶Si膜16を形成する
(図2(b))。多結晶Si膜14へのPドープの方法
は、リンデポ工程といわれる方法が主流である。リンデ
ポ工程とは、図2(a)に示される構造のSi基板を炉
に装入し、この炉に、POCl3 蒸気、O2 ガス、N 2
ガスを流し、900℃程度の温度で熱処理して、多結晶
Si膜14にPを拡散させるものである。このリンデポ
工程以外にも、多結晶Si膜14へPイオンをイオン注
入することにより、多結晶Si膜14にPを高濃度ドー
プする方法もある。Pを高濃度に含有した多結晶Si膜
16を形成した後は、レジスト18を用いて所定の形状
に多結晶Si膜16をエッチングし(図2(c))、そ
の後レジスト18を除去してゲート電極20を形成する
(図2(d))。
FIG. 2 shows a conventional method of forming a gate electrode.
FIG. First, on the surface of the Si substrate 10, the thickness number
Polycrystalline Si film 1 through 100Å gate oxide film 12
4 is formed (FIG. 2A). Lower resistance of polycrystalline Si
In order to do so, the polycrystalline Si film 14 is doped with P (phosphorus).
Then, the polycrystalline Si film 16 containing P at a high concentration is formed.
(FIG.2 (b)). Method of P-doping the polycrystalline Si film 14
The mainstream method is the so-called lindepo process. Linde
In the po process, the Si substrate having the structure shown in FIG.
Charge it into the furnace and add POCl3 Steam, O2 Gas, N 2 
Gas is flowed and heat treated at a temperature of about 900 ° C
P is diffused into the Si film 14. This Lindepo
In addition to the process, ion implantation of P ions into the polycrystalline Si film 14
By adding P into the polycrystalline Si film 14,
There is also a way to Polycrystalline Si film containing P in high concentration
After forming 16, the resist 18 is used to form a predetermined shape.
Then, the polycrystalline Si film 16 is etched (FIG. 2 (c)).
After that, the resist 18 is removed to form the gate electrode 20.
(FIG. 2 (d)).

【0004】ところで、デバイスが微細化するに伴い、
抵抗が一層低いゲート電極が要求されている。ゲート電
極の抵抗を一層低くするためには、このゲート電極を構
成する多結晶Siの結晶粒内に多くのPを均一に拡散さ
せることが必要である。しかし、多結晶Siの結晶粒が
小さいと多くの結晶粒界があり、この結晶粒界にPが偏
析するため、多くのPを結晶粒内に均一に拡散させるこ
とが困難となる。
By the way, as devices are miniaturized,
There is a demand for a gate electrode having a lower resistance. In order to further reduce the resistance of the gate electrode, it is necessary to uniformly diffuse a large amount of P in the crystal grains of polycrystalline Si forming the gate electrode. However, if the crystal grains of polycrystalline Si are small, there are many grain boundaries, and P segregates at these grain boundaries, making it difficult to uniformly diffuse a large amount of P into the crystal grains.

【0005】そこで、図2(a)で示される工程におい
て、多結晶Si膜14に代えてアモルファスSi膜を形
成し、このアモルファスSi膜にPをイオン注入する方
法が研究され、実施されている。この方法によれば、ア
モルファスSi膜を形成した後の熱処理でアモルファス
Si膜が結晶粒の大きな多結晶Si膜に変化し、このた
め、多くのPを結晶粒内に均一に拡散させることができ
る。
Therefore, in the process shown in FIG. 2A, a method of forming an amorphous Si film in place of the polycrystalline Si film 14 and implanting P ions into this amorphous Si film has been studied and implemented. . According to this method, the amorphous Si film is changed into a polycrystalline Si film having large crystal grains by the heat treatment after the formation of the amorphous Si film, so that a large amount of P can be uniformly diffused in the crystal grains. .

【0006】[0006]

【発明が解決しようとする課題】ところが、多結晶Si
膜は、約620℃〜630℃の範囲の温度で成膜レート
100Å/min.で形成されるのに対し、アモルファ
スSi膜は、約520℃〜550℃の範囲の温度で成膜
レート20Å/min.で形成される。従って、図2
(a)で示される工程において、多結晶Si膜14に代
えてアモルファスSi膜を同じ膜厚形成すると、処理時
間が約5倍になり、処理能力が大きく低下しスループッ
トが小さくなってしまう。また、上記のアモルファスS
i膜はシランガスを用いて形成されるが、このシランガ
スに代えてジシランガスを用いると、成膜レートが速く
なることが知られている。しかし、ジシランガスを用い
る方法では、例えば100枚のウエハを一つの炉に装入
してまとめて処理すると、1枚のウエハ内や各ウエハ間
において膜厚の均一性が悪くなり、1バッチにおける処
理枚数を減らさなければならないという問題が新たに生
じる。
However, polycrystalline Si
The film has a film formation rate of 100 Å / min at a temperature in the range of about 620 ° C to 630 ° C. On the other hand, the amorphous Si film is formed at a film formation rate of 20 Å / min. Is formed by. Therefore, FIG.
When the amorphous Si film is formed to have the same film thickness in place of the polycrystalline Si film 14 in the step shown in (a), the processing time becomes about 5 times, the processing capacity is greatly reduced, and the throughput is reduced. In addition, the amorphous S
The i film is formed by using a silane gas, but it is known that the film forming rate becomes faster if a disilane gas is used instead of the silane gas. However, in the method using disilane gas, for example, when 100 wafers are loaded into one furnace and collectively processed, the uniformity of the film thickness within one wafer or between wafers deteriorates, and the processing in one batch A new problem arises in that the number of sheets must be reduced.

【0007】また、ゲート酸化膜の上に、従来のように
多結晶Si膜のみ形成し、この多結晶Si膜に不純物を
イオン注入することにより、この多結晶Si膜をアモル
ファスSi膜に変化させる方法も考えられる。しかし、
この方法で、多結晶Si膜の全てをアモルファスSi膜
に変化させるためには、不純物イオンがゲート酸化膜を
突き抜けてしまう程度のエネルギーで不純物イオンを打
込まなくてはならない。不純物イオンがゲート酸化膜を
突き抜けてSi基板に到達すると、しきい値電圧のシフ
ト等の問題が発生する。このため、ゲート酸化膜の上に
多結晶Si膜のみを形成して不純物イオンの注入を行う
方法は採用できない。
Further, as in the prior art, only a polycrystalline Si film is formed on the gate oxide film, and impurities are ion-implanted into the polycrystalline Si film to change the polycrystalline Si film into an amorphous Si film. A method is also possible. But,
In order to change the entire polycrystalline Si film into an amorphous Si film by this method, it is necessary to implant the impurity ions with such energy that the impurity ions penetrate through the gate oxide film. When the impurity ions penetrate the gate oxide film and reach the Si substrate, a problem such as a threshold voltage shift occurs. Therefore, a method of forming only a polycrystalline Si film on the gate oxide film and implanting impurity ions cannot be adopted.

【0008】本発明は、上記事情に鑑み、従来よりも低
抵抗のゲート電極を形成する半導体装置の製造方法を提
供することを目的とする。
In view of the above circumstances, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which a gate electrode having a resistance lower than that of a conventional one is formed.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
の本発明の半導体装置の製造方法は、ゲート酸化膜の上
にゲート電極を形成する半導体装置の製造方法におい
て、前記ゲート酸化膜の上に第1のアモルファスSi膜
を形成し、該第1のアモルファスSi膜の上に多結晶S
i膜を形成し、該多結晶Si膜に不純物イオンを注入す
ることにより該多結晶Si膜を第2のアモルファスSi
膜に変化させ、該第2のアモルファスSi膜が形成され
た基板を熱処理することにより前記第1及び第2のアモ
ルファスSi膜を多結晶Si膜に変化させることを特徴
とするものである。
A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises a method of manufacturing a semiconductor device in which a gate electrode is formed on a gate oxide film. A first amorphous Si film is formed on the first amorphous Si film, and a polycrystalline S film is formed on the first amorphous Si film.
An i film is formed, and impurity ions are implanted into the polycrystalline Si film to form a second amorphous Si film.
It is characterized in that the first and second amorphous Si films are changed into polycrystalline Si films by changing the film into a film and heat-treating the substrate on which the second amorphous Si film is formed.

【0010】ここで、ゲート酸化膜の上に形成する第1
のアモルファスSi膜に代えて、ゲート酸化膜の上に単
結晶Si膜を形成してもよい。
The first oxide formed on the gate oxide film
Instead of the amorphous Si film, a single crystal Si film may be formed on the gate oxide film.

【0011】[0011]

【作用】本発明の半導体装置の製造方法によれば、ゲー
ト酸化膜の上に第1のアモルファスSi膜が形成され、
この第1のアモルファスSi膜の上に多結晶Si膜が形
成される。この多結晶Si膜に不純物がイオン注入され
るが、このイオン注入の際のダメージ効果により、即ち
不純物イオンがSi原子に衝突して多結晶Si膜の結晶
性が破壊されることにより、多結晶Si膜は第2のアモ
ルファスSi膜に変化する。このイオン注入により形成
された第2のアモルファスSi膜及びゲート酸化膜の上
に形成された第1のアモルファスSi膜は、その後熱処
理により、結晶粒径の大きな多結晶Si膜に変化する。
このため、不純物が偏析する結晶粒界が少なくなり、不
純物はSi結晶粒内に均一に拡散する。この結果、従来
よりも一層低抵抗のゲート電極を形成することができ
る。また、不純物イオンの注入前にゲート酸化膜の上に
形成されるSi膜は、一部がアモルファスSi膜で、残
りは多結晶Si膜であるため、全てをアモルファスSi
膜にする場合に比べるとスループットは大きくなる。
尚、ゲート酸化膜の上に一旦アモルファスSi膜を形成
し、このアモルファスSi膜の上に多結晶Si膜を形成
するため、ゲート酸化膜を突き抜けてしまう程度のエネ
ルギーで不純物イオンを打込まなくても、多結晶Si膜
をアモルファスSi膜に変化させることができる。
According to the method of manufacturing a semiconductor device of the present invention, the first amorphous Si film is formed on the gate oxide film,
A polycrystalline Si film is formed on the first amorphous Si film. Impurities are ion-implanted into this polycrystalline Si film, but due to the damage effect at the time of this ion implantation, that is, the impurity ions collide with Si atoms to destroy the crystallinity of the polycrystalline Si film, The Si film changes to a second amorphous Si film. The second amorphous Si film formed by this ion implantation and the first amorphous Si film formed on the gate oxide film are changed by heat treatment to a polycrystalline Si film having a large crystal grain size.
Therefore, the crystal grain boundaries in which the impurities are segregated are reduced, and the impurities are uniformly diffused in the Si crystal grains. As a result, a gate electrode having a resistance lower than that of the conventional one can be formed. In addition, since the Si film formed on the gate oxide film before the implantation of the impurity ions is partly an amorphous Si film and the rest is a polycrystalline Si film, all of the Si film is amorphous Si film.
The throughput is higher than when using a film.
Since the amorphous Si film is once formed on the gate oxide film and the polycrystalline Si film is formed on this amorphous Si film, it is not necessary to implant the impurity ions with energy enough to penetrate the gate oxide film. Also, the polycrystalline Si film can be changed to an amorphous Si film.

【0012】ここで、ゲート酸化膜の上に形成する第1
のアモルファスSi膜に代えて、ゲート酸化膜の上に単
結晶Si膜を形成した場合は、この上に形成されるSi
膜も単結晶膜にかなり近い膜になる。単結晶膜に近い膜
であるほど、ウェハ面内均一性はよくなり抵抗値の抑制
も容易となる。
Here, the first formed on the gate oxide film
When a single crystal Si film is formed on the gate oxide film instead of the amorphous Si film of
The film also becomes a film which is considerably close to a single crystal film. The closer the film is to a single crystal film, the better the in-plane uniformity of the wafer and the easier it is to suppress the resistance value.

【0013】[0013]

【実施例】以下、図面を参照して本発明の半導体装置の
製造方法の一実施例を説明する。図1はゲート電極の形
成を示す断面図である。先ず、Si基板10の表面に形
成された厚さ数100Åのゲート酸化膜12を介して、
SiH2 ガスを使用した減圧CVDにより約500℃の
温度で、厚さ1000ÅのアモルファスSi膜22を形
成する(図1(a))。引き続き、温度を610℃に変
え、他の条件は同じまま、厚さ2500Åの多結晶Si
膜24を形成する(図1(b))。これにより、厚さ3
500ÅのSi膜が形成される。次に、多結晶Si膜2
4にPをドープさせると共に多結晶Si膜24をアモル
ファスSi膜に変化させるために、多結晶Si膜24
に、Pイオンを100KeVで1×1016cm-2注入す
る。これにより、多結晶Si膜24は、Pを高濃度に含
有したアモルファスSi膜26に変化する(図1
(c))。その後、酸化工程などの熱処理が施される
が、これらの熱処理によりアモルファスSi膜22,2
6は結晶粒径の大きな多結晶Si膜28に変化する(図
1(d))。図2に示される従来の方法により、620
℃程度で成膜した多結晶Siの粒径は0.1〜0.2μ
m程度であるが、多結晶Si膜28の結晶粒径は1.0
μm以上となる。このため、Pが偏析する結晶粒界が少
なくなり、PはSi結晶粒内に均一に拡散する。この結
果、1×1016cm-2程度のイオン注入により、多結晶
Siの抵抗は100Ω/□となる。また、不純物イオン
の注入前にゲート酸化膜の上に形成されるSi膜は、ア
モルファスSi膜22が厚さ1000Åで、多結晶Si
膜24が厚さ2500Åである。前述のように、多結晶
Si膜の成膜レートを100Å/min.、アモルファ
スSi膜の成膜レートを20Å/min.とすると、ア
モルファスSi膜22と多結晶Si膜を形成する合計の
時間は、約75分である。これに対し、3500Åの厚
さのアモルファスSi膜を形成する時間は、約175分
になる。従って、本実施例の半導体装置の製造方法によ
れば、ゲート電極を低抵抗にでき、しかもSi膜の全て
をアモルファスSi膜にする場合に比べるとスループッ
トは大きくなる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for manufacturing a semiconductor device of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing formation of a gate electrode. First, through the gate oxide film 12 having a thickness of 100 Å formed on the surface of the Si substrate 10,
An amorphous Si film 22 having a thickness of 1000Å is formed at a temperature of about 500 ° C. by low pressure CVD using SiH 2 gas (FIG. 1A). Subsequently, the temperature was changed to 610 ° C., and the other conditions remained the same, while the thickness of the polycrystalline Si was 2500 Å.
The film 24 is formed (FIG. 1B). This gives a thickness of 3
A 500 Å Si film is formed. Next, the polycrystalline Si film 2
In order to dope P with 4 and change the polycrystalline Si film 24 into an amorphous Si film, the polycrystalline Si film 24
Then, P ions are implanted at 100 KeV and 1 × 10 16 cm −2 . As a result, the polycrystalline Si film 24 changes to the amorphous Si film 26 containing P at a high concentration (FIG. 1).
(C)). After that, a heat treatment such as an oxidation process is performed. By these heat treatments, the amorphous Si films 22 and 2 are
6 changes into a polycrystalline Si film 28 having a large crystal grain size (FIG. 1 (d)). According to the conventional method shown in FIG.
The grain size of polycrystalline Si deposited at about ℃ is 0.1-0.2μ
m, but the crystal grain size of the polycrystalline Si film 28 is 1.0
It becomes more than μm. Therefore, the crystal grain boundaries in which P segregates are reduced, and P diffuses uniformly in the Si crystal grains. As a result, the resistance of polycrystalline Si becomes 100 Ω / □ by the ion implantation of about 1 × 10 16 cm -2 . The Si film formed on the gate oxide film before the implantation of the impurity ions is an amorphous Si film 22 having a thickness of 1000 Å and is made of polycrystalline Si.
The membrane 24 has a thickness of 2500Å. As described above, the deposition rate of the polycrystalline Si film is 100 Å / min. , The deposition rate of the amorphous Si film was 20Å / min. Then, the total time for forming the amorphous Si film 22 and the polycrystalline Si film is about 75 minutes. On the other hand, the time required to form an amorphous Si film having a thickness of 3500Å is about 175 minutes. Therefore, according to the method for manufacturing the semiconductor device of the present embodiment, the resistance of the gate electrode can be made low, and the throughput is increased as compared with the case where the entire Si film is an amorphous Si film.

【0014】[0014]

【発明の効果】以上説明したように本発明の半導体装置
の製造方法によれば、不純物のイオン注入を利用して多
結晶Si膜をアモルファスSi膜に変化させ、その後の
熱処理によりアモルファスSi膜を結晶粒径の大きな多
結晶Si膜に変化させているため、ゲート電極を低抵抗
にでき、しかもSi膜の全てをアモルファスSi膜にす
る場合に比べるとスループットを大きくすることができ
る。
As described above, according to the method of manufacturing a semiconductor device of the present invention, the polycrystalline Si film is changed into the amorphous Si film by utilizing the ion implantation of impurities, and the amorphous Si film is formed by the subsequent heat treatment. Since the polycrystalline Si film having a large crystal grain size is used, the resistance of the gate electrode can be reduced, and the throughput can be increased as compared with the case where the entire Si film is an amorphous Si film.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の製造方法によりゲート電
極を形成する工程を示す断面図である。
FIG. 1 is a cross-sectional view showing a step of forming a gate electrode by a method of manufacturing a semiconductor device according to the present invention.

【図2】ゲート電極の従来の形成方法を示す断面図であ
る。
FIG. 2 is a cross-sectional view showing a conventional method of forming a gate electrode.

【符号の説明】[Explanation of symbols]

10 Si基板 12 ゲート酸化膜 22 アモルファスSi膜 24 多結晶Si膜 26 Pを高濃度に含有したアモルファスSi膜 28 結晶粒径の大きな多結晶Si膜 10 Si Substrate 12 Gate Oxide Film 22 Amorphous Si Film 24 Polycrystalline Si Film 26 Amorphous Si Film Containing P in High Concentration 28 Polycrystalline Si Film with Large Grain Size

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 ゲート酸化膜の上にゲート電極を形成す
る半導体装置の製造方法において、 前記ゲート酸化膜の上に第1のアモルファスSi膜を形
成し、 該第1のアモルファスSi膜の上に多結晶Si膜を形成
し、 該多結晶Si膜に不純物イオンを注入することにより該
多結晶Si膜を第2のアモルファスSi膜に変化させ、 該第2のアモルファスSi膜が形成された基板を熱処理
することにより前記第1及び第2のアモルファスSi膜
を多結晶Si膜に変化させることを特徴とする半導体装
置の製造方法。
1. A method of manufacturing a semiconductor device, wherein a gate electrode is formed on a gate oxide film, wherein a first amorphous Si film is formed on the gate oxide film, and the first amorphous Si film is formed on the first amorphous Si film. A polycrystalline Si film is formed, and impurity ions are implanted into the polycrystalline Si film to change the polycrystalline Si film into a second amorphous Si film, and a substrate on which the second amorphous Si film is formed is formed. A method of manufacturing a semiconductor device, characterized in that the first and second amorphous Si films are changed into a polycrystalline Si film by heat treatment.
【請求項2】 前記第1のアモルファスSi膜に代え
て、単結晶Si膜を形成することを特徴とする請求項1
記載の半導体装置の製造方法。
2. A single crystal Si film is formed in place of the first amorphous Si film.
A method for manufacturing a semiconductor device as described above.
JP15233093A 1993-06-23 1993-06-23 Manufacture of semiconductor device Withdrawn JPH0722618A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15233093A JPH0722618A (en) 1993-06-23 1993-06-23 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15233093A JPH0722618A (en) 1993-06-23 1993-06-23 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0722618A true JPH0722618A (en) 1995-01-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JPH0722618A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6211455B1 (en) * 1998-07-02 2001-04-03 Astropower Silicon thin-film, integrated solar cell, module, and methods of manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6211455B1 (en) * 1998-07-02 2001-04-03 Astropower Silicon thin-film, integrated solar cell, module, and methods of manufacturing the same
US6362021B2 (en) 1998-07-02 2002-03-26 Astropower, Inc. Silicon thin-film, integrated solar cell, module, and methods of manufacturing the same
US6420643B2 (en) 1998-07-02 2002-07-16 Astropower, Inc. Silicon thin-film, integrated solar cell, module, and methods of manufacturing the same

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