JPH0722597A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To make an I/O region the one which can flexibly cope with the change in functions, the expansion of functions, etc., by forming a plurality of basic cells of different gate lengths in a control circuit region in the I/O region. CONSTITUTION:In an outer part of a semiconductor chip, an I/O region 120 which has a buffer region 120b having a final-stage output buffer and a control circuit region 120a which materializes specified circuit functions is formed. In the control circuit region 120a, a plurality of basic cells of different gate lengths are formed. What should be taken care of is that the control circuit region 120a includes at least part of a transistor which constitutes an input buffer. Since a plurality of transistors of different gate lengths are formed in the control circuit region 120a, an appropriate transistor can be selected from the transistors of different gate lengths. By this method, for example, delicate slew rate control, etc., can be conducted and thereby a very flexible device can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master array type semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Conventionally, master array type semiconductor integrated circuits have been widely used. The master array method is a method in which a large number of basic cells having a predetermined structure are formed in advance on an LSI chip, and wiring within the basic cells and between the basic cells is added to complete an integrated circuit that performs a desired operation. Say. In this master array system, various integrated circuits can be completed simply by creating a mask pattern for wiring, which is suitable for small-quantity, high-mix production.

FIG. 4 is a schematic configuration diagram of a master array type LSI chip, and FIG. 5 is an enlarged schematic diagram of an input / output area of the LSI chip. As shown in FIG. 4, the master array type LSI chip 10 has an internal primitive area 11 in which a large number of transistors forming a basic cell for a logic gate are formed in the central area, and the internal primitive area 11 is formed according to the specifications. A desired logic circuit function is realized by applying metal wiring.

An input / output area 12 including a control circuit area 12a and a buffer area 12b is formed around the internal primitive area 11. This input / output region is a region where a circuit for transmitting and receiving signals to and from the outside is formed, and signals are transmitted and received to and from the outside via pads 12c (see FIG. 5) arranged therein.

In the buffer area 12b forming the input / output area 12, transistors and the like for forming the final stage output buffer are built. In the control circuit area 12a, transistors and the like for realizing a slew rate control circuit and various test circuits are formed. As described above, transistors corresponding to the respective functions are formed in the respective regions and metal wiring is performed to complete an LSI chip that realizes a specific function.

[0006]

In the master array method, as described above, a transistor in which a base transistor is prefabricated is prepared, and metal wiring is performed according to specifications to realize a specific circuit function. However, it is almost impossible to change the specifications of the input / output area, and if it is desired to change this, it is necessary to change it from the base process for forming the transistor. Particularly in the control circuit area 12a, with the recent miniaturization and speeding up of LSIs, there is a strong tendency to incorporate various circuit functions such as a slew rate control circuit that regulates the change speed of an output signal and various test circuits. There is a demand for a structure that can flexibly cope with the process without changing the underlying process.

As one of the proposals that meet this requirement, there is one disclosed in Japanese Patent Application Laid-Open No. 60-30164. This is a transistor built in the control circuit area 12a,
When the circuit function to be realized in the control circuit area 12a is not sufficient with the transistor built in the control circuit area 12a, the internal primitive area 11 has a commonality with the transistor built in the internal primitive area 11. The transistor is diverted, while the control circuit area 12 is used.
When there are extra transistors built in a, the extra transistors are to be accommodated in the internal primitive region 11 side.

When the proposed method is adopted, the control circuit region 12a has some flexibility, and the necessity of changing the base process for forming the transistor is reduced to some extent, but it is not sufficient yet. It is desirable to make the control circuit area more flexible to the extent that delicate control of the slew rate can be performed without changing the underlying process.

In view of the above circumstances, it is an object of the present invention to provide a master array type semiconductor integrated circuit device having an input / output region capable of flexibly coping with a function change or a function expansion.

[0010]

A semiconductor integrated circuit device according to the present invention which achieves the above object, is provided in the peripheral portion of a semiconductor chip.
In a master array semiconductor integrated circuit device, wherein an input / output region having a buffer region having an output buffer at the final stage and a control circuit region for realizing a predetermined circuit function is formed, a gate is provided in the control circuit region. It is characterized in that a plurality of basic cells having different lengths are formed.

Here, the control circuit area may include at least a part of transistors forming an input buffer.

[0012]

In the semiconductor integrated circuit device of the present invention, since a plurality of transistors having different gate lengths are formed in the control circuit area, it is possible to select an appropriate transistor from the plurality of transistors having different gate lengths. For example, it is possible to realize delicate slew rate control and the like, which is extremely flexible.

Further, for example, a transistor having a short gate length formed in the control circuit region is used, and a threshold value for determining the input signal of the input buffer to be'H 'level or'L' level is used. Subtle adjustments are possible.

[0014]

EXAMPLES Examples of the present invention will be described below. 1 is a schematic structural diagram of an input / output region of an embodiment of a semiconductor integrated circuit device of the present invention, and FIG. 2 is a structural diagram of a basic cell formed in the input / output region shown in FIG. In FIG. 1, a large number of input / output regions 120 having the same structure (only four columns are shown here) are arranged in a slice structure, and each input / output region 120 is
Are the control circuit area 120a and the buffer area 12 respectively.
0b and 0b.

In the buffer area 120b, a transistor (not shown) that constitutes the final stage output buffer is built. The feature of this embodiment resides in the control circuit area 120a, in which the P-channel transistor 121a,
121b, 121c and N-channel transistor 1
22a, 122b, 122c are formed.

Each transistor 121a, 121b, 12
1c, 122a, 122b, and 122c each have a structure in which two gate lines 132 are formed on the diffusion region 131 as shown in FIG. 2, and P-channel transistors with different signs. 121a, 121
b and 121c have different gate widths W, and N-channel transistors 122a and 122b, which have different signs,
122c also has different gate widths W. Table 1 shows an example of the gate width W and the gate line width L of each transistor.

[0017]

[Table 1] ───────────────────────── W L ──────────────────── ────── 121a, 122a 10 μm 0.5 μm 121b, 122b 5 μm 0.5 μm 121c, 122c 2 μm 0.5 μm ─────────────────────── FIG. 3 is a circuit diagram showing an output buffer circuit with a slew rate control circuit.

The output buffer 140 at the final stage is formed in the output buffer area 120b (see FIG. 1), and the inverter 130 at the previous stage is formed in the control circuit area 120a. The output buffer 140 is the first output buffer 141.
And a second output buffer 142, the outputs of which are the same pad 15
It is connected to 0.

The first inverter 131 and the second inverter 132 of the inverter 130 are the P-channel transistors 14 of the first output buffer 141, respectively.
1a and the N-channel transistor 141b are connected to respective gates, and the third inverter 133 and the fourth inverter 134 of the inverter 130 are the P-channel transistor 142a and the N-channel transistor 142a of the second output buffer 142, respectively. It is connected to 142b.

Here, the first inverter 131 and the second inverter 132 are configured by using the P-channel transistor 121b and the N-channel transistor 122b having the intermediate gate width W = 5 μm shown in FIG. 1 and Table 1. ing. On the other hand, the third inverter 133 includes a P-channel transistor 121a having a gate width W = 10 μm and an N-channel transistor 1 having a gate width W = 2 μm.
22c is used, and therefore the third inverter 133 has the first and second inverters 131,
Compared with 132, the logic threshold value V _SW is closer to the power supply potential V _DD side.

The fourth inverter 134 includes a P-channel transistor 121c having a gate width W = 2 μm and an N-channel transistor 1 having a gate width W = 10 μm.
22a is used, and therefore, the fourth inverter 134 has a logic threshold V _SW of the ground potential as compared with the first and second inverters 131 and 132, as opposed to the third inverter 133. It is closer to the GND side.

Therefore, the first to fourth inverters 130
When the same signal is input to the second inverter 132 and the signal changes from the “H” level to the “L” level, for example, the logic threshold value V _SW of the second inverter 132 is the fourth inverter 13
Since it is higher than that of 4, the N-channel transistor 141b connected to the second inverter 132 is turned on first, and then the N-channel transistor 142b connected to the fourth inverter 134 is turned on. in this way,
The on / off timings of the two output buffers 141 and 142 are deviated from each other, whereby slew rate control is performed.

In addition to the above example, P-channel transistors 121a, 121b, 121c and N-channel transistors 122a, 122b, 122 having different gate widths W are used.
By connecting c in series or in parallel, it is possible to obtain the degree of freedom in selecting the logic threshold V _{SW at} a level close to full custom, which is changed from the base process for forming a transistor.

Further, by utilizing the P-channel transistor 121c and the N-channel transistor 122c having the small gate width W arranged in the control circuit region 120a shown in FIG.
Delicate tuning of the threshold value for determining the input signal of the input buffer as the “H” level or the “L” level is also facilitated.

[0025]

As described above, in the semiconductor integrated circuit device of the present invention, in the master array type semiconductor integrated circuit device, a plurality of basic cells having different gate lengths are formed in the control circuit region in the input / output region. Therefore, it is possible to perform delicate slew rate control of the output buffer and delicate threshold value adjustment of the input buffer without going back to the underlying process of making the transistor, and the degree of freedom in design is remarkably high. improves.

[Brief description of drawings]

FIG. 1 is a schematic structural diagram of an input / output region of an embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a structural diagram of a transistor formed in the input / output region shown in FIG.

FIG. 3 is a circuit diagram showing an output buffer circuit with a slew rate control circuit.

FIG. 4 is a schematic configuration diagram of a master array type LSI chip.

FIG. 5 is an enlarged schematic diagram of an input / output area of an LSI chip.

[Explanation of symbols]

10 LSI chip 11 Internal primitive area 12 Input / output area 12a Control circuit area 12b Buffer area 12c Pad 120 Input / output area 120a Control circuit area 120b Buffer area 121a, 121b, 121c P channel transistor 122a, 122b, 122c N channel transistor 140, 141 , 142 output buffers 130, 131, 132, 133, 134 inverters 150 pads

Claims (2)

[Claims] 1. A semiconductor device of a master array system in which an input / output region having a buffer region having an output buffer at the final stage and a control circuit region for realizing a predetermined circuit function is formed in the peripheral portion of a semiconductor chip. In the integrated circuit device, a plurality of basic cells having different gate lengths are formed in the control circuit region, which is a semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the control circuit region includes at least a part of transistors forming an input buffer.