JPH0722574A - Multichip module integrated board - Google Patents

Multichip module integrated board

Info

Publication number
JPH0722574A
JPH0722574A JP18543093A JP18543093A JPH0722574A JP H0722574 A JPH0722574 A JP H0722574A JP 18543093 A JP18543093 A JP 18543093A JP 18543093 A JP18543093 A JP 18543093A JP H0722574 A JPH0722574 A JP H0722574A
Authority
JP
Japan
Prior art keywords
chip module
board
multichip module
boards
wiring pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18543093A
Other languages
Japanese (ja)
Other versions
JP3216940B2 (en
Inventor
Masakazu Inaba
雅一 稲葉
Takeshi Iwayama
健 岩山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Mektron KK
Original Assignee
Nippon Mektron KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Mektron KK filed Critical Nippon Mektron KK
Priority to JP18543093A priority Critical patent/JP3216940B2/en
Publication of JPH0722574A publication Critical patent/JPH0722574A/en
Application granted granted Critical
Publication of JP3216940B2 publication Critical patent/JP3216940B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4688Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4691Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers

Landscapes

  • Combinations Of Printed Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PURPOSE:To provide a multichip module integrated board composed of a plurality of multichip module boards which are used for mounting modules composed of a plurality of LSI bare chips mounted on small high density wiring boards on a printed wiring board and which are connected to each other. CONSTITUTION:A plurality of multichip module boards A and B which are used for mounting modules composed of a plurality of LSI bare chips mounted on small high density wiring boards on a printed wiring board are provided. The circuit wiring pattern 1 of at least one layer of one (A) of the multichip module boards A and B is extended outward with its insulating base material to be connected continuously to the circuit wiring pattern 2 of the part of the other multichip module board B.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複数個のLSIベアチ
ップを小型の高密度配線基板に搭載してモジュ−ル化し
たものをプリント基板に搭載する為の複数のマルチチッ
プモジュ−ル基板間を相互に接続したマルチチップモジ
ュ−ル集合基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plurality of multi-chip module boards for mounting a plurality of LSI bare chips on a small high-density wiring board and forming a module on a printed board. The present invention relates to a multi-chip module aggregate substrate in which components are mutually connected.

【0002】[0002]

【従来技術とその問題点】この種の従来のマルチチップ
モジュ−ル基板は、図3の如く、セラミック基板やシリ
コン基板等からなる微細配線多層基板20にLSIチッ
プ等のベアチップ21,22を搭載し、該基板の外周部
に配列されたリ−ドアレイ23を使用してプリント基板
に実装する方法が採用されている。
2. Description of the Related Art In the conventional multi-chip module board of this type, as shown in FIG. 3, bare chips 21, 22 such as LSI chips are mounted on a fine wiring multi-layer board 20 made of a ceramic board, a silicon board or the like. Then, a method of mounting on the printed circuit board by using the lead array 23 arranged on the outer peripheral portion of the circuit board is adopted.

【0003】しかし、このような方法では、高密度実装
されたマルチチップモジュ−ル基板であってもプリント
基板との接続部分でプリント基板側に於ける回路形成限
界や接続限界の制限を受けるので、全体として高密度実
装配線基板を構成することは困難であった。
However, in such a method, even in a multi-chip module board mounted in high density, the circuit formation limit and the connection limit on the printed board side are restricted at the connection part with the printed board. It was difficult to construct a high-density mounting wiring board as a whole.

【0004】また、接続部分に於けるインピ−ダンスの
整合を図ることも困難であるので、実装系全体で高速化
を達成することは困難であった。
Further, since it is difficult to match the impedance at the connection portion, it has been difficult to achieve high speed in the entire mounting system.

【0005】[0005]

【課題を解決するための手段】本発明は上記のような従
来のマルチチップモジュ−ル基板実装に伴う問題点を好
適に解消する為のマルチチップモジュ−ル集合基板を提
供するものである。
SUMMARY OF THE INVENTION The present invention provides a multi-chip module aggregate substrate for suitably solving the problems associated with the conventional multi-chip module substrate mounting as described above.

【0006】その為に本発明のマルチチップモジュ−ル
集合基板では、複数個のLSIベアチップを小型の高密
度配線基板に搭載してモジュ−ル化したものをプリント
基板に搭載する為の複数のマルチチップモジュ−ル基板
を有し、この一方のマルチチップモジュ−ル基板に於け
る少なくとも一層の回路配線パタ−ンはその絶縁べ−ス
材と共に外部に伸長して他のマルチチップモジュ−ル基
板の一部の回路配線パタ−ンと連続的に接続されるよう
に構成したものである。
Therefore, in the multi-chip module aggregate board of the present invention, a plurality of LSI bare chips are mounted on a small high-density wiring board and modularized to mount a plurality of modules on a printed board. A multi-chip module board is provided, and at least one layer of circuit wiring patterns on one of the multi-chip module boards is extended to the outside together with the insulating base material to expand the other multi-chip module board. It is configured so as to be continuously connected to a part of the circuit wiring pattern of the substrate.

【0007】ここで、マルチチップモジュ−ル基板相互
を連続的に接続する為の上記手段は可撓性回路基板で構
成するのが好適である。
Here, it is preferable that the above-mentioned means for continuously connecting the multi-chip module boards to each other be composed of a flexible circuit board.

【0008】[0008]

【実施例】図1は本発明の一実施例によるマルチチップ
モジュ−ル集合基板を概念的に示す断面構成図であり、
図ではそれぞれ4層の回路配線導体層を有する2つのマ
ルチチップモジュ−ル基板A及びBの間を相互に接続し
た例を示す。
FIG. 1 is a sectional view conceptually showing a multi-chip module aggregate substrate according to an embodiment of the present invention.
The figure shows an example in which two multichip module boards A and B each having four circuit wiring conductor layers are connected to each other.

【0009】即ち、一方のマルチチップモジュ−ル基板
Aに於ける第一の層の回路配線パタ−ン1は可撓性回路
基板7として外部に伸長し、他のマルチチップモジュ−
ル基板Bに於ける第二の層の回路配線パタ−ン2と連続
的に接続されている。これらの両基板A,Bの最上層に
はLSIベアチップを搭載する為の半田バンプ3がそれ
ぞれ形成されている。
That is, the circuit wiring pattern 1 of the first layer on one of the multi-chip module boards A extends to the outside as a flexible circuit board 7, and the other multi-chip module board A.
The circuit wiring pattern 2 of the second layer on the circuit board B is continuously connected. Solder bumps 3 for mounting an LSI bare chip are formed on the uppermost layers of both substrates A and B, respectively.

【0010】また、上記両基板A,Bの各層の導体層
は、ヴァイアホ−ル4で電気的に導通されて高密度な三
次元回路を構成している。そして、両基板A,Bの底部
には、高密度に実装されるLSIベアチップからの発熱
を効果的に放熱する為の冷却用フィン5を有する放熱板
6が設けられている。
Further, the conductor layers of the respective layers of both the substrates A and B are electrically conducted by the via hole 4 to form a high-density three-dimensional circuit. A heat radiating plate 6 having cooling fins 5 for effectively radiating the heat generated from the LSI bare chips mounted at high density is provided on the bottoms of both substrates A and B.

【0011】図2は本発明の一実施例によるマルチチッ
プモジュ−ル集合基板の機器搭載状態の一例を示し、各
マルチチップモジュ−ル基板A,B,CにはLSIベア
チップ8が搭載され、また、それら各マルチチップモジ
ュ−ル基板A,B,C相互間を接続する可撓性回路基板
7は柔軟性に富むので、適当なスペ−サ9を使用しなが
ら図の如く可撓性回路基板7の部分で折曲げ積層して機
器にコンパクトに搭載することができる。
FIG. 2 shows an example of a device mounting state of a multi-chip module aggregate board according to an embodiment of the present invention. An LSI bare chip 8 is mounted on each of the multi-chip module boards A, B and C. Further, since the flexible circuit board 7 for connecting the respective multi-chip module boards A, B, C to each other is highly flexible, the flexible circuit board 7 as shown in FIG. The board 7 can be folded and laminated to be compactly mounted on the device.

【0012】[0012]

【発明の効果】本発明のマルチチップモジュ−ル集合基
板によれば、各マルチチップモジュ−ル基板を接続する
回路配線パタ−ン層は、マルチチップモジュ−ル基板を
構成している回路配線パタ−ンと一体に形成されるの
で、接続の為のスぺ−スを必要とせず小型化を達成でき
る。
According to the multi-chip module aggregate substrate of the present invention, the circuit wiring pattern layer for connecting the respective multi-chip module substrates has the circuit wiring which constitutes the multi-chip module substrate. Since it is formed integrally with the pattern, it is possible to achieve miniaturization without the need for a space for connection.

【0013】従って、搭載されたLSIベアチップ間の
距離を短縮し、モジュ−ル化されたことによって得られ
た基板の高速化を損なう虞がない。
Therefore, the distance between the mounted LSI bare chips is shortened, and there is no fear of impairing the speeding up of the substrate obtained by being modularized.

【0014】また、各マルチチップモジュ−ル基板間の
接続信頼性を高めることができる一方、折りたたんで積
層するような実装が可能となるので、電子機器の小型化
に大いに寄与する。
Further, the reliability of connection between the multi-chip module boards can be improved, while the mounting by folding and stacking is possible, which greatly contributes to downsizing of electronic equipment.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の一実施例によるマルチチップモジュ
−ル集合基板を概念的に示す断面構成図。
FIG. 1 is a sectional configuration view conceptually showing a multi-chip module aggregate substrate according to an embodiment of the present invention.

【図2】 本発明の一実施例によるマルチチップモジュ
−ル集合基板の機器搭載状態の一例を示す図。
FIG. 2 is a diagram showing an example of a device mounting state of a multi-chip module aggregate substrate according to an embodiment of the present invention.

【図3】 従来のマルチチップモジュ−ル基板を示す
図。
FIG. 3 is a diagram showing a conventional multi-chip module substrate.

【符号の説明】 A マルチチップモジュ−ル基板 B マルチチップモジュ−ル基板 1 回路配線パタ−ン 2 回路配線パタ−ン 3 半田バンプ 4 ヴァイアホ−ル 5 冷却用フィン 6 放熱板 7 可撓性回路基板 8 LSIベアチップ 9 スペ−サ[Explanation of reference symbols] A multi-chip module substrate B multi-chip module substrate 1 circuit wiring pattern 2 circuit wiring pattern 3 solder bumps 4 via holes 5 cooling fins 6 heat sink 7 flexible circuit Substrate 8 LSI Bare Chip 9 Spacer

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数個のLSIベアチップを小型の高密
度配線基板に搭載してモジュ−ル化したものをプリント
基板に搭載する為の複数のマルチチップモジュ−ル基板
を有し、この一方のマルチチップモジュ−ル基板に於け
る少なくとも一層の回路配線パタ−ンはその絶縁べ−ス
材と共に外部に伸長して他のマルチチップモジュ−ル基
板の一部の回路配線パタ−ンと連続的に接続されるよう
に構成したマルチチップモジュ−ル集合基板。
1. A plurality of multi-chip module boards for mounting a plurality of LSI bare chips on a small high-density wiring board and modularizing the same on a printed board. At least one layer of circuit wiring pattern on the multi-chip module substrate is extended to the outside together with the insulating base material and is continuous with a part of the circuit wiring pattern of another multi-chip module substrate. A multi-chip module aggregate substrate configured to be connected to.
【請求項2】 前記マルチチップモジュ−ル基板相互を
連続的に接続する為の上記手段を可撓性回路基板で構成
した請求項1のマルチチップモジュ−ル集合基板。
2. The multi-chip module aggregate substrate according to claim 1, wherein the means for continuously connecting the multi-chip module substrates to each other comprises a flexible circuit board.
JP18543093A 1993-06-29 1993-06-29 Multi-chip module assembly board Expired - Fee Related JP3216940B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18543093A JP3216940B2 (en) 1993-06-29 1993-06-29 Multi-chip module assembly board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18543093A JP3216940B2 (en) 1993-06-29 1993-06-29 Multi-chip module assembly board

Publications (2)

Publication Number Publication Date
JPH0722574A true JPH0722574A (en) 1995-01-24
JP3216940B2 JP3216940B2 (en) 2001-10-09

Family

ID=16170652

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18543093A Expired - Fee Related JP3216940B2 (en) 1993-06-29 1993-06-29 Multi-chip module assembly board

Country Status (1)

Country Link
JP (1) JP3216940B2 (en)

Also Published As

Publication number Publication date
JP3216940B2 (en) 2001-10-09

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