JPH0722535A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0722535A
JPH0722535A JP16305293A JP16305293A JPH0722535A JP H0722535 A JPH0722535 A JP H0722535A JP 16305293 A JP16305293 A JP 16305293A JP 16305293 A JP16305293 A JP 16305293A JP H0722535 A JPH0722535 A JP H0722535A
Authority
JP
Japan
Prior art keywords
semiconductor device
packaging
positioning
packaging substrate
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16305293A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Mori
義之 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16305293A priority Critical patent/JPH0722535A/en
Publication of JPH0722535A publication Critical patent/JPH0722535A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Abstract

PURPOSE:To improve the positioning accuracy of a semiconductor device upon its being packaged on a packaging substrate and hereby reduce failure packaging by providing a plurality of positioning holes in a package bottom facing to the packaging substrate upon packaging the semiconductor device. CONSTITUTION:Three for example of positioning holes 3 are provided on a bottom surface of a package facing to a packaging substrate 2 of a resin molding type semiconductor device 1. Provided positioning protrusions 4 are also provided on the packaging substrate 2 at the same locations as those of the positioning holes 3, the protrusions on the packaging substrate 2 are inserted into the positioning holes 3 of the semiconductor device 1 upon the semiconductor device 1 being packaged on the packaging substrate 2. whereby the semiconductor device 1 and the packaging substrate 2 are prevented from being displaced from each other owing to any vibration before the packaging for ensurance of accurate packaging. Further, three positioning portions are used, whereby the packaging is prevented from being reversely packaged for reduction of failure packaging.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
プリント基板へ実装する時に位置決め容易な表面実装型
半導体装置のパッケージの構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a surface mount type semiconductor device package which can be easily positioned when mounted on a printed circuit board.

【0002】[0002]

【従来の技術】最近の半導体装置の高機能化に伴ない、
半導体装置の外部導出リードの多ピン化および半導体装
置のパッケージの縮少化による外部導出リードのリード
間ピッチの縮少化より、半導体装置を実装基板上に実装
する際の位置決め精度が厳しくなってきている。その対
策とし、半導体装置のパッケージの裏面に複数個の突起
を設けたものが、特開昭62−52952号公報に記載
されている。
2. Description of the Related Art With the recent increase in functionality of semiconductor devices,
The accuracy of positioning when mounting a semiconductor device on a mounting board becomes stricter due to the reduction in the lead-to-lead pitch of the external leads due to the increase in the number of pins of the external leads of the semiconductor device and the reduction in the package of the semiconductor device. ing. As a countermeasure, a semiconductor device package having a plurality of protrusions on its back surface is disclosed in Japanese Patent Laid-Open No. 62-95252.

【0003】このパッケージは、図3に示すように、実
装基板2と相対するパッケージ本体10の裏面に位置決
め用の突起5を複数個設けたものであり、実装基板2に
位置決め用の穴6を設ける事により、半導体装置を実装
基板2に精度よく実装する事ができる。
As shown in FIG. 3, this package is provided with a plurality of positioning projections 5 on the back surface of the package body 10 facing the mounting board 2, and the mounting board 2 is provided with positioning holes 6. By providing the semiconductor device, the semiconductor device can be accurately mounted on the mounting substrate 2.

【0004】[0004]

【発明が解決しようとする課題】この従来のパッケージ
を用いた半導体装置では、実装する実装基板に位置決め
用の穴を設けないと実装できないという問題点があっ
た。又、実装すべきピン配列とは逆の方向(180°反
転)に実装される逆実装についての対策がされていない
ため実装不良を生じるという問題点もあった。
The semiconductor device using this conventional package has a problem that it cannot be mounted unless the mounting board to be mounted is provided with a positioning hole. In addition, there is a problem that a mounting failure occurs because no countermeasure is taken for reverse mounting in which the pin array is to be mounted in the opposite direction (180 ° inversion).

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置は実
装基板と相対するパッケージの底面部に複数個の位置決
め用の穴を設けたものである。
A semiconductor device according to the present invention is provided with a plurality of positioning holes on the bottom surface of a package facing a mounting substrate.

【0006】実装基板に位置決め用の突起を設けておけ
ば、半導体装置を実装基板に精度よく実装する事ができ
る。又、位置決め用の穴を3個にする事で逆実装の対策
も行なう事ができ、更に突起のない実装基板へも実装す
ることができる。
If the mounting board is provided with a positioning projection, the semiconductor device can be mounted on the mounting board with high accuracy. Further, by providing three positioning holes, it is possible to take measures against reverse mounting, and it is also possible to mount on a mounting board having no protrusion.

【0007】[0007]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0008】図1(a),(b)は本発明の一実施例の
正面図及び底面図である。
1A and 1B are a front view and a bottom view of an embodiment of the present invention.

【0009】樹脂モールド型の半導体装置1の実装基板
2と相対するパッケージの底面部には、例えば深さ約
0.5mm,幅約1mmの位置決め用の穴3が3個設け
てある。
Three holes 3 for positioning having a depth of about 0.5 mm and a width of about 1 mm are provided on the bottom surface of the package facing the mounting substrate 2 of the resin mold type semiconductor device 1.

【0010】実装基板2上にも位置決め用の穴3と同位
置に位置決め用の突起4を設けておくことにより、半導
体装置1を実装基板2へ実装する時は、半導体装置1の
位置決め用の穴3に実装基板2上の突起4を挿入するこ
とにより、実装前の振動等によるずれを防ぎ、精度よく
実装する事ができる。又、位置決め部を3ケ所にする事
により、逆実装の防止ができ、実装不良を低減させる事
ができる。尚、位置決め用の穴3の位置は図2のような
位置でも同様な効果がある。
When the semiconductor device 1 is mounted on the mounting substrate 2 by providing the positioning protrusion 4 on the mounting substrate 2 at the same position as the positioning hole 3, the semiconductor device 1 is positioned on the mounting substrate 2. By inserting the protrusions 4 on the mounting substrate 2 into the holes 3, it is possible to prevent displacement due to vibration or the like before mounting and to mount with high accuracy. Further, by providing the positioning portions at three positions, reverse mounting can be prevented and mounting defects can be reduced. The same effect can be obtained even if the position of the positioning hole 3 is as shown in FIG.

【0011】[0011]

【発明の効果】以上説明したように本発明の半導体装置
は、実装時に実装基板と相対するパッケージ底部に複数
個の位置決め用の穴を設ける事により、精度よく半導体
装置を実装する事ができ、又逆実装の防止もできるた
め、実装不良を低減させる事ができる効果がある。又、
実装基板側で位置決め用の突起の対応がない場合でも実
装する事が可能である。
As described above, the semiconductor device of the present invention can be mounted with high accuracy by providing a plurality of positioning holes at the bottom of the package facing the mounting substrate during mounting. Further, since reverse mounting can be prevented, it is possible to reduce mounting defects. or,
It can be mounted even if the mounting board does not have a positioning protrusion.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の正面図及び底面図。FIG. 1 is a front view and a bottom view of an embodiment of the present invention.

【図2】本発明の他の実施例の底面図。FIG. 2 is a bottom view of another embodiment of the present invention.

【図3】従来の半導体装置の一例の正面図。FIG. 3 is a front view of an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体装置 2 実装基板 3 穴 4 突起 5 突起 6 穴 10 パッケージ本体 1 semiconductor device 2 mounting substrate 3 hole 4 protrusion 5 protrusion 6 hole 10 package body

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 実装時に実装基板と相対する半導体装置
パッケージの底面部に位置決め用の穴を複数個設けた事
を特徴とする半導体装置。
1. A semiconductor device, wherein a plurality of positioning holes are provided in a bottom surface portion of a semiconductor device package facing a mounting substrate during mounting.
JP16305293A 1993-07-01 1993-07-01 Semiconductor device Pending JPH0722535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16305293A JPH0722535A (en) 1993-07-01 1993-07-01 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16305293A JPH0722535A (en) 1993-07-01 1993-07-01 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0722535A true JPH0722535A (en) 1995-01-24

Family

ID=15766263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16305293A Pending JPH0722535A (en) 1993-07-01 1993-07-01 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0722535A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091763A (en) * 2006-10-04 2008-04-17 Mitsubishi Electric Corp Semiconductor device, manufacturing method thereof, and manufacturing method of mounting substrate
CN106935516A (en) * 2015-12-30 2017-07-07 欣兴电子股份有限公司 The preparation method of the encapsulating structure of built-in type electronic building brick

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091763A (en) * 2006-10-04 2008-04-17 Mitsubishi Electric Corp Semiconductor device, manufacturing method thereof, and manufacturing method of mounting substrate
CN106935516A (en) * 2015-12-30 2017-07-07 欣兴电子股份有限公司 The preparation method of the encapsulating structure of built-in type electronic building brick
CN106935516B (en) * 2015-12-30 2019-05-03 欣兴电子股份有限公司 The production method of the encapsulating structure of built-in type electronic building brick

Similar Documents

Publication Publication Date Title
US5032088A (en) Guide structure for a multicontact connector
KR950034708A (en) Vertical package installed on both sides of the printed circuit board
JPH0722535A (en) Semiconductor device
JPH07297573A (en) Printed circuit board fixing mechanism
JPH05136325A (en) Semiconductor surface-mounting component
JPH0541169U (en) Printed board
JP4711529B2 (en) Liquid crystal display device
JP2629462B2 (en) Mounting structure of heat sink of integrated circuit package
JPH02111093A (en) Surface-mounting structure of semiconductor device
KR200198272Y1 (en) Carrier Guide
JP2790131B2 (en) IC carrier
JP2722639B2 (en) Integrated circuit package
JPH04129259A (en) Electronic parts
JPH0697355A (en) Stacked electronic component
JPH09129770A (en) Integrated circuit device
JPH08172247A (en) Circuit board
JPH09121081A (en) Mounting structure for printed wiring board
JPS63215060A (en) Semiconductor device
JP2000049258A (en) Smd ic device
JPH0536856A (en) Semiconductor device
JPH04334048A (en) Package for semiconductor device
JPH0239488A (en) Packaging structure of electronic part to printed board
JPH07142644A (en) Surface-mount integrated circuit package
JPH01260843A (en) Ic package
JPH0936283A (en) Semiconductor package and ic socket

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19960507