JPH0722397B2 - Image encoding / decoding device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding / decoding device used for digitally coding and transmitting a moving image, and more particularly to improving coding efficiency and facilitating detection of breaks in coding information to ensure transmission error detection. The present invention relates to an image encoding / decoding device according to the above.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a conventional image coding / decoding apparatus, in which 1 is an input digital image signal and 2 is an input digital image signal 1 (K is an integer of 2 or more). ) Blocks that are grouped into blocks /
A raster converter, 3 is an input signal sequence grouped into K units, 4 is a difference signal sequence between an input signal sequence in a frame memory 12 described later and a past signal sequence 4 located at the same position on the image, and 6 is A threshold value used for significant / insignificant discrimination, 7 is a motion detection block encoder for performing significant / insignificant discrimination based on the threshold value 6, and block-encoding only a significant difference signal sequence, and 8 is a motion It is a significant difference signal sequence block coded signal output from the detection block encoder 7.

Reference numeral 9 is a block decoder which decodes the significant block data included in the significant difference signal sequence block coded signal 8 and outputs a decoded difference signal sequence 10, and 11 is a signal sequence 4 outputted from the frame memory 12. A decoded signal sequence obtained by adding the decoded differential signal sequence 10 and supplied to the frame memory 12.

Numeral 13 is a code allocator which outputs a code allocation signal 14 by variable length coding the significant difference signal sequence block coded signal 8 output from the motion detection block coder 7, and 15 is a code allocator 13. , 16 is an output of the buffer memory 15, and 17 is a frame configuration circuit connected to the output side of the buffer memory 15, which outputs to a transmission frame transmission line 18.

Next, the operation will be described. When the input digital image signal 1 is supplied, the block / raster converter 2 outputs the input signal sequence 3 by dividing the input digital image signal 1 into K blocks. Then, the past signal series 4 at the same position on the image of the frame memory 12 is subtracted from the input signal series 3 to obtain the difference signal series 5, and then the motion detection block encoder 7 sets a threshold value 6 By performing the significant / unintentional discrimination based on the above, only the significant difference signal sequence is output as the significant difference signal sequence block coded signal 8.

The significant difference signal sequence block coded signal 8 is decoded in the block decoder 9 to obtain a decoded difference signal sequence 10, and the decoded signal sequence 4 is added to the past signal sequence 4. 11 is required.

Then, the decoded signal sequence 11 is supplied to the frame memory 12 to update the contents of the block so that the contents are matched by transmission and reception.

Next, the significant difference signal sequence block coded signal 8 consisting of the significant / unconscious result and the significant block coding result is code-length-coded by the code assigner 13 for each cluster in block units. It is stored in the buffer 15 as the signal 14. The contents of the buffer 15 are read at a constant speed so that the speed is smoothed, and the output signal 16 is supplied to the frame composing circuit 17 to compose a transmission frame to form the transmission line 1.
8 is sent. FIG. 10 shows an example of encoding.

[0009]

Since the conventional image coding / decoding apparatus is configured as described above, it is not sufficient to prevent the propagation of a transmission error, and the error is transmitted via the contents of the frame memory. There is a problem that the image is propagated and the decoded image may be disturbed.

The present invention has been made to solve the above problems, and an object thereof is to obtain an image coding / decoding device capable of easily detecting a transmission path error.

[0011]

An image coding / decoding apparatus according to the present invention, when receiving a significant / unconscious code assignment result and a significant block data code assignment result, performs a significant / unsigned operation for each video frame unit. After the unconscious codes are sequentially decoded and stored in the buffer memory, the number of significant blocks in one video frame is obtained, and then the number of significant blocks and the number of blocks corresponding to the significant block data code assignment result are examined. Meanwhile, the decoding is performed and the data is stored in the buffer memory.

[0012]

According to the image coding / decoding apparatus of the present invention, the number of significant blocks and the number of blocks corresponding to the significant block data code assignment result are checked while the decoding is performed and the decoding is stored in the buffer memory. It becomes easy to detect transmission errors.

[0013]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an image encoding apparatus. In the figure, 101 is a scan converter which divides an input digital image signal 201 into blocks for every K pieces,
A significant difference signal sequence 102 is determined based on a threshold value 300 of whether the difference signal sequence 203 between the signal sequence 204 on the same image position in the frame memory 103 and the latest input signal sequence 202 is significant or unconscious. It is a block coder that block-codes only one.

Reference numeral 103 is a frame memory for storing at least one frame of an image signal, and 104 is a block-encoded signal sequence 2 output from the block encoder 102.
It is a block decoder that decodes 06 to obtain a decoded differential signal sequence 207.

Reference numeral 105 denotes a significant / insignificant code assigner for performing variable length coding by further summing the significant / unconscious results for each M, 106 denotes a significant block code assignor for variable length coding a significant block coded signal, Numeral 107 is a buffer for temporarily storing the non-uniformly input significant / insignificant code allocation results and performing rate balancing, and 108 is a buffer for temporarily storing non-uniformly input significant block code assignment signals to perform rate balancing. , 109 are header-added frame configuration circuits that read information from the buffers 107 and 108, add headers and perform transmission.

FIG. 2 shows a significant / insignificant code assigner 1 shown in FIG.
5 is a block diagram showing a concrete example of a buffer 107 and a buffer 107. In the figure, 110 is a blocking circuit for grouping significant / unconscious signals into M blocks and further dividing them into blocks.
Reference numeral 11 is a pattern determination circuit that determines whether to encode a continuous number of patterns in which the pattern of a block is highly likely to be speed-read or whether to encode the combination, and 112 controls the encoding allocation processing. An encoding control circuit, 113 is a run counter for counting the number of consecutive patterns, 1
Reference numeral 14 is a pattern coding circuit for allocating codes to patterns, 115 is a run coding circuit for allocating a continuous number of codes, 116 is a gate for inhibiting output until the code allocation processing is completed, and 117 is code allocation processing completed. This is a select for selecting a route that has been made.

FIG. 3 is a block diagram showing an image decoding apparatus. In the figure, reference numeral 119 is a header detection frame disassembling circuit for detecting a header and detecting the beginning of a video frame.
20 is a significant / insignificant decoder for decoding significant / insignificant information, 121 is a significant block decoder for decoding significant blocks, 122 is a temporary storage of significant / insignificant information decoding results, and synchronization with significant block decoding results A buffer that takes
A buffer 123 temporarily stores the significant block decoding result in contrast to the buffer 122 and synchronizes with the significant / insignificant information decoding result, and a gate 124 reads a significant block decoded signal from the buffer 123 according to the significant / insignificant information decoding result. .

Reference numeral 125 designates a significant block as a differential signal series 20.
7 is a block decoder for decoding, 126 is a frame memory for storing at least one frame of a past image, 127
Is a scanning inverse converter that inversely converts a decoded signal 208 obtained by adding the differential signal series 207 and the corresponding signal series 204 on the past image output from the frame memory 126 into a raster scan.

FIG. 4 shows in detail the header detection frame decomposing circuit 119 shown in FIG. 3. The frame decomposing circuit shown as 119 is a part of the header detecting frame decomposing circuit 119 shown in FIG. Decoding control circuit for controlling the decoding process, 130 is a variable length decoding circuit for decoding significant / insignificant coded information, 131 is a run length buffer for storing the number of consecutive patterns, 132 is a pattern buffer for storing patterns, and 133 is A run length subtraction counter for repeatedly reading the same pattern for a continuous number, 13
4 is a pattern latch that holds the same pattern for the number of times of repeated reading, and 135 is a pattern of M units
It is an inverse blocking circuit that decomposes into individual units.

Next, the operation will be described. First, the input digital image signal 201 is divided into K blocks by the scan converter 101 to form a signal series 202. Then, from this signal series 202, the past signal series 204 at the same position on the image stored in the frame memory 103
Is subtracted, the difference signal sequence 203 is obtained.

Next, with respect to this differential signal sequence 203,
The block encoder 102 discriminates significant / insignificant on the basis of the threshold value 300, and the significant signal difference signal sequence 203
Only block code. The block decoder 104 decodes the block coded signal 206 to obtain a decoded differential signal sequence 207, which is added to the past signal sequence 204 to obtain a decoded signal sequence 208. Then, the decoded signal sequence 208 is supplied to the frame memory 103 to update the contents thereof so that the contents of the transmitted and received frame memories match.

On the other hand, the significant / unconscious signal 205 is further grouped by M in the blocking circuit 110 shown in FIG. 2, and whether the continuous number is coded or the combination is coded in the pattern determination circuit 111. Judge the other.

The run counter 113 counts the consecutive numbers for each specific combination, and the run encoding circuit 115 counts the consecutive numbers at the time when the sequences of the same pattern are separated.
Send to. The run coding circuit 115 performs variable length coding on a continuous number. The pattern coding circuit 114 also performs variable length coding on the combination itself.

The gate 116 inhibits the output until the encoding is completed, and the select 117 selects the encoded data and writes it in the buffer 107. At the same time 1
While the video frame is being encoded, the significant block code assignor 106 converts the significant block coded signal 206 into a variable length code and writes it into the buffer 108. When the encoding process of one video frame is completed, the header addition frame configuration circuit 109 first adds a header to the significant / unconscious information 210 of the entire one video frame and transmits the information, and finally adds a special code.
Next, a header is added to the significant block data 211 of the entire one video frame for transmission, and the entire one video frame is transmitted.
01 is ended.

5 to 8 show examples of the above encoding. next,
Decoding will be described with reference to FIGS. The transmitted data 212 is subjected to header detection frame decomposition circuit 119.
It is separated into encoded information only by processing by
The output signal is first decoded by the significant / involuntary decoder 120 into a combination of significant / unconscious signals for the entire one video frame and the continuous number 219 is decoded, and the pattern buffers 132,
It is stored in the run length buffer 131.

Detection of a special code indicating a division of transmission information 2
This operation is continued until 13, and then the significant block decoder 121 decodes the significant block data by the number of all significant blocks of one video frame obtained by decoding the significant / unconscious information, and stores the significant block data in the buffer 123. . Finally, when the special code 213 indicating the end of the data is detected, the reception of one video frame is completed. Therefore, the occurrence of a transmission error can be known by confirming that the number of significant blocks known from the significant / unconscious signal and the number of significant blocks known from the significant block encoded data match. This is because the number of significant blocks known from the significant block coded data is likely to be incorrect when a transmission error occurs.

Thereafter, the contents of the pattern buffer 132 are transferred to the pattern latch 13 in synchronization with the video data decoding clock.
4 and holds the contents of the pattern latch 134 while the run length subtraction counter for the continuous number indicated by the contents of the run length buffer 131 is counting.

Next, the contents thus read are decomposed by the deblocking circuit 135, and the significant / unconscious signal 2
Call for 05. According to the significant / unconscious signal 205,
The significant block data 206 is read from the buffer 123. However, in case of no intention, the output is prohibited by the gate 124.

The significant block data 206 is decoded by the block decoder 125 to obtain a decoded differential signal sequence 207, and the past relevant signal sequence 204 in the frame memory 126 is obtained.
A signal sequence 208 is obtained by adding The contents of the frame memory 126 are updated by the decoded signal sequence 208 to match the contents on the transmitting side, and the scanning inverse converter 127 decomposes K blocks to obtain a signal digital image signal. After repeating the above for one video frame, the next video frame is decoded.

Example 2. Although the significant block is block-encoded in the above embodiment, the same effect as that of the above embodiment can be obtained even if the significant block is encoded for each pixel.

[0031]

As described above, according to the present invention, the amount of significant / unconscious information can be reduced with a simple configuration, and transmitted information can be surely decoded so that a transmission path error can be image-decoded. Since the detection is performed before, there is an effect that the contents of the frame memory can be prevented from including an error.

[Brief description of drawings]

FIG. 1 is a block diagram showing an image coding apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a specific example of a significant / insignificant code assigner and a buffer in FIG.

FIG. 3 is a block diagram showing an image decoding apparatus according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a specific example of the significant / unconscious information encoder of FIG.

FIG. 5 is an explanatory diagram showing a blocking operation.

FIG. 6 is an explanatory diagram illustrating an operation of significant / unconscious information.

FIG. 7 is a pattern diagram showing an example of encoding / decoding of significant / unconscious information.

FIG. 8 is a transmission frame diagram showing a transmission frame after a header-added frame structure.

FIG. 9 is a block diagram showing a conventional image encoding device.

FIG. 10 is an explanatory diagram explaining an encoding operation.

[Explanation of symbols]

101 Scan Converter 102 Block Encoder 103 Frame Memory 104 Block Decoder 105 Significant / Insignificant Code Assigner 106 Significant Block Code Assigner 107, 108 Buffer 109 Header-added Frame Configuration Circuit (Frame Configuration Circuit) 120 Significant / Insignificant Decoding 121 Significant block decoder 125 Block decoder 126 Frame memory 127 Scan inverse converter

Claims (1)

[Claims] 1. A first frame memory for storing a digital image signal for at least one video frame, and an input signal sequence by dividing an input digital image signal into K units (K is an integer of 2 or more). A scan converter,
Significant difference signal by identifying significant / insignificant on the basis of a threshold value with respect to the difference signal series obtained by calculating the difference between the blocked input signal series and the output signal series on the image in the frame memory A block encoder for block-encoding a sequence, and decoding the difference signal sequence from an output signal of the block encoder, and adding the output signal to the signal sequence in the first frame memory. Block decoder for updating the content of the signal sequence in the first frame memory, and the significant / unconscious result as M
A significant / insignificant code assigner that performs variable length coding for each number (M is an integer of 2 or more), a significant block code assigner that encodes the significant difference signal sequence coded signal, and the significant / unconscious code An encoding unit including a frame configuration circuit for transmitting an allocation result and a significant block data code allocation result, a significant / insignificant decoder for variable-length decoding the significant / unconscious code, and a variable-length decoding for the significant block code assignment result. Significant block decoder, a second frame memory for storing a digital image signal for at least one video frame, a significant block is decoded into a difference signal sequence, and the difference is read from a corresponding position in the second frame memory. A block decoder for adding the read digital image signal to update the contents of the corresponding position in the second frame memory; An image encoding / decoding apparatus including a decoding unit composed of a scanning inverse converter for performing scanning inverse conversion on the decoded signal obtained, when receiving the significant / unconscious code assignment result and the significant block data code assignment result. Is to decode the significant / unconscious code for each video frame unit and store it in the buffer memory to obtain the number of significant blocks of one video frame. The number of significant blocks and the block corresponding to the significant block data code allocation result An image encoding / decoding device characterized by performing coincidence with the number of pixels, performing decoding, and storing in a buffer memory.