JPH0547030B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image encoding/decoding device used for digitally encoding and transmitting moving images, and particularly to improving encoding efficiency and detecting breaks in encoded information. The present invention relates to an image encoding/decoding device that facilitates and ensures transmission error detection.

[Conventional technology]

FIG. 9 is a block diagram showing an example of the main part of an inter-frame differential encoding device using a block encoding method commonly used in the past. In the figure, 1 is an input digital image signal, 2 is an input digital image signal
A raster/block converter that converts the data into K blocks (K is an integer of 2 or more), 3 is an input signal sequence that is grouped into K blocks, and 4 is an input signal sequence in the frame memory 12, which will be described later. A past signal sequence at the same position on the image, 5 is a difference signal sequence between the input signal sequence 3 and the past signal sequence 4, 6 is a threshold value used for significant/insignificant identification, and 7 is a significant signal sequence. / A motion detection block encoder that performs random identification based on a threshold value 6 and blocks encodes only significant difference signal sequences; 8 is a significant difference signal sequence block output from the motion detection block encoder 7; 9 is a significant difference signal sequence block decoder that decodes significant block data included in the block coded signal 8 and outputs a decoded difference signal sequence 10; 11 is a signal sequence 4 output from the frame memory 12; , a decoded signal sequence obtained by adding the decoded difference signal sequence 10, and is supplied to the frame memory 12. 13 is a code allocator that outputs a code allocation signal 14 by variable length coding the significant difference signal sequence block coded signal 8 output from the motion detection block encoder 7;
15 is a buffer memory connected to the code allocator 13; 16 is the output of the buffer memory 15; 17
is a frame configuration circuit connected to the output side of the buffer memory 15, and is a frame configuration circuit connected to the output side of the buffer memory 15, and is connected to the transmission frame transmission line 1.
Output to 8.

In the circuit configured in this manner, when input digital image signal 1 is supplied, raster/block converter 2 converts this input digital image signal 1 into K
By dividing the input signal sequence S _l into blocks,
Output as 3. This input signal sequence S _l 3 is sent to the motion detection block encoder 7 after the past signal sequence P _l 4 located at the same position on the image in the frame memory 12 is subtracted to obtain a differential signal sequence E _l 5. Significance/insignificance is discriminated based on the threshold value Tθ6, so that only the significant difference signal sequence is output as the significant difference signal sequence block encoded signal 8. Then, this significant difference signal sequence block encoded signal 8 is decoded in a block decoder 9, whereby the decoded difference signal sequence E∧
_l 10 is obtained, and the decoded signal sequence S∧ _l 11 is obtained by adding it to the past signal sequence P _l 4. This decoded signal sequence S∧ _l 11 is then supplied to the frame memory 12 to update the contents of the block, thereby making the contents consistent between transmission and reception.

Next, the significant difference signal sequence block encoded signal 8 consisting of the significant/unconscious classification result and the significant block encoding result is variable-length encoded for each cluster in block units in the code assigner 13, thereby producing a code assignment signal. 14 in the buffer 15.
The contents of this buffer 15 are read out at a constant speed to smooth the speed, and the output signal 16 is supplied to a frame configuration circuit 17 to configure a transmission frame and send it to a transmission line 18. FIG. 10 shows an encoding example.

[Problem that the invention seeks to solve]

However, in the above-mentioned conventional image encoding device, in order to prevent the propagation of transmission path errors during decoding, since significant/insignificant information occupies a large proportion of the total amount of information, certain Since it is necessary to insert a special code into each block, there is a problem in that the amount of fixed information increases.

The present invention was made in order to solve the above-mentioned problems, and it is an object of the present invention to provide an image encoding/decoding device that facilitates the detection of transmission path errors.

[Means for solving problems]

Therefore, the image encoding/decoding device according to the present invention collectively encodes the significant/unconscious classification results for each M large blocks, and adds a header to the data before decoding the significant block data. This makes it possible to easily detect transmission errors by decoding significant/unconscious information and determining the number of significant blocks.

[Effect]

In the image encoding/decoding device configured in this way, the significant/unconscious results are encoded into M pieces, and at the same time, processing is performed in parallel with the encoding of significant blocks. In addition to improving encoding efficiency, the break in encoded information is reliably detected as the header is added, making it easier to detect transmission errors.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of an image encoding device according to the present invention, in which 101 is a raster/block converter that converts an input digital image signal 201 into K blocks, and 102 is a raster/block converter. The significance/unconsciousness of the differential signal sequence 203 between the signal sequence 204 on the same image position in the frame memory 103 and the latest input signal sequence 202 is determined based on the threshold value 300, and significant differential signal sequences are blocked. Motion detection block encoder for encoding, 10
3 is a frame memory that stores at least one frame of image signals; 104 is a block decoder that decodes the block encoded signal sequence 206 output from the motion detection block encoder 102 to obtain a decoded difference signal sequence; Reference numeral 105 denotes a significant/insignificance code allocator that performs variable length coding on the M significant/insignificant classification results, 106 a significant block code allocator that performs variable length coding on the significant block coded signal, and 107 a nonsignificant code allocator. A buffer 108 temporarily stores significant/insignificant code assignment results that are input evenly and performs speed smoothing; 108 a buffer that performs speed smoothing by temporarily storing significant block code assignment signals that are input unevenly; 109; is a header-adding frame configuration circuit that reads buffers and information from the buffers at a constant speed, adds headers, and transmits the data.

Figure 2 shows the significant/insignificant code assigner 1 shown in Figure 1.
05 and the buffer 107. In the figure, 110 is a blocking circuit that collects M significant/unconscious signals and further blocks them, and 111 indicates the possibility that the block pattern is continuous. 112 is a coding control circuit that controls coding allocation processing; 113 is a run counter that counts the number of consecutive patterns; 112 is a coding control circuit that controls the coding allocation process; , 114 is a pattern encoding circuit that assigns codes to a pattern, 115 is a run encoding circuit that assigns a continuous number of codes, 1
16 is a gate that prohibits output until the code assignment process is completed; 117 is a select that selects the path for which the code assignment process has been completed.

Figure 3 shows the configuration of the image decoding device.
119 is a header detection frame decomposition circuit that detects a header and detects the beginning of a video frame; 120
121 is a significant block decoder that decodes significant blocks; 122 temporarily stores the decoding results of significant/insignificant information and synchronizes them with the decoding results of significant blocks; A buffer 123 is symmetrical to 122 for temporarily storing the significant block decoding results and synchronizing with the significant/insignificant information decoding results. 124 is a significant/insignificant buffer.
A gate reads a significant block decoded signal from the buffer according to the result of decoding the meaningless information, 125 is a block decoder that decodes the significant block into a differential signal sequence 207, 126 is a frame memory that stores at least one frame of past images, and 127 is a differential signal. The corresponding signal sequence 2 on the past image output from the sequence 207 and the frame memory 126
This is a raster/block inverse converter that inversely converts the decoded signal 208 obtained by addition with 04 to raster scanning.

FIG. 4 shows the header detection frame decomposition circuit 119 shown in FIG. 3 in detail. The frame decomposition circuit 119' is a part of the header detection frame decomposition circuit 119 shown in FIG. A decoding control circuit that controls unintentional decoding processing, 1
30 is a variable length decoding circuit for decoding significant/insignificant encoded information, 131 is a run length buffer for storing the number of consecutive patterns, 132 is a pattern buffer for storing patterns, and 133 is for storing the same pattern by the consecutive number of patterns. A run length subtraction counter for repeated reading; 134 a pattern latch for holding the same pattern for the number of repeated readings; 135;
is a deblocking circuit that decomposes M patterns into one pattern.

The encoding operation will be explained below based on FIGS. 1 and 2. First, the input digital image signal 201 is converted into K by the raster/block converter 101.
The signal sequence 202 is created by blocking each signal.
Then, this signal series 202 is obtained by subtracting the past signal series 204 at the same position on the image read from the frame memory 103.
A difference signal sequence 203 is obtained. Next, the motion detection block encoder 102 performs a significant/signal determination based on a threshold value 300 on this difference signal sequence 203.
Distinguish the difference signal sequence 20 of the significant block.
3 is block encoded. The block decoder 104 decodes the block encoded signal 206 to obtain a decoded difference signal sequence 207, and adds this to the past signal sequence 204 to obtain a decoded signal sequence 208. This decoded signal sequence 208 is then supplied to the frame memory 103 to update its contents so that the contents of the transmitted and received frame memories match.

On the other hand, the significant/unconscious signal 205 is further grouped into M pieces in the blocking circuit 110 shown in FIG. Determine whether or not.

The run counter 113 counts the consecutive numbers for each specific combination, and the encoding circuit 115 calculates the consecutive numbers when the same pattern breaks up.
Send to. The run encoder 115 performs variable length encoding on consecutive numbers. In addition, the pattern encoding circuit 1
14 encodes the combination itself into a variable length code.

The gate 116 prohibits output until the encoding is completed, and the selector 117 selects the encoded data and writes it into the buffer 107. At the same time, during the period when one video frame is being encoded, the significant block code allocator 1
06 converts the significant block encoded signal 206 into a variable length code 209 and writes it into the buffer 108. When the encoding process for one video frame is completed, the header addition frame configuration circuit 109 first adds a header to the significant/unconscious information 210 of the entire video frame and transmits it, and finally adds a special code. Next, a header is added to the significant block data 211 of one entire video frame and transmitted, and the transmission 201 of one entire video frame is completed.

Examples of the above encoding are shown in FIGS. 5, 6, 7, and 8.

Next, decoding will be explained based on FIGS. 3 and 4. The transmitted data 212 is processed by the header detection frame decomposition circuit 119 to separate it into encoded information only, and the output signal is first processed by the significant/unconscious decoder 120 to separate significant/unconscious signals of one entire video frame. The combinations and consecutive numbers 219 are decoded and each pattern buffer 1 is decoded.
32, store it in the run length buffer 131. This operation continues until a special code indicating a break in the transmitted information is detected 213, and then the significant block decoder 121 decodes significant block data by the number of significant blocks in one entire video frame obtained by decoding the significant/unconscious information. It is decoded and stored in the buffer 123. Finally, when the special code 213 indicating the end of data is detected, the reception of one entire video frame is completed. Thereafter, the contents of the pattern buffer 132 are written to the pattern latch 134 in synchronization with the video data decoding clock, and the pattern latch 131 is Retains the contents of. Next, the contents read out in this way are decomposed by the deblocking circuit 135, and significant/
An unconscious signal 205 is obtained. According to this significant/insignificant decoded signal 205, significant block data 206 is read from the buffer 123. However, if it is unexpected, the output is prohibited by the gate 124. This significant block data 206 is transferred to the block decoder 12.
5 to obtain a decoded difference signal sequence 207, which is added to the previous corresponding signal sequence 204 in the frame memory 126 to obtain a decoded sequence 208. This composite signal sequence 208 updates the contents of the frame memory 126 to match the contents with the transmitting side, and the raster/block inverse converter 12
7, the K groups are decomposed to obtain a decoded digital image signal. After repeating the above steps for one video frame, the next video frame is decoded.

In the above embodiment, significant blocks are encoded as blocks, but the same effects as in the embodiments described above can be achieved even when significant blocks are encoded pixel by pixel.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to reduce the amount of significant/unconscious information with a simple configuration, and also to reliably decode sent information and detect transmission path errors before image decoding. This has an excellent effect in that it is possible to prevent errors from being included in the contents of the frame memory.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image encoding device according to the present invention, FIG. 2 is a block diagram showing a specific example of the significant/unconscious information encoder shown in FIG. 1, and FIG. FIG. 4 is a block diagram of the image decoding device according to the invention, and FIG. 5 is a block diagram showing a specific example of the significant/unconscious information encoder shown in FIG.
Figure 6 is an explanatory diagram showing the operation of blocking, Figure 6 is a diagram explaining the operation of significant/unconscious information, Figure 7 is an example of encoding/decoding of significant/unconscious information, and Figure 8 is a header. FIG. 9 is a block diagram showing an example of a conventional image encoding device, and FIG. 10 is a diagram for explaining the encoding operation in FIG. 9. In the figure, 101 is a raster/block converter;
2 is a motion detection block encoder, 103 is a frame memory, 104 is a block decoder, 105
106 is a significant block code assigner, 107 and 108 are buffers, 109
110 is a block forming circuit; 111 is a pattern determination circuit; 113 is a header addition frame configuration circuit;
is a run counter, 114 is a pattern encoding circuit,
115 is a run encoding circuit, 116 is a gate, 11
7 is a select, 119 is a header detection frame decomposition circuit, 120 is a significant/insignificant decoder, 121 is a significant block decoder, 122 and 123 are buffers,
124 is a gate, 125 is a block decoder, 1
26 is a frame memory, 127 is a raster/block inverse converter, 129 is a decoding control circuit, 130 is a variable length decoding circuit, 131 is a run length buffer, 13
2 is a pattern buffer, 133 is a run length subtraction counter, 134 is a pattern latch, and 135 is a deblocking circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. Frame memory that always stores at least one video frame of digital image signals, and raster/block conversion that creates an input signal series by grouping the input digital image signals into K blocks (K is an integer of 2 or more). The difference signal sequence obtained by calculating the difference between the blocked input signal sequence and the output signal sequence at the same position on the image in the frame memory is determined based on a threshold value.
A motion detection block encoder that blocks encodes only a significant differential signal sequence by identifying non-significance; a block decoder that updates the contents of the signal sequence in the frame memory by adding it to the signal sequence in the frame memory; a significant/unconscious code allocator that performs variable length encoding; a significant block code allocator that performs variable length encoding of the significant difference signal sequence encoded signal;
A buffer memory for separately storing the significant/unconscious code assignment results and the significant block data code assignment results, and a buffer memory for dividing the contents of the buffer memory into units of a certain word length and adding headers before transmission. An image encoding/decoding device comprising a header-adding frame configuration circuit.