JP2929591B2 - Image coding device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image encoding device. 2. Description of the Related Art Conventionally, adaptive dynamic range coding has been known as a method for coding an image signal with high efficiency (for example, Japanese Patent Application Laid-Open No. Sho 61-1444989). In this adaptive dynamic range coding, all pixels constituting a screen are divided into blocks each consisting of several pixels, and for each of the blocks, the constituent pixels are linearly quantized between a maximum value and a minimum value of the pixels, And the dynamic range value (difference between the maximum value and the minimum value) and the quantized value of each pixel. In this coding method, when the dynamic range in a block is small, the quantization step of each pixel is finer. On the contrary, when the dynamic range is large, the quantization step is coarse. Can be appropriately quantized according to. Also, with this conventional encoding method, the number of image transmission bits can be greatly reduced. For example, 8
In the case where bit image data is encoded in units of blocks of 3 × 6 pixels, if the number of quantization bits of each pixel in the block is 4 bits, the number of bits per block before compression (encoding) Is 144 (= 3 × 6 × 8), but after compression, each pixel data is 72 (= 3 × 6 × 8).
4) There are 16 (= 8 × 2) bits for the maximum value and the minimum value, a total of 88 bits, which can be compressed to about half. [Problems to be Solved by the Invention] However, in this conventional encoding method, each pixel value is quantized by equally dividing the dynamic range in each block, and thus the distribution of each pixel value is Is not considered at all, and therefore, depending on the image, the quantization error of each pixel may become extremely large. Therefore, the present invention improves on the conventional block coding method,
It is an object of the present invention to provide an image encoding device for reducing a quantization error of pixel data. [Means for Solving the Problems] An image encoding apparatus according to the present invention includes: a block forming unit that divides digital image data into blocks each including a predetermined number of samples; and an image data block formed by the blocking unit. Encoding means for encoding the image data by quantizing the image data between a maximum value and a minimum value, and a decoding value obtained by decoding the encoded data encoded by the encoding means and the blocking means. Error detection means for detecting a quantization error between the true value of the image data and the block unit, according to the detection result of the error detection means, the encoded data encoded by the encoding means, the block Changing means for changing the quantization error in units so as to reduce the quantization error. Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an encoding apparatus according to one embodiment of the present invention. Although the television signal used in the present embodiment complies with the NTSC system, the present invention can be applied to a device that encodes a television signal conforming to another system. In FIG. 1, an NTSC television signal input from an input terminal 9 is sampled by an A / D conversion circuit 10 at a sampling frequency 4f _SC which is four times the carrier frequency f _SC , and is, for example, 8 bits per pixel. It forms a quantized digital television signal and forms a block circuit 11
Supplied to The blocking circuit 11 is composed of a memory capable of storing the digital television signal for one field screen, a write / read control circuit for the memory, and the like. S ₁ , S in the direction
_{2, S 3, S 4,} S 17, S 18, ... temporarily stored in the memory of the digital television signal supplied serially in the order of, then, each pixel data from the memory S _1, S ₂ , S ₃ , S ₄ , S ₅ , S ₆ ,
., S ₁₅ , S ₁₆ , S ₁₇ , S ₁₈ ,..., S ₃₁ , S ₃₂ are read out in this order, so that the digital television signal
As shown by, four pixels in the horizontal direction and four lines in the vertical direction surrounded by a broken line are divided into one block unit, and are divided and output. FIG. 2 shows the case of interlaced scanning, and the line indicated by the dashed line indicates the scanning line of another field. Reference numeral 12 denotes a circuit for calculating the maximum value and the minimum value in the block of interest, which can be easily realized as software or hardware. The method implemented by hardware is composed of a comparison circuit and a hold circuit. For example, in the case of calculating the maximum value, the larger value of the two inputs may be held and passed to the next stage, and the minimum value may be calculated. Conversely, in the case of calculation, the smaller of the two inputs may be held and passed to the next stage. Thereby, data of the maximum value and the minimum value is finally obtained. Reference numeral 14 denotes a block encoding circuit, 16 denotes a decoding circuit 18, and an error calculating circuit. Each pixel value of the block output from the blocking circuit 11 is also applied to these circuits 14, 18. The block coding circuit 14 divides the maximum value and the minimum value into n (integer of 2 or more) based on the maximum value and the minimum value calculated by the maximum value / minimum value calculation circuit 12, and determines whether each pixel data is Check if it belongs to a parcel. The numerical value indicating the section to which it belongs is called an index. Thus, for example, 8 bits,
Pixel data quantized at 256 levels can be represented by a maximum value, a minimum value, and 2-bit pixel information for each pixel block. The details of the block encoding circuit will be described later. In a conventional transmission apparatus, these data are transmitted as they are, but in the present embodiment, the following processing is further performed. That is, the decoding circuit 16 decodes the index by the block coding circuit 14, and the error calculation circuit 18 calculates the error between each decoded pixel data and the true value of each pixel data from the blocking circuit 11. The shift amount calculating circuit 20 determines the shift amounts of the maximum value and the minimum value in a direction to cancel the error according to the error amount calculated by the error calculating circuit 18. For example, if the sum of the errors is a large negative number, the maximum value and the minimum value in the pixel block are shifted to the plus side, that is, the shift amount is set to a positive value. The value and the minimum value are shifted to the negative side, that is, the shift amount is set to a negative value. For example, the correspondence between input and output values as shown in Table 1 may be stored in the read-only memory in advance. However, Table 1 is an example in which each block includes 4 × 4, that is, 16 pixels. In this example, since 16 pixels are included in one block, if the shift amount of the maximum value and the minimum value is set to 1, the sum of errors in one block changes by about 16, and the maximum value and the minimum value Considering that the boundary value changes due to the shift and the error does not increase even if the pixel of interest belongs to another section, the relationship between the sum of the error and the shift amount is determined. I have. When determining the shift amount, not only the sum of the errors,
The shift amount may be determined based on the information indicating how many decoded values have errors in the block, or in consideration of the sum of the errors. Then, a more accurate code can be transmitted. The adding circuit 22 modifies the maximum value and the minimum value calculated by the maximum value / minimum value calculating circuit 12 by adding the shift amount. FIG. 3 shows an example of the modification.
The small circles in the figure are the pixel values, and at the time of decoding, these are decoded into intermediate values of the respective divided regions. FIG. 3A shows the state before the modification, and FIG. 3B shows the state after the modification. As shown in FIG. 3 (a), when the sum of errors at the time of decoding is a positive value before the modification, the maximum value and the minimum value are shifted to the plus side as shown in FIG. 3 (b). As a result, the sum of errors during decoding is reduced. The block encoding circuit 24 calculates and outputs an index in accordance with the modified maximum value and minimum value from the adding circuit 22, similarly to the block encoding circuit 14. The modified maximum value and minimum value output from the addition circuit 22 and the index output from the block encoding circuit 24 are transmitted to another device or a remote place. FIG. 4 shows details of the block encoding circuit 14. However, in order to simplify the explanation, the number of divisions n between the maximum value and the minimum value
Indicates the case of 4. Also, the block coding circuit 24
May have the same structure. Reference numeral 30 denotes an input terminal for each pixel data in the block, 32 denotes an input terminal for maximum value data, and 34 denotes an input terminal for minimum value data. The subtraction circuit 36 subtracts the minimum value data from the maximum value data and outputs a dynamic range. Multipliers 38, 40, and 42 multiply the dynamic range by 3/4, 2/4, and 1/4, respectively, and adders 44, 46, and 48 add the minimum value to the multiplication result. As a result, the boundary values of the divided areas are obtained. The comparison circuits 50, 52, and 54 compare the pixel data from the input terminal 30 with each boundary value. When the input of the + terminal is larger than the input of the-terminal, “1” is output. Otherwise, “0” is output. Output. The encoder 56 includes comparison circuits 50 and 5
From the outputs of 2,54, a 2-bit index indicating the section to which the pixel value belongs is output. Table 2 shows the input / output characteristics of the encoder 56. FIG. 5 also shows the correspondence between the pixel values and the output of the encoder 56. FIG. 6 shows a specific example of the decoding circuit 16. Here also, for convenience of explanation, the number n of divisions of the dynamic range is set to 4 as in the above-described block encoding circuit. A terminal 60 is an input terminal for the maximum value data, 62 is an input terminal for the minimum value data, and 64 and 66 are input terminals for the indexes D ₁ and D ₀ from the block encoding circuit 14 (encoder 56). The subtraction circuit 68 subtracts the minimum value from the maximum value, and the multiplication circuits 70, 72, 74 and 76 multiply the output of the subtraction circuit 68 by 7/8, 5/8, 3/8 and 1/8, respectively. Multiplication circuit 70-7
The output of 6 is a value corresponding to the center of each section divided into four. Then, a switch switching circuit 67 according to a 2-bit index output from the encoder 56 for each pixel.
Switch 78 to switch the four multiplication circuits 70 to 76
Is selected. When the minimum value is added to the selection result by the adding circuit 80, a decoded value of each pixel data is obtained at the output terminal 82. In the above embodiment, the case where the maximum value data and the minimum value data in the block are transmitted has been described. In addition, the dynamic range (difference between the maximum value and the minimum value) within the block and the maximum value data or the minimum value data may be transmitted. A combination with the value data may be transmitted. [Effects of the Invention] As can be easily understood from the above description, according to the present invention, it is possible to transmit pixel data with a small quantization error by a circuit configuration that is not so complicated, and to reduce an image with less image quality deterioration on the receiving side. Can be played.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of an encoding apparatus according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of block formation, and FIG. 3 is modification of maximum value data and minimum value data. FIG. 4 is an explanatory diagram of the operation, FIG. 4 is a specific example of the block encoding circuit 14, FIG. 5 is an output example of the encoder 56 of the block encoding circuit 14, and FIG.
16 is a specific example. 12 ... Minimum / maximum value calculation circuit, 14, 24 ... Block encoding circuit, 16 ... Decoding circuit, 18 ... Error calculation circuit, 20 ...
… Shift amount calculation circuit

Claims (1)

(57) [Claims] Blocking means for dividing the digital image data into blocks each consisting of a predetermined number of samples; and coding by quantizing the image data between a maximum value and a minimum value of the image data blocked by the blocking means. Encoding means for decoding, and error detection for detecting a quantization error between a decoded value obtained by decoding the encoded data encoded by the encoding means and a true value of image data from the blocking means in the block unit. Means, and changing means for changing the coded data coded by the coding means in accordance with the detection result of the error detection means so that the quantization error is reduced in units of the block. An image encoding device characterized by the above-mentioned.