KR920008268Y1 - Clipping circuit in discrete cosine transform - Google Patents

Abstract

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Description

Clipping Circuit in Compression Coding Device of Image Signal

1 is a circuit diagram of a conventional video signal compression encoding apparatus.

2 is a circuit diagram of a video signal compression encoding apparatus of the present invention.

3 is a clipping circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

22: input processor 24: block constructor

28 subtractor 30 transform encoder

32: quantizer 36: inverse quantizer

38: inverse transform encoder 40: adder

42: frame memory 44: clipping circuit

46: buffer 48: memory

The present invention relates to a compression encoding apparatus for a video signal, and more particularly, to a clipping circuit for limiting an error due to video locking when playing a compressed video signal in a video signal compression encoding apparatus.

In order to transmit a normal video signal to the upper chamber through a telephone network, it is necessary to digitally convert the video signal and compress it to a small amount of digital data.

A device for digitally converting and compressing a video signal as described above is called a compression encoder, and a conventional video signal compression encoder is shown in FIG. 1.

1 is a circuit diagram of a conventional compression coding apparatus for a video signal, and is a circuit diagram of a final compression coding apparatus.

When the analog image signal is input to the input line 20 of the conventional compression encoding apparatus configured as shown in FIG. 1, the analog image signal is converted into digital by the input processor 22, and the signal converted into digital is The filter is input to the block constructer 24.

The digital video signal input to the block configurator 24 configures the input video signal in units of blocks in the scanning order. At this time, from the frame memory 42, the video signal value of one block of the same size at the same position spatially in the previous frame is read from the internal memory and inputted to the subtractor 28. The subtractor 28 subtracts the video signal of the block unit output from the block configurator 24 and the output data of the frame memory 42 to calculate a difference at a spatially identical position. This difference is called a prediction error value. .

The prediction error values are transform-coded by the transform encoder 30 and then quantized by the quantizer 32 and transmitted to the line 34.

On the other hand, in order to encode the next frame, the inverse quantizer 36 and the inverse transform encoder 38 perform the inverse process of the transform encoder 30 and the quantizer 32, and the adder 40 adds the prediction value and the prediction error value to the frame memory. Save at 42.

Therefore, only the data from which the image block data previously transmitted is subtracted from the current image block is transmitted to the output line 34, and the frame memory 42 is transmitted to the current line 34 from the previously transmitted image block data. The added data is added and newly recorded.

The receiving side needs to know the reverse process of the transmitting side.

The prediction error values output from the subtractor 28 are intraframe 2D transformed by the transform encoder 30. In this case, DCT (Discrete Cosine Transform) and DFT (Discrete Fourier Transfor) can be used.

When the input processor 22 converts the analog image into 8-bit digital data and inputs 8-bit image data in the compression encoding apparatus of FIG. 1, the input processor 22 is reproduced by the adder 40 and the frame memory 42 The video data stored in) should be 8 bits.

The reason for limiting the input video signal as a digital data of 8 bits by 8 bits allocated to sampling of the CCIR Recommendation 60-255 the level of the luminance signal as a standard of the video signal digital coding recommendations to the (luminance signal: 2 ⁸ = 255 This is because it is limited to the range of) to maintain compatibility with the system for processing video signals.

Accordingly, the data stored in the frame memory 42 of FIG. 1 is subtracted by the subtractor 28, the transform encoder 30, and the quantizer by using the input processor 22 and the block configurator 24. 30), the data is recovered through the inverse quantizer 32, the decode converter 38, and the adder 40. Finally, the data stored in the frame memory 42 is 0 to 255 levels corresponding to 8 bits. It can be seen that it must be a data value.

However, the conventional compression protection apparatus as described above has a tgansform operation and a quantization process during the processes of the transform encoder 30, the quantizer 32, the inverse quantizer 36, and the inverse transform encoder 38. If a signal is out of the range that the signal should have due to the effect of an error occurring during quautization, it is therefore required to limit the data value of the reproduced image to the boundary value of the signal range.

Accordingly, an object of the present invention is to provide a clipping circuit that prevents the brightness of the reproduced image from departing from a predetermined region due to noise when reproducing the image signal compressed by the image signal compression encoding apparatus.

The present invention for achieving the above object is connected between the adder 40 and the frame memory 42 and is enabled when the reproduction data RD output from the adder 40 has a negative value, thereby enabling the reproduction data ( A buffer 46 for buffering and inputting boundary data of RD into the frame memory 42, and when the reproduction data RD has a positive value, is enabled so that clipping data of the address designated by the reproduction data RD is acquired. It is characterized by consisting of a memory 48 to be input to the memory 42.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an apparatus for compressing and encoding a video signal according to the present invention, and includes a clipping circuit for removing a conversion process error and a quantization error between the frame memory 42 and the adder 40 in the above-described configuration of FIG. 44) is connected and other configurations and reference numerals are the same as in FIG.

3 is a buffering circuit diagram of the present invention, which is enabled by an inverted signal of the most significant bit MSB of the reproduction data RD of a predetermined bit, and is buffered to output a clipping boundary data. The most significant bit MSB of the reproduction data RD is input to store data corresponding to an input address, which is enabled and a desired clipping range, and clinking data is stored using the reproduction data of the predetermined bit as an address. And an inverter 50 for inverting the most significant bit MSB of the reproduction data RD and providing an enable signal to the buffer 46.

At this time, in the memory 48 of the configuration of FIG. 3, the clipping data desired for the address should be masked using the reproduction signal data as an address.

In the above-described operation of FIG. 2 with reference to FIG. 3, the processing by the input processor 22 will be described as an example of 8-bit analog / digital conversion.

When the analog video signal is input to the line 20 now, the input processor 22 converts the analog video signal, which is input, into 8-bit digital data, and filters the band.

At this time, the block configurator 24 configures the input image signals in block units and outputs them to the subtractor 28.

As described above, from the frame memory 42 during operation, the video signal values of one block of the same size at the same position in the previous frame are read from the internal memory and outputted to the subtractor 8.

At this time, the subtractor 28 inputs the prediction error data, which is the prediction error value obtained by subtracting the block image data of the previous frame from the block of the current input image signal, that is, the block encoder 24, to the transform encoder 30. .

Therefore, the signal input to the transform encoder 30 via the subtractor 28 is 9 bits. The MSB (most significant bit) of the data output from the subtractor 28 is a sign bit indicating whether the remaining 8 bits of data are positive or negative. The predictive error (subtracted data), which is 9 bits by the subtractor 28, is output to the transmission path 34 through a transform encoding process and a quantization process by operations of the transform encoder 30 and the quantizer 32.

Meanwhile, the data transmitted to the transmission path 34 is input to the inverse quantizer 36, inversely quantized, and then to the inverse transform encoder 38, inversely encoded, and output to the adder 40. Therefore, the adder 40 receives a signal including a quantization error caused by the operations of the inverse quantizer 36 and the decode converter 38 and an error caused by the conversion process.

When the prediction value output from the frame memory 42 by the adder 40, that is, block data having the same size spatially and the data currently output to the transmission path 34, is added to the 10-bit reproduction data ( RD). At this time, the 9-bit data output from the decode converter 38 and the 8-bit data output from the frame memory 42 are added and converted into 10-bit reproduction data RD, that is, data of -512 to 512 levels. This is because of the generation of carry output (occurrence) or barrow by addition of bit data. [Most Significant Bit (MSB) of 10-bit Output Data of Adder 40 Represents Positive and Negative Signs of Remaining 9-bit Value]

Therefore, the 10-bit reproduction data RD containing the error must be stored in the frame memory 42 by making the original form 8 bits, that is, a value of 0 to 255 levels. Such an operation is illustrated in FIG. By the operation of the clipping circuit 44.

If the original input video signal has only a positive value, the reproduced signal may have a negative value due to an intermediate insertion of an error by the operations of the inverse quantizer 36, the decode converter 38, and the adder 40. Will be.

As described above, the 10-bit reconstructed data (RD) output from the adder 40 is negative due to the operations of the inverse magnetizer 36, the decode converter 38, and the adder 40. If the remaining 9 bits except the bit MSB have a value of -512 to -1, the most significant bit MSB of the reproduction data has a sign bit of "1".

The most significant bit MSB of the reproduction data RD output from the adder 40 is the enable terminal / OE of the memory 48 shown in FIG. 3 (where "/" represents logic of an inverted state). Means "BAR which is" _ "] and is inverted by the inverter and input to the enable terminal (/ OE) of the buffer 46.

Therefore, when the logic of the sign bit that is the most significant bit MSB of the reproduction data RD is "1", the memory 48 is disabled, and only the buffer 46 is caused by the output of the inverter 50. Enabled to the inverted "low" output. When the buffer 46 is enabled as described above, an 8-bit clipping boundary Data (substantially "0") set in advance and input to the data input terminal Din of the buffer 46 is set. The buffer memory 42 is buffered to the data input terminal of the frame memory 42 of FIG. 2 so that the frame memory 42 stores the clipping boundary value input through the buffer 46.

If the reproduction data RD outputted from the adder 40 is a positive value (the values of 9 bits other than the most significant bit MSB are 0 to 512), the most significant bit MSB of the reproduction data RD is The output of inverter 50 becomes logic '1' as the sine bit is output to logic " 0 ", thereby disabling buffer 46 in FIG. 3 and enabling memory 48 only.

As described above, when the sine bit, which is the most significant bit MSB of the reproduction data RD, becomes logic " 0 ", the memory 48 pre-addresses the address value with the remaining 9 bits of the reproduction data RD as an address. Output the set clipping data.

At this time, the memory 48 stores an input address, that is, clipping data of a clipping range for the reproduction data RD in correspondence with the address.

For example, in each of the 0 to 255 address areas ("0 0000 0000 to 0 111111 in binary"), data of 0 to 255 ("0000,0000 to 0,1111.1111 in binary") is stored. Values of 256 to 512 (0,1111 and 1111 in binary) are stored so that the value of the output data is clipped so as not to exceed the level of 255.

Therefore, the memory 48 reads the clipping data corresponding to the 9-bit reproduction data RD input to the address terminals A0 to A8 in the internal region and outputs the clipping data to the frame memory 42.

Therefore, the clipping circuit 44 is reproduced by the inverse quantizer 36, the decode converter 38, and the adder 40 so that the reproduction data RD having a value of -512 to 512 is 0 to 256. The data is clipped to standard level data having a level, and transmitted to the frame memory 42.

When the range of the video signal inputted by the above operation is changed or when the clipping range of the video signal is changed, it is only necessary to change the data value in the memory 48. You can change the clipping range.

As described above, the present invention compresses the clipping range by using a memory element when the brightness of the reproduced image is out of the entire range that the signal should have due to the error generated during the compression process when the image signal is compressed and reproduced. There is an advantage that can be arbitrarily determined.

Claims (1)

(Correction) An input processor 22 for converting and outputting an analog video signal, a block configurator 24 for outputting the output data of the input processor 22 in block units in a scanning order and outputting the data in all frames. A frame memory 42 for outputting block data of the same size at a spatially identical position, and a subtractor for subtracting and outputting block data of all frames output from the frame memory 42 from data of the block configurator 24 ( 28, a transform encoder 30 and a quantizer 32 for transform encoding and quantizing the output of the subtractor 28, and an inverse quantizer for inverse quantizing and inverse transform encoding the output of the quantizer 32 ( 36) and an inverse transform encoder 38, and an adder 40 which adds the output of the inverse transform encoder 38 and the data of the frame memory 42 to output reproduction data RD. In the clipping circuit in the display device, when the playback data RD output from the adder 40 has a negative value when connected between the adder 40 and the frame memory 42, the preset playback is enabled. A buffer 46 for buffering and inputting boundary data of the data RD into the frame memory 42 and a clipping of the address where the reproduction data RD is designated when the reproduction data RD has a positive value. And a memory (48) for inputting data into the memory (42).