JPH0722200B2 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistorInfo
- Publication number
- JPH0722200B2 JPH0722200B2 JP3633686A JP3633686A JPH0722200B2 JP H0722200 B2 JPH0722200 B2 JP H0722200B2 JP 3633686 A JP3633686 A JP 3633686A JP 3633686 A JP3633686 A JP 3633686A JP H0722200 B2 JPH0722200 B2 JP H0722200B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate
- electrode
- source
- resist mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010408 film Substances 0.000 claims description 92
- 239000000758 substrate Substances 0.000 claims description 31
- 239000012212 insulator Substances 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims description 2
- 239000012528 membrane Substances 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 11
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 10
- 229910052719 titanium Inorganic materials 0.000 description 10
- 239000010936 titanium Substances 0.000 description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 239000011521 glass Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 2
- 229910052753 mercury Inorganic materials 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】 〔概要〕 薄膜トランジスタの製造方法の改良である。DETAILED DESCRIPTION [Outline] It is an improvement in a method of manufacturing a thin film transistor.
透光性絶縁物基板上に不透光性の電極（逆スタガード型
においてはゲート電極、スタガード型においてはソース
電極・ドレイン電極）を形成した後、透光性絶縁物基板
の裏面から紫外線照射をなしながら原料ガスを供給し
て、光の照射されている領域のみに堆積をさせる光CVD
法を使用して、透光性絶縁物基板上の不透光性電極が存
在しない領域に、付加的に絶縁膜を形成して、不透光性
電極にもとづく段差を解消し、その上に、従来技術と同
様にして、逆スタガード型またはスタガード型の薄膜ト
ランジスタを形成することとして、不透光性の電極の段
差に起因する絶縁耐圧不良の可能性を解消したものであ
る。After forming a non-translucent electrode (gate electrode in the reverse staggered type, source electrode / drain electrode in the staggered type) on the transparent insulating substrate, UV irradiation is performed from the back surface of the transparent insulating substrate. While supplying the source gas, the photo-CVD that deposits only in the area where the light is irradiated
By using the method, an insulating film is additionally formed in the region where the non-translucent electrode on the translucent insulator substrate does not exist, and the step due to the non-transmissive electrode is eliminated. By forming an inverted staggered type or staggered type thin film transistor in the same manner as in the prior art, the possibility of a breakdown voltage failure due to a step difference of an opaque electrode is eliminated.
本発明は、薄膜トランジスタの製造方法の改良に関す
る。特に、絶縁膜の段差にもとづき、各電極のエッジ部
で絶縁耐圧が低下する可能性を解消し、薄膜トランジス
タの絶縁耐圧を向上する改良に関する。The present invention relates to an improvement in a method of manufacturing a thin film transistor. In particular, the present invention relates to an improvement that eliminates the possibility that the withstand voltage is lowered at the edge of each electrode due to the step of the insulating film, and improves the withstand voltage of the thin film transistor.
逆スタガード型薄膜トランジスタの従来技術に係る製造
方法を説明する。A conventional method of manufacturing an inverted staggered thin film transistor will be described.
第７図参照 ガラス板等透光性絶縁物基板１上にクロム膜等を形成
し、これをパターニングして不透光性ゲート電極２を形
成する。See FIG. 7. A chrome film or the like is formed on a transparent insulating substrate 1 such as a glass plate, and this is patterned to form a non-transparent gate electrode 2.
つゞいて、窒化シリコン膜等よりなるゲート絶縁膜３と
水素化アモルファスシリコン等よりなる動作層４と二酸
化シリコン等よりなるチャンネル保護用絶縁膜５とをつ
ゞけて形成する。Then, the gate insulating film 3 made of a silicon nitride film, the operating layer 4 made of hydrogenated amorphous silicon, and the channel protection insulating film 5 made of silicon dioxide are formed together.
その上にポジ型レジスト膜６を形成する。A positive resist film 6 is formed thereon.
第８図参照 透光性絶縁物基板１の側から、不透光性ゲート電極２を
マスクとして露光した後現像して、不透光性ゲート電極
２と同一形状の第１のレジストマスク61を形成する。See FIG. 8. From the transparent insulating substrate 1 side, the first resist mask 61 having the same shape as the non-transparent gate electrode 2 is exposed by using the non-transparent gate electrode 2 as a mask and then developed. Form.
この第１のレジストマスク61を使用し、フッ酸等をもっ
てチャンネル保護用絶縁膜５を除去する。Using this first resist mask 61, the channel protection insulating film 5 is removed with hydrofluoric acid or the like.
第９図参照 ｎ型水素化アモルファスシリコン膜71とソース電極・ド
レイン電極用のチタン膜72・アルミニュウム膜73との二
重層をつゞけて形成した後、第１のレジストマスク61を
除去して、ソース電極・ドレイン電極用のアルミニュウ
ム膜73とチタン膜72とｎ型水素化アモルファスシリコン
膜71とをゲート領域上からリフトオフする。See FIG. 9. After forming a double layer of an n-type hydrogenated amorphous silicon film 71, a titanium film 72 for source / drain electrodes, and an aluminum film 73, the first resist mask 61 is removed. The aluminum film 73 for source / drain electrodes, the titanium film 72, and the n-type hydrogenated amorphous silicon film 71 are lifted off from the gate region.
第10図参照 ゲート・ソース・ドレイン領域に第２のレジストマスク
（図示せず）を形成し、この第２のレジストマスク（図
示せず）を使用して、ソース電極・ドレイン電極用のア
ルミニュウム膜73とチタン膜72とｎ型水素化アモルファ
スシリコン膜71と動作層４と、所望によってはゲート絶
縁膜３とを、薄膜トランジスタ領域以外から除去して素
子分離をなす。See FIG. 10. A second resist mask (not shown) is formed in the gate / source / drain regions, and an aluminum film for source / drain electrodes is formed using this second resist mask (not shown). 73, the titanium film 72, the n-type hydrogenated amorphous silicon film 71, the operating layer 4 and, if desired, the gate insulating film 3 are removed from regions other than the thin film transistor region to provide element isolation.
次に、スタガード型薄膜トランジスタの従来技術に係る
製造方法を説明する。Next, a conventional method for manufacturing a staggered thin film transistor will be described.
第11図参照 ガラス板等透光性絶縁物基板１上にチタン膜等を形成
し、これをパターニングしてソース電極９とドレイン電
極10とを形成する。See FIG. 11. A titanium film or the like is formed on the transparent insulating substrate 1 such as a glass plate, and the titanium film or the like is patterned to form the source electrode 9 and the drain electrode 10.
つゞいて、水素化アモルファスシリコン等よりなる動作
層４と窒化シリコン膜等よりなるゲート絶縁膜３とをつ
ゞけて形成する。Then, the operating layer 4 made of hydrogenated amorphous silicon or the like and the gate insulating film 3 made of a silicon nitride film or the like are formed together.
その上に、ゲート電極出用導電膜８を形成し、さらに、
その上に、ネガ型レジスト膜11を形成する。A conductive film 8 for gate electrode output is formed thereon, and further,
A negative resist film 11 is formed thereon.
第12図参照 ネガ型レジスト膜11を露光・現像して、チャンネル上の
みに第３のレジストマスク111を形成する。See FIG. 12. The negative resist film 11 is exposed and developed to form a third resist mask 111 only on the channel.
この第３のレジストマスク111を使用してゲート電極用
導電膜８をパターニングしてゲート電極81を形成する。The third resist mask 111 is used to pattern the gate electrode conductive film 8 to form a gate electrode 81.
第13図参照 第３のレジストマスク111を除去した後、ソース・ゲー
ト・ドレイン領域上に第４のレジストマスク（図示せ
ず）を形成し、この第４のレジストマスク（図示せず）
を使用して、動作層４をソース・ゲート・ドレイン領域
以外から除去して素子分離をなす。See FIG. 13. After removing the third resist mask 111, a fourth resist mask (not shown) is formed on the source / gate / drain regions, and the fourth resist mask (not shown) is formed.
Is used to remove the operating layer 4 from regions other than the source / gate / drain regions to form element isolation.
その後、第４のレジストマスク（図示せず）を除去す
る。After that, the fourth resist mask (not shown) is removed.
〔発明が解決しようとする問題点〕 上記せる従来技術に係る薄膜トランジスタは、逆スタガ
ード型であってもスタガード型であっても、動作層とゲ
ート絶縁膜とが段差上に形成されることとなるので、こ
の段差上に形成されるゲート絶縁膜の絶縁耐圧が平坦部
に形成される場合に比して劣っており、ゲート電極エッ
ジ部やソース・ドレイン電極エッジ部での絶縁性の信頼
性が劣るという欠点がある。[Problems to be Solved by the Invention] In the thin film transistor according to the above-mentioned conventional technology, whether the inverted staggered type or the staggered type, the operation layer and the gate insulating film are formed on the step. Therefore, the withstand voltage of the gate insulating film formed on the step is inferior to that in the case where it is formed in the flat portion, and the reliability of the insulating property at the edge portion of the gate electrode and the edge portion of the source / drain electrode is low. It has the disadvantage of being inferior.
本発明の目的はこの欠点を解消することにあり、ゲート
絶縁膜形成領域に段差がなく、ゲート絶縁膜は平坦な面
上に形成されており、その結果、ゲート電極エッジ部や
ソース・ドレイン電極エッジ部での絶縁性が向上してい
る薄膜トランジスタの製造方法を提供することにある。An object of the present invention is to eliminate this drawback. The gate insulating film formation region has no step and the gate insulating film is formed on a flat surface. As a result, the gate electrode edge portion and the source / drain electrode are formed. It is an object of the present invention to provide a method for manufacturing a thin film transistor having improved insulation at the edge portion.
上記の目的を達成するために本発明が採った手段は、透
光性絶縁物基板１上に不透光性のゲート電極２または不
透光性のソース電極９のドレイン電極10とを形成した
後、透光性絶縁物基板１の側から紫外線を照射しながら
原料ガスを供給して光の照射されている領域のみに堆積
をさせる光CVD法を使用して、付加絶縁膜31または32を
形成して、上記の電極２・９・10にもとづく段差を埋め
て、ゲート絶縁膜を平坦化することにある。In order to achieve the above object, the means adopted by the present invention is to form an opaque gate electrode 2 or a opaque source electrode 9 drain electrode 10 on a translucent insulator substrate 1. After that, the additional insulating film 31 or 32 is formed by the photo-CVD method in which the source gas is supplied while irradiating the ultraviolet ray from the side of the translucent insulator substrate 1 and the deposition is performed only in the region where the light is radiated. It is to form the gate insulating film by filling the step due to the electrodes 2, 9 and 10 and flattening the gate insulating film.
上記の欠点はゲート絶縁膜の段差に起因するものである
から、ゲート絶縁膜の段差を埋めて平坦化すれば解消す
ることは明らかであり、この段差を埋めるために、一部
領域にのみ形成されている不透光性のゲート電極または
不透光性のソース電極とドレイン電極を介して光照射を
なす光CVD法を利用したものである。Since the above-mentioned drawbacks are caused by the step difference in the gate insulating film, it is clear that the problem can be solved by filling the step difference in the gate insulating film and flattening it. The photo CVD method is used in which light irradiation is performed through a non-translucent gate electrode or a non-translucent source electrode and a drain electrode.
以下、図面を参照しつゝ、本出願に係る各発明の実施例
に係る薄膜トランジスタの製造方法を説明する。Hereinafter, a method of manufacturing a thin film transistor according to each embodiment of the present invention will be described with reference to the drawings.
第１例 第２図参照 ガラス板等透光性絶縁物基板１上にクロム膜等を形成
し、これをパターニングして不透光性ゲート電極２を形
成する。First Example See FIG. 2 A chrome film or the like is formed on a transparent insulating substrate 1 such as a glass plate, and the chrome film is patterned to form a non-transparent gate electrode 2.
赤外線ヒータを使用して基板１を約700℃に加熱しなが
ら、基板１の裏面から低圧水銀灯を使用して基板１の裏
面から紫外線照射をなし、同時に、ジシラン（Si2H6）
とアンモニヤ（NH3）との混合ガスを0.1〜1Torrのガス
圧で供給してなす光CVD法を使用して、窒化シリコンよ
りなる付加絶縁膜31を、光の照射される領域（ゲート電
極２の存在しない領域）のみにゲート電極２と同一の高
さに形成して、ゲート電極２の上面を平坦化する。While heating the substrate 1 to about 700 ° C. using an infrared heater, the back surface of the substrate 1 is irradiated with ultraviolet rays from the back surface of the substrate 1 using a low pressure mercury lamp, and at the same time, disilane (Si 2 H 6 ) is used.
The additional insulating film 31 made of silicon nitride is formed on the region to be irradiated with light (gate electrode 2) by using a photo-CVD method in which a mixed gas of ammonia and ammonia (NH 3 ) is supplied at a gas pressure of 0.1 to 1 Torr. Is formed in the same height as that of the gate electrode 2 only in a region where the gate electrode 2 does not exist, and the upper surface of the gate electrode 2 is flattened.
つゞいて、プラズマCVD法を使用して、窒化シリコン膜
等よりなるゲート絶縁膜３と水素化アモルファスシリコ
ン等よりなる動作層４と二酸化シリコン等よりなるチャ
ンネル保護用絶縁膜５とをつゞけて形成する。これらの
ゲート絶縁膜３と動作層４は、平面上に形成されるか
ら、段差を有することなく平面状である。Then, using the plasma CVD method, the gate insulating film 3 made of a silicon nitride film and the like, the operating layer 4 made of hydrogenated amorphous silicon and the like and the channel protection insulating film 5 made of silicon dioxide and the like are attached. To form. Since the gate insulating film 3 and the operating layer 4 are formed on a plane, they have a plane shape without a step.
その上にポジ型レジスト膜６を形成する。A positive resist film 6 is formed thereon.
第３図参照 透光性絶縁物基板１の側から、不透光性のゲート電極２
をマスクとして露光した後現像して、ゲート電極２と同
一形状の第１のレジストマスク61を形成する。See FIG. 3. From the side of the transparent insulating substrate 1, the non-transparent gate electrode 2
Is used as a mask for exposure and then development is performed to form a first resist mask 61 having the same shape as the gate electrode 2.
第４図参照 ｎ型水素化アモルファスシリコン膜71とソース電極・ド
レイン電極用のチタン膜72とアルミニュウム膜73との二
重層をつゞけて形成した後、第１のレジストマスク61を
除去して、ソース電極・ドレイン電極用のアルミニュウ
ム膜73とチタン膜72とｎ型水素化アモルファスシリコン
膜71とをゲート領域上からリフトオフする。See FIG. 4. After forming a double layer of an n-type hydrogenated amorphous silicon film 71, a titanium film 72 for source / drain electrodes, and an aluminum film 73, the first resist mask 61 is removed. The aluminum film 73 for source / drain electrodes, the titanium film 72, and the n-type hydrogenated amorphous silicon film 71 are lifted off from the gate region.
第1a図参照 ゲート・ソース・ドレイン領域に第２のレジストマスク
（図示せず）を形成し、この第２レジストマスク（図示
せず）を使用して、ソース電極・ドレイン電極用のアル
ミニュウム膜73とチタン膜72とｎ型水素化アモルファス
シリコン膜71と動作層４と、所望によってはゲート絶縁
膜３とを、薄膜トランジスタ領域以外から除去して素子
分離をなす。See FIG. 1a. A second resist mask (not shown) is formed in the gate / source / drain regions, and using this second resist mask (not shown), an aluminum film 73 for source / drain electrodes is formed. The titanium film 72, the n-type hydrogenated amorphous silicon film 71, the operating layer 4 and, if desired, the gate insulating film 3 are removed from regions other than the thin film transistor region to provide element isolation.
以上の工程をもって製造された薄膜トランジスタのゲー
ト絶縁膜３には段差部が存在しないので、ゲート電極エ
ッジやソース電極エッジ・ドレイン電極エッジの絶縁耐
圧が向上している。Since there is no stepped portion in the gate insulating film 3 of the thin film transistor manufactured through the above steps, the withstand voltage of the gate electrode edge and the source electrode edge / drain electrode edge is improved.
第２例 第５図参照 ガラス板等透光性絶縁物基板１上にチタン膜等を形成
し、これをパターニングして不透光性のソース電極９・
ドレイン電極10を形成する。Second Example See FIG. 5 A titanium film or the like is formed on a transparent insulating substrate 1 such as a glass plate, and is patterned to form a non-translucent source electrode 9.
The drain electrode 10 is formed.
赤外線ヒータを使用して基板１を約700℃に加熱しなが
ら、基板１の裏面から低圧水銀灯を使用して基板１の裏
面から紫外線照射をなし、同時に、ジシラン（Si2H6）
とアンモニヤ（NH3）との混合ガスを0.1〜1Torrのガス
圧で供給してなす光CVD法を使用して、窒化シリコンよ
りなる付加絶縁膜32を、光の照射される領域（ソース電
極９・ドレイン電極10の存在しない領域）に、ソース電
極９・ドレイン電極10と同一の高さに形成して、ソース
電極９・ドレイン電極10の上面を平坦化する。While heating the substrate 1 to about 700 ° C. using an infrared heater, the back surface of the substrate 1 is irradiated with ultraviolet rays from the back surface of the substrate 1 using a low pressure mercury lamp, and at the same time, disilane (Si 2 H 6 ) is used.
The additional insulating film 32 made of silicon nitride is formed on the region (source electrode 9) to be irradiated with light by using a photo-CVD method in which a mixed gas of ammonia and ammonia (NH 3 ) is supplied at a gas pressure of 0.1 to 1 Torr. In a region where the drain electrode 10 does not exist), the source electrode 9 and the drain electrode 10 are formed at the same height, and the upper surfaces of the source electrode 9 and the drain electrode 10 are flattened.
つゞいて、プラズマCVD法を使用して、水素化アモルフ
ァスシリコン等よりなる動作層４と窒化シリコン膜等よ
りなるゲート絶縁膜３とをつゞけて形成する。Then, the operating layer 4 made of hydrogenated amorphous silicon or the like and the gate insulating film 3 made of a silicon nitride film or the like are formed together by using the plasma CVD method.
その上に、ゲート電極用導電膜８を形成し、さらに、そ
の上に、ポジ型レジスト膜11を形成する。A conductive film 8 for gate electrode is formed thereon, and a positive type resist film 11 is further formed thereon.
第６図参照 ポジ型レジスト膜11を露光・現像して、チャンネル上の
みに第３のレジストマスク111を形成する。See FIG. 6. The positive resist film 11 is exposed and developed to form a third resist mask 111 only on the channel.
この第３のレジストマスク111を使用してゲート電極用
導電膜８をパターニングしてゲート電極81を形成する。The third resist mask 111 is used to pattern the gate electrode conductive film 8 to form a gate electrode 81.
第1b図参照 第３のレジストマスク111を除去した後、ソース・ゲー
ト・ドレイン領域上に第４のレジストマスク（図示せ
ず）を形成し、この第４のレジストマスク（図示せず）
を使用して、動作層４をソース・ゲート・ドレイン領域
以外から除去して素子分離をなす。See FIG. 1b. After removing the third resist mask 111, a fourth resist mask (not shown) is formed on the source / gate / drain regions, and the fourth resist mask (not shown) is formed.
Is used to remove the operating layer 4 from regions other than the source / gate / drain regions to form element isolation.
その後、第４のレジストマスク（図示せず）を除去す
る。After that, the fourth resist mask (not shown) is removed.
以上の工程をもって製造された薄膜トランジスタのゲー
ト絶縁膜３には段差部が存在しないので、ゲート電極エ
ッジやソース電極エッジ・ドレイン電極エッジの絶縁耐
圧が向上している。Since there is no stepped portion in the gate insulating film 3 of the thin film transistor manufactured through the above steps, the withstand voltage of the gate electrode edge and the source electrode edge / drain electrode edge is improved.
以上説明せるとおり、本発明に係る薄膜トランジスタの
製造方法においては、透光性絶縁物基板上に不透光性ゲ
ート電極または不透光性のソース電極とドレイン電極と
を形成した後、透光性絶縁物基板の側から紫外線を照射
しながら原料ガスを供給して、光の照射されている領域
のみに堆積をさせる光CVD法を使用して付加絶縁膜を形
成して、上記の電極にもとづく段差を埋めてゲート絶縁
膜を平坦化することとされているで、本発明に係る薄膜
トランジスタの製造方法をもって製造された薄膜トラン
ジスタのゲート絶縁膜には段差部が存在せず、ゲート電
極エッジやソース電極エッジ・ドレイン電極エッジの絶
縁耐圧が向上している。As described above, in the method for manufacturing a thin film transistor according to the present invention, in the method for manufacturing a thin film transistor, after forming an opaque gate electrode or an opaque source electrode and a drain electrode on a translucent insulator substrate, the translucent An additional insulating film is formed by using the optical CVD method in which the source gas is supplied while irradiating ultraviolet rays from the side of the insulator substrate, and the deposition is performed only in the region where the light is irradiated, and based on the above electrodes. Since it is supposed that the step is filled and the gate insulating film is flattened, the gate insulating film of the thin film transistor manufactured by the method of manufacturing a thin film transistor according to the present invention does not have a step, and the gate electrode edge and the source electrode are not formed. The withstand voltage of the edge / drain electrode edges is improved.
第1a図は、本出願に係る第１の発明の一実施例に係る逆
スタガード型薄膜トランジスタの製造方法を実施して製
造した逆スタガード型薄膜トランジスタの構造図であ
る。 第1b図は、本出願に係る第２の発明の一実施例に係るス
タガード型薄膜トランジスタの製造方法を実施して製造
したスタガード型薄膜トランジスタの構造図である。 第２〜４図は、本出願に係る第１の発明の一実施例に係
る逆スタガード型薄膜トランジスタの製造方法の主要工
程完了後の基板断面図である。 第５〜６図は、本出願に係る第２の発明の一実施例に係
るスタガード型薄膜トランジスタの製造方法の主要工程
完了後の基板断面図である。 第７〜10図は、従来技術に係る逆スタガード型薄膜トラ
ンジスタの主要工程完了後の基板断面図である。 第11〜13図は、従来技術に係るスタガード型薄膜トラン
ジスタの主要工程完了後の基板断面図である。 １……透光性絶縁物基板（ガラス板）、２……不透光性
ゲート電極、３……ゲート絶縁膜、31、32……付加絶縁
膜、４……動作層、５……チャンネル保護膜、６……ポ
ジレジスト膜、61……第１のレジストマスク、７……導
電膜、71……ｎ型水素化アモルファスシリコン、72……
チタン膜、73……アルミニュウム膜、９……ソース電
極、10……ドレイン電極、８……導電膜、81……ゲート
電極、11……ネガレジスト膜、111……第３のレジスト
マスク。FIG. 1a is a structural diagram of an inverted staggered thin film transistor manufactured by performing a method for manufacturing an inverted staggered thin film transistor according to an embodiment of the first invention of the present application. FIG. 1b is a structural diagram of a staggered type thin film transistor manufactured by performing a method of manufacturing a staggered type thin film transistor according to an embodiment of the second invention of the present application. 2 to 4 are cross-sectional views of the substrate after completion of the main steps of the method for manufacturing an inverted staggered thin film transistor according to an embodiment of the first invention of the present application. 5 to 6 are cross-sectional views of the substrate after completion of the main steps of the method for manufacturing a staggered thin film transistor according to the embodiment of the second invention of the present application. 7 to 10 are cross-sectional views of the substrate after completion of the main steps of the conventional inverted staggered thin film transistor. 11 to 13 are cross-sectional views of a substrate after completion of main steps of a staggered thin film transistor according to a conventional technique. 1 ... Translucent insulator substrate (glass plate), 2 ... Non-transparent gate electrode, 3 ... Gate insulating film, 31, 32 ... Additional insulating film, 4 ... Operating layer, 5 ... Channel Protective film, 6 ... Positive resist film, 61 ... First resist mask, 7 ... Conductive film, 71 ... N-type hydrogenated amorphous silicon, 72 ...
Titanium film, 73 ... Aluminum film, 9 ... Source electrode, 10 ... Drain electrode, 8 ... Conductive film, 81 ... Gate electrode, 11 ... Negative resist film, 111 ... Third resist mask.
Claims (2)
ート電極（２）を形成し、 ゲート絶縁膜（３）を形成し、 動作層（４）を形成し、 チャンネル保護用絶縁膜（５）を形成し、 ポジ型レジスト膜（６）を形成し、 該ポジ型レジスト膜（６）を前記透光性絶縁物基板
（１）の側から露光して前記不透光性のゲート電極
（２）と同一形状の第１のレジストマスク（61）を形成
し、 導電膜（７）を形成した後、前記第１のレジストマスク
（61）を使用して、前記導電膜（７）をチャンネル領域
から除去し、 ソース・ゲート・ドレイン領域上に第２のレジストマス
クを形成し、該第２のレジストマスクを使用して、前記
導電膜（７）と前記動作層（４）とを、ソース・ゲート
・ドレイン領域以外から除去して素子分離をなす薄膜ト
ランジスタの製造方法において、 前記不透光性のゲート電極（２）を形成した後、前記ゲ
ート絶縁膜（３）の形成に先立ち、 前記透光性絶縁物基板（１）の側から紫外線を照射して
なす光CVD法を使用して、前記不透光性のゲート電極
（２）の存在しない領域に、前記透光性絶縁物基板
（１）上に、付加絶縁膜（31）を、該付加絶縁膜（31）
の上面を前記不透光性のゲート電極（２）の上面とおゝ
むね一致させて形成することを特徴とする薄膜トランジ
スタの製造方法。1. A translucent insulating substrate (1) is formed with a non-translucent gate electrode (2), a gate insulating film (3) is formed, an operating layer (4) is formed, and a channel is formed. A protective insulating film (5) is formed, a positive type resist film (6) is formed, and the positive type resist film (6) is exposed from the transparent insulating substrate (1) side to form the opaque film. After forming a first resist mask (61) having the same shape as that of the gate electrode (2) and forming a conductive film (7), the conductive film is formed by using the first resist mask (61). The film (7) is removed from the channel region, a second resist mask is formed on the source / gate / drain regions, and the conductive film (7) and the operating layer () are formed using the second resist mask. 4) is removed from a region other than the source / gate / drain regions to form a thin film transistor. In the manufacturing method, after forming the opaque gate electrode (2), prior to forming the gate insulating film (3), ultraviolet rays are irradiated from the side of the transparent insulating substrate (1). The additional insulating film (31) is formed on the transparent insulating substrate (1) in the region where the non-transparent gate electrode (2) does not exist by using the optical CVD method. Membrane (31)
A method of manufacturing a thin film transistor, wherein the upper surface of the thin film transistor and the upper surface of the non-transparent gate electrode (2) are substantially aligned with each other.
ース電極（９）とドレイン電極（10）とを形成し、 動作層（４）を形成し、 ゲート絶縁膜（３）を形成し、 導電膜（８）を形成し、 チャンネル領域上のみに第３のレジストマスク（111）
を形成し、 該第３のレジストマスク（111）を使用して、前記導電
膜（８）をチャンネル領域以外から除去してゲート電極
（81）を形成し、 ソース・ゲート・ドレイン領域上に第４のレジストマス
クを形成し、該第４のレジストマスクを使用して、前記
動作層（４）を、ソース・ゲート・ドレイン領域以外か
ら除去して素子分離をなす薄膜トランジスタの製造方法
において、 前記不透光性のソース電極（９）とドレイン電極（10）
とを形成した後、前記動作層（４）の形成に先立ち、 前記透光性絶縁物基板（１）の側から紫外線を照射して
なす光CVD法を使用して、前記不透光性のソース電極
（９）とドレイン電極（10）とが存在しない領域に、透
光性絶縁物基板（１）上に、付加絶縁膜（32）を、該付
加絶縁膜（32）の上面を前記ソース電極（９）・前記ド
レイン電極（10）の上面とおゝむね一致させて形成する
ことを特徴とする薄膜トランジスタの製造方法。2. An opaque source electrode (9) and a drain electrode (10) are formed on a transparent insulating substrate (1), an operating layer (4) is formed, and a gate insulating film ( 3) is formed, a conductive film (8) is formed, and a third resist mask (111) is formed only on the channel region.
And using the third resist mask (111), the conductive film (8) is removed from a region other than the channel region to form a gate electrode (81), and a gate electrode (81) is formed on the source / gate / drain regions. No. 4 resist mask is formed, and the operating layer (4) is removed from a region other than the source / gate / drain regions by using the fourth resist mask to form a thin film transistor. Translucent source electrode (9) and drain electrode (10)
After forming the operating layer (4), the photo-transmissive insulator substrate (1) is irradiated with ultraviolet rays to form the non-translucent film. In a region where the source electrode (9) and the drain electrode (10) do not exist, an additional insulating film (32) is provided on the translucent insulator substrate (1), and an upper surface of the additional insulating film (32) is provided as the source A method of manufacturing a thin film transistor, characterized in that the electrode (9) and the drain electrode (10) are formed so as to substantially coincide with the upper surfaces thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3633686A JPH0722200B2 (en) | 1986-02-20 | 1986-02-20 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3633686A JPH0722200B2 (en) | 1986-02-20 | 1986-02-20 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62194675A JPS62194675A (en) | 1987-08-27 |
| JPH0722200B2 true JPH0722200B2 (en) | 1995-03-08 |
Family
ID=12466984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3633686A Expired - Lifetime JPH0722200B2 (en) | 1986-02-20 | 1986-02-20 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0722200B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4902175B2 (en) * | 2005-09-21 | 2012-03-21 | 日新製鋼株式会社 | Escalator step structure |
| WO2014208476A1 (en) | 2013-06-27 | 2014-12-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
-
1986
- 1986-02-20 JP JP3633686A patent/JPH0722200B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62194675A (en) | 1987-08-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3409542B2 (en) | Method for manufacturing semiconductor device | |
| JPH0132672B2 (en) | ||
| JPS62124775A (en) | Manufacture of thin film transistor by inclined etching and the thin film transistor | |
| CN104678643B (en) | The production method of display base plate and display panel | |
| JP2003517641A (en) | Method for manufacturing active matrix device | |
| TWI226965B (en) | Semi-transmission type liquid crystal display and fabrication method thereof | |
| JPH0722200B2 (en) | Method of manufacturing thin film transistor | |
| JP2003302647A (en) | Liquid crystal display element and method for manufacturing the same | |
| JPS6359266B2 (en) | ||
| JPS62104171A (en) | Manufacture of thin film transistor | |
| JP3521737B2 (en) | Method for manufacturing thin-film semiconductor device, method for manufacturing active matrix substrate, and coating apparatus for tetramethoxysilane | |
| JP3218861B2 (en) | Manufacturing method of liquid crystal display device | |
| JP3071964B2 (en) | Manufacturing method of liquid crystal display device | |
| CN106910712B (en) | The production method of array substrate | |
| US5122849A (en) | Silicon thin film transistor | |
| JP2885458B2 (en) | Thin film transistor | |
| JPH07142737A (en) | Manufacture of thin-film transistor | |
| CN100587944C (en) | Pixel structure manufacturing method | |
| JPS59165459A (en) | Manufacture of thin film transistor | |
| JPS6230376A (en) | Manufacture of thin film transistor | |
| JPH05283693A (en) | Manufacture of thin film transistor | |
| JPH07221316A (en) | Manufacture of thin film transistor | |
| JPH05175233A (en) | Manufacture of liquid crystal device | |
| JPS62120074A (en) | Manufacture of thin film transistor | |
| JPH02117142A (en) | Manufacture of thin film transistor matrix |