CN100587944C - Pixel structure manufacturing method - Google Patents

Pixel structure manufacturing method Download PDF

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CN100587944C
CN100587944C CN 200710305315 CN200710305315A CN100587944C CN 100587944 C CN100587944 C CN 100587944C CN 200710305315 CN200710305315 CN 200710305315 CN 200710305315 A CN200710305315 A CN 200710305315A CN 100587944 C CN100587944 C CN 100587944C
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layer
electrode
pixel structure
forming
manufacturing method
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CN 200710305315
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Chinese (zh)
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CN101197333A (en
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廖达文
廖金阅
杨智钧
林汉涂
石志鸿
蔡佳琪
黄明远
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友达光电股份有限公司
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Abstract

A manufacturing method of a pixel structure includes the following steps that: firstly, a substrate is provided; secondly, a first conductive layer is formed on the substrate, and a first shade whichexposes part of the first conductive layer is arranged above the first conductive layer; thirdly, laser passes through the first shade to irradiate the first conductive layer, thereby removing part ofthe first conductive layer to form a grid electrode; fourthly, a grid electrode insulating layer is formed on the substrate to cover the grid electrode; fifthly, a channel layer is formed on the gridelectrode insulating layer positioned above the grid electrode; sixthly, a source electrode and a drain electrode are formed on the channel layer positioned at both sides of the grid electrode; seventhly, a patterning protective layer is formed to cover the channel layer and expose the drain electrode; finally, an electrode material layer is formed to cover the patterning protective layer and theexposed drain electrode, and patterning of the electrode material is completed through the patterning protective layer to form a pixel electrode. Compared with the well known manufacturing method ofa pixel structure, the invention can simplify processing steps and reduces the manufacturing cost of photomask.

Description

像素结构的制作方法 The method of making a pixel structure

技术领域 FIELD

本发明涉及一种像素结构的制作方法,且特别涉及一种使用激光剥离工 The present invention relates to a method for manufacturing a pixel structure, and more particularly relates to using a laser lift-off

艺(laser ablation process)来制作半导体层的像素结构的制作方法。 Yi (laser ablation process) to make a pixel structure manufacturing method of the semiconductor layer. 背景技术 Background technique

显示器为人与信息的沟通界面,目前以平面显示器为主要发展的趋势。 Communication interface display for people with information, currently flat panel display as the main development trends. 平面显示器主要有以下几种:有机电激发光显示器(organic electroluminescence display)、等离子体显示器(plasma display panel)以及薄膜晶体管液晶显示器等(thin film transistor liquid crystal display)。 The flat panel display are the following: organic electroluminescent display (organic electroluminescence display), plasma display panel (plasma display panel) and a thin film transistor liquid crystal display (thin film transistor liquid crystal display). 其中,又以薄膜晶体管液晶显示器的应用最为广泛。 Among these are a thin film transistor liquid crystal display is most widely. 一般而言,薄膜晶体管液晶显示器主要由薄膜晶体管阵列基板(thin film transistor array substrate)、彩色滤光阵列基板(color filter substrate)和液晶层(liquid crystal layer)所构成。 In general, a thin film transistor liquid crystal display is mainly composed of a thin film transistor array substrate (thin film transistor array substrate), a color filter array substrate (color filter substrate) and a liquid crystal layer (liquid crystal layer) is constituted. 其中,薄膜晶体管阵列基板包括多条扫描线(scan lines)、多条数据线(data lines)以及多个阵列排列的像素结构(pkd unit),且各个像素结构分别与对应的扫描线及数据线电性连接。 Wherein the thin film transistor array substrate includes a plurality of scan lines (scan lines), a plurality of data lines (data lines) and a plurality of pixels arranged in an array structure (pkd unit), and each of the pixel structures respectively corresponding to the scanning lines and data lines electrically connected.

图1A〜图1G为公知像素结构的制作方法示意图。 FIG 1G is a schematic view of FIG 1A~ well-known method for manufacturing the pixel structure. 首先,请参照图1A, 提供基板IO,并通过第一道光掩模工艺于基板10上形成栅极20。 First, referring to FIG. 1A, the IO board, and the gate electrode 20 is formed on the substrate 10 through a first photomask process. 接着,请参照图1B,在基板10上形成栅极绝缘层30以覆盖住栅极20。 Next, referring to FIG 1B, a gate insulating layer 30 to cover the gate electrode 20 on the substrate 10. 然后,请参照图1C,通过第二道光掩模工艺于栅极绝缘层30上形成位于栅极20上方的沟道层40。 Then, referring to Figure 1C, the second photomask process is formed on the gate insulating layer of the channel layer 30 over the gate electrode 2040. 之后,请参照图1D,通过第三道光掩模工艺于沟道层40的部分区域以及栅极绝缘层30的部分区域上形成源极50以及漏极60。 Next, referring to 1D, a source electrode 50 is formed on a portion 60 and a drain region of the channel layer 40 and a partial region of the gate insulating layer 30 by a third photomask process. 一般而言, 沟道层40的材质为非晶硅(amorphous silicon),值得一提的是,为了减少沟道层40与源极50之间以及沟道层40与漏极60之间的接触阻抗,实务上可利用离子掺杂(ion doping)的方式于非晶硅的表面形成N型掺杂区。 Generally, the material of the channel layer 40 is an amorphous silicon (amorphous silicon), it is worth mentioning that, in order to reduce the channel layer 40 between the source contact and the channel layer between the source electrode 50 and drain 60 and 40 ions may be utilized impedance practice doping (ion doping) of N-type doped region is formed on the surface of the amorphous silicon.

请继续参照图1D,源极50与漏极60分别由沟道层40的两侧延伸至栅极绝缘层30上,并将沟道层40的部分区域暴露。 Please continue to 1D, the source 50 and drain 60 extend from both sides of the channel layer 40 to the insulating layer on the gate 30, and the partial region of the channel layer 40 is exposed. 接着,请参照图1E,于基 Next, referring to 1E, the group to

5板10上形成保护层70以覆盖栅极绝缘层30、沟道层40、源极50以及漏极60。 70 is formed to cover the gate insulating layer 30, channel layer 40, source electrode 50 and drain electrode 60 protective layer 105 on the plate. 然后,请参照图1F,通过第四道光掩模工艺将保护层70图案化,以于保护层70中形成接触孔H。 Then, referring to 1F, a process by a fourth photomask protective layer 70 is patterned to form contact holes in the protective layer 70 H. 由图1F可知,保护层70中的接触孔H会将漏极60的部分区暴露。 Seen from 1F, a part of contact holes in the protective layer 70 will drain 60 H exposed. 之后,请参照图1G,通过第五道光掩模工艺于保护层70上形成像素电极80,由图1G可知,像素电极80会透过接触孔H与漏极60电性连接。 Next, referring to FIG. 1G, a pixel electrode 80 is formed on the protective layer 70 through a fifth photomask process, can be seen from FIG. 1G, the pixel electrode 80 through a contact hole H will be connected to the drain electrode 60 electrically. 在像素电极80制作完成之后,便完成了像素结构90的制作。 After the pixel electrode 80 finished, it will complete the production of the pixel structure 90. 承上述,公知的像素结构卯主要是通过五道光掩模工艺来进行制作, 换言之,像素结构90需采用五个具有不同图案的光掩模(mask)来进行制作。 Bearing the above-described known structure of the pixel d is carried out primarily produced by five photomask technology, in other words, the pixel structure 90 requires the use of five photomasks (mask) having different patterns to be produced. 由于光掩模的造价十分昂贵,且每道光掩模工艺均须使用到具有不同图案的光掩模,因此,若无法縮减光掩模工艺的数目,像素结构卯的制造成本将无法降低。 Since the cost is very expensive photomask, and each photomask must use to process a photomask having different patterns, therefore, if the number of photomasks irreducible process, the manufacturing cost of the pixel structure tenon will not decrease.

此外,随着薄膜晶体管液晶显示面板的尺寸日益增加,用来制作薄膜晶体管阵列基板的光掩模尺寸也会随之增加,而大尺寸的光掩模在造价上将更为昂贵,使得像素结构卯的制造成本无法有效地降低。 Further, as the size of the TFT-LCD panel, increasing the size of photomasks used to make a thin film transistor array substrate will increase, and a large-sized photomask will be more expensive in cost, so that the pixel structure Mao manufacturing costs can not be effectively reduced.

发明内容 SUMMARY

本发明涉及一种像素结构的制作方法,其适于降低制作成本。 The present invention relates to a method for manufacturing a pixel structure, which is adapted to reduce production costs. 为具体描述本发明的内容,在此提出一种像素结构的制作方法,其先提供基板,并形成第一导电层于基板上。 Detailed description of the present invention, herein is proposed a method of making a pixel structure which provides the first substrate, and forming a first conductive layer on the substrate. 接着,提供第一遮罩于第一导电层上方,且第一遮罩暴露出部分的第一导电层。 Next, a first mask over the first conductive layer, exposing the mask and the first portion of the first conductive layer. 之后,使用激光经过第一遮罩照射第一导电层,以移除第一遮罩所暴露的部分第一导电层,而形成栅极。 Thereafter, a first mask is irradiated with a laser through the first conductive layer, a first conductive layer to remove the exposed portion of the first mask to form a gate. 继之,形成栅极绝缘层于基板上,以覆盖栅极。 Followed, a gate insulating layer on the substrate to cover the gate. 接着,形成沟道层于栅极上方的栅极绝缘层上。 Next, a channel layer is formed on the gate insulating layer above the gate. 之后,形成源极以及漏极于栅极两侧的沟道层上,且栅极、 沟道层、源极以及漏极构成薄膜晶体管。 Thereafter, the source and drain are formed on the sides of the gate on the channel layer, and a gate, a channel layer, source and drain constitute a thin film transistor. 接着,形成图案化保护层于薄膜晶体管上,以覆盖沟道层并暴露漏极。 Next, a patterned passivation layer on the thin film transistor to cover the exposed channel layer and a drain. 之后,形成电极材料层,以覆盖图案化保护层与暴露的漏极,并且通过图案化保护层使电极材料层同步图案化,以形成像素电极。 Thereafter, the electrode material layer is formed to cover the drain pattern and the exposed protective layer, and the electrode material layer is patterned by synchronization patterned protective layer to form a pixel electrode.

在本发明的像素结构制作方法中,还包括在形成图案化保护层之后,烘烤图案化保护层,以使图案化保护层的顶表面凸出于图案化保护层的侧壁。 In the method of manufacturing the pixel structure of the present invention, further comprising, after forming a patterned protective layer, baking the patterned passivation layer, so that the top surface of the patterned protective layer on the patterned passivation layer projecting sidewalls. 在一个实施例中,图案化保护层的顶表面为蕈状(nmshroom)顶表面。 In one embodiment, the top surface of the patterned protective layer is a mushroom top surface (nmshroom).

6在本发明的像素结构制作方法中,还包括在形成像素电极之后,移除图案化保护层。 6 In the method of manufacturing the pixel structure of the present invention, further comprising, after forming the pixel electrode, removing the patterned protective layer.

在本发明的像素结构制作方法中,形成沟道层的方法包括例如为先形成半导体层于基板上,接着,图案化半导体层,以形成沟道层。 The method of the manufacturing method of the pixel structure of the present invention, comprises forming a channel layer is formed, for example, the first semiconductor layer on a substrate, then patterning the semiconductor layer to form a channel layer. 在另一实施例中,形成沟道层的方法例如为先形成半导体层于基板上,接着,提供第二遮罩于半导体层上方,且第二遮罩暴露出部分的半导体层。 In another embodiment, the channel layer is formed, for example, the first semiconductor layer is formed on the substrate, then providing a second mask over the semiconductor layer, a second mask and the exposed portion of the semiconductor layer. 之后,使用激光经过第二遮罩照射半导体层,以移除第二遮罩所暴露的部分半导体层。 Thereafter, the mask is irradiated with a laser through the second semiconductor layer, a second semiconductor layer to remove portions of the mask is exposed.

在本发明的像素结构制作方法中,形成源极以及漏极的方法例如为先形成第二导电层于沟道层与栅极绝缘层上,接着,图案化第二导电层,以形成源极以及漏极。 In the method of manufacturing the pixel structure of the present invention, a method to form the source and the drain of the first example, the second conductive layer is formed on the channel layer and the gate insulating layer, and then, the second conductive layer is patterned to form the source and a drain.

在本发明的像素结构制作方法中,包括同时形成该沟道层、该源极以及该漏极。 In the method of manufacturing the pixel structure of the present invention, comprising simultaneously forming the channel layer, the source and drain. 在一个实施例中,同时形成该沟道层、该源极以及该漏极的方法例如为先形成半导体层于栅极绝缘层上,接着,形成第三导电层于半导体层上。 In one embodiment, the channel layer are formed simultaneously, the source and drain, for example, the method of the first semiconductor layer is formed on the gate insulating layer, and then forming a third conductive layer on the semiconductor layer. 继之,形成光致抗蚀剂层于栅极上方的第三导电层上,其中光致抗蚀剂层可分为第一光致抗蚀剂区块与位于第一区块两侧的第二光致抗蚀剂区块,且第一光致抗蚀剂区块的厚度小于第二光致抗蚀剂区块的厚度。 Followed by forming a first photoresist layer on the third conductive layer over the gate electrode, wherein the photoresist layer may be divided into a first photoresist on both sides of the first block and the block the second photo-thickness of the resist thickness of the titanium block photoresist block, and a first photoresist block is smaller. 接着,以光致抗蚀剂层为掩模对第三导电层与半导体层进行第一蚀刻工艺。 Next, the photoresist layer as a mask layer on the third conductive semiconductor layer and the first etching process. 然后,减少光致抗蚀剂层的厚度,直到第一光致抗蚀剂区块被完全移除。 Then, to reduce the thickness of the photoresist layer is completely removed until a first block of photoresist. 最后,以剩余的第二光致抗蚀剂区块为掩模对第三导电层进行第二蚀刻工艺,以使剩余的第三导电层构成源极与漏极,而半导体层构成沟道层。 Finally, the remaining second photoresist as a mask to block the third conductive layer is a second etching process, so that the remaining conductive layer constituting the third source and the drain, and the semiconductor layer constituting the channel layer . 在另一实施例中,同时形成沟道层、源极以及漏极的方法例如为先形成半导体层于栅极绝缘层上,接着,形成第二导电层于半导体层上。 In another embodiment, simultaneously forming the channel layer, source and drain, for example, a method to form a first semiconductor layer on the gate insulating layer, and then, the second conductive layer is formed on the semiconductor layer. 之后,形成光致抗蚀剂层于栅极上方的第二导电层上,其中光致抗蚀剂层可分为第一光致抗蚀剂区块与位于第一区块两侧的第二光致抗蚀剂区块,且第一光致抗蚀剂区块的厚度小于第二光致抗蚀剂区块的厚度。 Thereafter, the photoresist layer is formed on the second conductive layer over the gate electrode, wherein the photoresist layer may be divided into a first photoresist on both sides of the first block and the second block the second photo-resist thickness tile thickness of the photoresist block, and a first photoresist block is smaller. 继之,以光致抗蚀剂层为掩模对第二导电层进行第一蚀刻工艺以及对半导体层进行第二蚀刻工艺。 Followed, in the photoresist layer as a mask for etching the second conductive layer is a first process and a second semiconductor layer of the etching process. 之后,减少光致抗蚀剂层的厚度, 直到第一光致抗蚀剂区块被完全移除。 Thereafter, to reduce the thickness of the photoresist layer is completely removed until a first block of photoresist. 接着,以剩余的第二光致抗蚀剂区块为掩模对第二导电层进行第三蚀刻工艺以及对半导体层进行第四蚀刻工艺, 以使剩余的第二导电层构成源极以及漏极,而半导体层构成沟道层。 Next, the remaining second photoresist as a mask to block the second conductive layer and the third semiconductor layer is an etching process for a fourth etching process, so that the remaining second conductive layer constituting a source and a drain electrode, the channel layer and the semiconductor layer.

上述形成光致抗蚀剂层的第一光致抗蚀剂区块与第二光致抗蚀剂区块的方法例如是经过半调式光掩模工艺或灰调式光掩模工艺。 The method of the first photoresist block and a second block photoresist the photoresist layer is formed, for example, via a half-tone mask or a gray-tone process photomask process. 在另一实施例中,形成光致抗蚀剂层的第一光致抗蚀剂区块与第二光致抗蚀剂区块的方》去也可以是使用激光经过遮罩照射光致抗蚀剂层而形成。 In another embodiment, of forming a photoresist layer of the first photoresist block and a second photoresist block "may be used to mask a laser through the anti-photo-irradiated etching layer is formed. 此外,在其他实施例中,沟道层、源极与漏极的制作方法还包括在形成半导体层之后,先形成欧姆接触层于半导体层表面。 Further, in other embodiments, the channel layer, source and drain manufacturing method further comprises, after forming a semiconductor layer, an ohmic contact layer formed on the first semiconductor layer surface. 接着,经过第一蚀刻工艺与第二蚀刻工艺,移除 Next, after the first etching process and the second etching process, to remove

对应于第二光致抗蚀剂区块之外的欧姆接触层。 A second ohmic contact layer corresponding to the photo-resist outside the block. 上述的减少光致抗蚀剂层r享 Above the photoresist layer to reduce the share r

度的方法包括进行灰化(ashing)工艺。 The method includes the degree of ashing (ashing) process.

在本发明的像素结构制作方法中,形成图案化保护层的方法,在一个实施例中例如是在形成薄膜晶体管之后,形成保护层于薄膜晶体管上。 In the method of manufacturing the pixel structure of the present invention, a patterned protective layer method, in one embodiment, for example, after forming a thin film transistor, a protective layer is formed on the thin film transistor. 接着, 再图案化保护层。 Next, another patterned passivation layer. 在另一实施例中,形成图案化保护层的方法例如是在形成薄膜晶体管之后,形成保护层于薄膜晶体管上。 In another embodiment, the patterned protective layer is formed, for example, after forming a thin film transistor, a protective layer is formed on the thin film transistor. 接着,提供第三遮罩于保护层上方,且第三遮罩暴露出部分的保护层。 Subsequently, a third protective layer above the mask, and the mask to expose the third portion of the protective layer. 然后,使用激光经过第三遮罩照射保护层,以移除第三遮罩所暴露的部分保护层。 Then, the mask is irradiated with a laser through the third protective layer, the third layer to remove portions of the protective mask is exposed.

在本发明的像素结构制作方法中,图案化保护层包括形成于部分栅极绝缘层上。 In the method of manufacturing the pixel structure of the present invention, comprises forming a patterned protective layer on a portion of the gate insulating layer.

在本发明的像素结构制作方法中,图案化保护层的组成包括有机光致抗蚀剂材料。 In the method of manufacturing the pixel structure of the present invention, the patterned passivation layer comprises an organic photoresist material.

在本发明的像素结构制作方法中,形成导电层的方法包括通过溅镀形成铟锡氧化物层或铟锌氧化物层。 The method of the manufacturing method of the pixel structure of the present invention, a conductive layer comprises a layer of indium tin oxide or indium zinc oxide layer is formed by sputtering.

在本发明的像素结构制作方法中,照射于半导体层的激光能量例如是介于10 mJ/cn^至500 mJ/cn^之间。 In the method of manufacturing the pixel structure of the present invention, the laser energy is irradiated to the semiconductor layer, for example, is between 10 mJ / cn ^ to 500 mJ / cn ^. 另外,激光的波长例如是介于100 nm至400腿之间。 Further, for example, the laser wavelength is between 100 nm to 400 legs.

在本发明的像素结构制作方法中,还包括在形成栅极的同时形成下层电容电极,而在形成源极以及漏极的同时形成上层电容电极,其中下层电容电极与上层电容电极构成储存电容器。 In the method of manufacturing the pixel structure of the present invention, further comprising forming a lower capacitor electrode while the gate is formed, the upper layer capacitor electrode is formed simultaneously with the formation of source and drain, wherein the lower capacitor electrode and upper capacitor electrode constitute the storage capacitor.

本发明通过图案化保护层的适当图案在形成导电层的同时,即完成导电层的图案化,以形成像素电极,因此相比于公知的像素结构制作方法,可以简化工艺步骤并减少光掩模的制作成本。 Pixel structure manufacturing method of the present invention by appropriately patterning the patterned passivation layer at the same time forming a conductive layer, i.e., the completion of the patterned conductive layer to form a pixel electrode, as compared to the known process steps can be simplified and reduced photomasks production costs. 此外,在制作半导体层时,激光剥离工艺所使用的遮罩较公知的光掩模简易,因此激光剥离工艺步骤中所使用的遮罩的造价较为低廉。 Further, in the production of the semiconductor layer, the mask used in the laser lift-off process well-known than the photomask simple, so the cost of laser lift-off mask used in process step relatively cheap.

8为让本发明的上述特征和优点能更明显易懂,下文特举优选实施例,并配合所附附图,作详细说明如下。 8 to make the above features and advantages of the invention will become apparent from, the following preferred embodiment Laid For examples conjunction with the accompanying drawings, described in detail below.

附图说明 BRIEF DESCRIPTION

图1A〜图1G为公知像素结构的制作方法示意图。 FIG 1G is a schematic view of FIG 1A~ well-known method for manufacturing the pixel structure.

图2A〜图2H为本发明的一种像素结构的制作方法示意图。 FIG 2A~ FIG schematic 2H method for manufacturing a pixel structure of the present invention.

图3A〜图3C为一种形成沟道层的激光剥离制作方法示意图。 FIG 3C is a schematic view of FIG 3A~ making laser lift-off method of forming a channel layer.

图4A〜图4C为一种形成源极以及漏极的制作方法示意图。 FIG 4C is a schematic view of FIG 4A~ A method of making a source and a drain electrode are formed.

图5A〜图5D为一种同时形成沟道层、源极以及漏极的制作方法示意图。 FIG 5A~ FIG. 5D simultaneously formed as a channel layer, a source electrode and a method for manufacturing a schematic diagram of a drain.

图6A〜图6F为另一种同时形成沟道层、源极以及漏极的制作方法示意图。 FIG 6A~ FIG 6F to another while forming the channel layer, and a method for manufacturing a schematic view of a source drain.

图7A〜图7E为另一种同时形成沟道层、源极以及漏极的制作方法示意图。 FIG 7A~ FIG. 7E to another while forming the channel layer, a schematic view of manufacturing method of the source and drain.

图8A〜图8C为一种形成图案化保护层的激光剥离制作方法示意图。 FIG 8C is a schematic view of FIG 8A~ laser lift-off method for manufacturing a patterned passivation layer is formed.

图9A〜图91为本发明的另一种像素结构的制作方法示意图。 Another method for manufacturing the pixel structure of FIG 91 FIG 9A~ present invention. FIG.

并且,上述附图中的各附图标记说明如下: Further, the above description of each of the reference numerals in the drawings are as follows:

10、 200 基板 10, the substrate 200

20、 212 栅极 20, gate 212

30 栅极绝缘层 A gate insulating layer 30

40、 232 沟道层 40, the channel layer 232

50、 242 源极 50, the source electrode 242

60、 244漏极 60, the drain electrode 244

70 保护层 The protective layer 70

80、 282 像素电极 80, the pixel electrode 282

90 像素结构 90 pixel structure

210 第一导电层 The first conductive layer 210

216 下层电容电极 The lower layer capacitor electrode 216

220 栅极绝缘层 The gate insulating layer 220

230 半导体层 The semiconductor layer 230

240 第二导电层 The second conductive layer 240

9上层电容电极 9 the upper layer capacitor electrode

250 光致抗蚀剂层 The photoresist layer 250

250a 第一光致抗蚀剂区块 250a first photoresist block

250b 第二光致抗蚀剂区块 250b of the second photoresist block

252 图案化光致抗蚀剂层 252 patterned photoresist layer

260 薄膜晶体管 The thin film transistor 260

270 保护层 The protective layer 270

272 图案化保护层 Patterned passivation layer 272

280 导电材料层 A conductive material layer 280

280A、 280B部分导电材料层 280A, 280B portion of the conductive material layer

C 储存电容器 Storage capacitor C

激光 laser

H 接触孔 A contact hole H

M 蕈状的顶表面 Mushroom-shaped top surface M

SI 第一遮罩 SI first mask

S2 第二遮罩 S2 second mask

S3 第三遮罩 S3 third mask

具体实施方式 detailed description

图2A〜图2H为本发明的一种像素结构的制作方法的示意图。 FIG 2A~ FIG schematic 2H method for manufacturing a pixel structure of the present invention. 请参照图2A,首先提供基板200,基板200的材质例如为玻璃、塑胶等硬质或软质材料。 Referring to 2A, a substrate 200 is first provided, the material of the substrate 200, for example, glass, plastic and other hard or soft material. 接着,形成第一导电层210于基板200上,其中第一导电层210例如是通过溅镀(sputtering)、蒸镀(evaporation)或是其他薄膜沉积技术所形成,第一导电层210的材质例如为铝(A1)、钼(Mo)、钛(Ti)、钕(Nd)、上述的氮化物如氮化钼(MoN)、氮化钛(TiN)、其叠层、上述的合金或是其他导电材料。 Next, a first conductive layer 210 is formed on the substrate 200, wherein the first conductive layer 210, for example, by sputtering (sputtering), evaporation (evaporation) or formed by other thin film deposition techniques, the material of the first conductive layer 210 e.g. aluminum (A1), molybdenum (Mo), titanium (Ti), neodymium (Nd), the above-mentioned nitrides such as molybdenum nitride (MoN), titanium nitride (TiN), which is laminated, alloys or other conductive material.

接着,如图2B所示,提供第一遮罩S1于第一导电层210上方,且第一遮罩Sl暴露出部分的第一导电层210,并使用激光L经过第一遮罩Sl照射第一导电层210。 Next, as shown in FIG. 2B, a first mask provided above the first conductive layer 210 is S1, and the first mask to expose the first conductive layer portion 210 Sl, and uses the laser light L is irradiated through the first mask section Sl a conductive layer 210. 详言之,经激光L照射后的第一导电层210会吸收激光L 的能量而自基板200表面剥离(ablation)。 In detail, the first conductive layer 210 by the laser beam L is irradiated absorbs energy of the laser light L peeled from the substrate 200 surface (ablation). 具体而言,用来剥离第一导电层210的激光L的能量例如是介于10mJ/cn^至500mJ/cmZ之间。 Specifically, the energy of the laser L to the release of the first conductive layer 210, for example, between 10mJ / cn ^ to 500mJ / cmZ. 另夕卜,激光L 的波长例如是介于100nm至400nm之间。 Another Bu Xi, L, for example, the wavelength of the laser is between 100nm to 400nm. 特别的是,本实施例的激光L也可利用数字曝光方式(digital exposure)来进行栅极材料层210的剥离程序,其中数字曝光方式具有自动定位以及调整能量的作用,使得激光光束的剥离工艺更为准确。 In particular, the laser light L according to the present embodiment may also utilize a digital exposure system (digital exposure) procedures to release the gate material layer 210, wherein the digital exposure system with automatic positioning and adjusting the energy effect, lift-off process such that the laser beam more accurate.

之后,如图2C所示,移除第一遮罩S1所暴露的部分第一导电层210之后,剩余的第一导电层210构成栅极212。 Thereafter, 2C, removing the first conductive layer exposed portion S1 after the first mask 210, the remaining first conductive layer 210 constituting the gate 212. 值得注意的是,不同于公知使用造价昂贵的光掩模来进行栅极212的制作,本发明使用造价低廉的遮罩Sl 完成栅极212的制作,因此能节省成本。 It is noted that, unlike known to use costly photomask for production of the gate electrode 212, the present invention uses a low cost mask gate 212 to complete the production of Sl, it is possible to save costs. 在本实施例中,像素结构的制作方法还包括在形成栅极212的同时,形成下层电容电极216。 In the present embodiment, a method for manufacturing the pixel structure further includes a gate electrode 212 is formed at the same time, the lower layer capacitor electrode 216 is formed.

接着,请参照图2D,于基板200上形成覆盖栅极212以及下层电容电极216的栅极绝缘层220,其中栅极绝缘层220例如是通过化学气相沉积法(chemical vapor deposition, CVD)或其他合适的薄膜沉积技术所形成,而栅极绝缘层220的材质例如是氧化硅、氮化硅或氮氧化硅等介电材料。 Next, referring to FIG 2D, is formed to cover the gate 220 and the lower capacitor electrode 212 of the gate insulating layer 216 on the substrate 200, wherein the gate insulating layer 220, for example, by chemical vapor deposition (chemical vapor deposition, CVD) or other suitable formed by thin film deposition techniques, the material of the gate insulating layer 220 such as silicon oxide, silicon nitride or silicon oxynitride dielectric material. 接着, 形成沟道层232于栅极212上方的栅极绝缘层200上,而沟道层232的材质例如是非晶硅(amorphoussilicon)或其他半导体材料。 Subsequently, the channel layer 232 is formed on the gate insulating layer 200 above the gate electrode 212, and the material of the channel layer 232 is an amorphous silicon (amorphoussilicon) or other semiconductor materials. 在本实施例中,形成沟道层232的方法例如是通过化学气相沉积法形成半导体层230 (标示于图3A),接着,在图案化半导体层230以形成沟道层232。 In the present embodiment, a method of forming a channel layer 232, for example, a semiconductor layer 230 (shown in FIG. 3A) is formed by a chemical vapor deposition method, and then, the semiconductor layer 230 is patterned to form the channel layer 232.

请接着参照图2E,形成源极242以及漏极244于栅极212两侧的沟道层232上,其中形成源极242以及漏极244的方法包括先形成第二导电层240 (标示于图4A)于沟道层232与栅极绝缘层220上,接着再图案化第二导电层240,而第二导电层240的材质例如为铝(A1)、钼(Mo)、钛(Ti)、钕(Nd)、 上述的氮化物如氮化钼(MoN)、氮化钛(TiN)、其叠层、上述的合金或是其他导电材料。 Next, please refer to FIG. 2E, a source 242 and a drain electrode formed on the channel layer 244 of the gate 212 on both sides 232, 242 wherein a method of forming a source electrode and a drain 244 comprises first forming a second conductive layer 240 (shown in FIG. 4A) on the channel layer 232 and the gate insulating layer 220, followed by patterning the second conductive layer 240, the material of the second conductive layer 240, for example, aluminum (A1), molybdenum (Mo), titanium (Ti), neodymium (Nd), the above-mentioned nitrides such as molybdenum nitride (MoN), titanium nitride (TiN), which is laminated, alloys or other conductive materials. 上述的栅极212、沟道层232、源极242以及漏极244构成薄膜晶体管260。 The above-described gate electrode 212, channel layer 232, source electrode 242 and drain electrode 244 constitute a thin film transistor 260. 另夕卜,如图2E所示,在本实施例中,在形成源极242以及漏极244的同时,还包括形成上层电容电极246,使得下层电容电极216与上层电容电极246构成储存电容器C,以维持良好的显示品质。 Another Bu Xi, 2E, in the present embodiment, in forming the source 242 and the drain 244 at the same time, further comprising forming an upper capacitor electrode 246, such that the lower layer capacitor electrode 216 and the upper capacitor electrode 246 constituting the storage capacitor C in order to maintain a good display quality.

此外,在其他实施例中,可先在半导体层230 (标示于图3A)的表面形成欧姆接触层(未标示),接着,再通过蚀刻工艺移除部分的欧姆接触层(未标示)。 Further, in other embodiments, the first semiconductor layer 230 (shown in FIG. 3A) formed in a surface of the ohmic contact layer (not shown), then, again through the ohmic contact layer etching process removes portions (not shown). 举例而言,可利用离子掺杂(km doping)的方式于半导体层230 (标 For example, ion doping can be used (km doping) semiconductor layer 230 in a manner (superscript

ii示于图3A)的表面形成N型掺杂区,以减少沟道层232与源极242之间以及沟道层232与漏极244之间的接触阻抗。 ii shown in FIG. 3A) formed in a surface region of N-type dopant to reduce the contact resistance between the channel layer 232 between the source 242 and the drain 232 and the channel layer 244.

接着,请参照图2F,形成图案化保护层272于薄膜晶体管260上,以覆盖沟道层232并暴露出部分漏极244。 Next, referring to FIG 2F, patterned passivation layer 272 is formed on the thin film transistor 260, to cover the channel layer 232 and exposing a portion of the drain electrode 244. 如图2F所示,在本实施例中,图案化保护层272所形成的范围包括形成于部分栅极绝缘层220上,图案化保护层272的材质可以例如是丙烯酸树脂、感光性树脂等有机介电材料所组成,也可以例如是氧化硅、氮化硅或氮氧化硅等无机介电材料所组成,而形成图案化保护层272的方法例如是通过光致抗蚀剂涂布或其他合适的薄膜沉积技术,如化学气相沉积法所形成。 2F, in the present embodiment, the range of patterned passivation layer 272 is formed on a portion includes forming the gate insulating layer 220, patterned passivation layer 272 material may be, for example, an acrylic organic resin, a photosensitive resin the dielectric material composed of, for example, may be composed of silicon oxide, silicon nitride or silicon oxynitride, an inorganic dielectric material, a method of patterning the protective layer 272 is formed, for example, by applying a photoresist or other suitable the thin film deposition techniques such as chemical vapor deposition is formed. 接着,请继续参照图2F,以图案化保护层272以及第二导电层240为掩模,进行蚀刻工艺,以移除未被图案化保护层272以及第二导电层240所遮蔽的另一部分栅极绝缘层220,并同时暴露出栅极焊垫(未标示)上的第一导电层210 (未标示)。 Next, proceed to 2F, a patterned passivation layer 272 and the second conductive layer 240 as a mask, an etching process to remove the protective layer 272 is not patterned, and another portion of the gate conductive layer 240 of the second shielded a gate insulating layer 220, and at the same time exposing the gate pad (not shown) on the first conductive layer 210 (not shown).

然后,请参考图2G,形成电极材料层280,以覆盖图案化保护层272与暴露的漏极244,其中电极材料层280的材质为铟锡氧化物或铟锌氧化物, 而形成电极材料层280的方法例如是通过溅镀形成铟锡氧化物层或铟锌氧化物层。 Then, referring to FIG 2G, the electrode material layer 280 is formed to cover the patterned passivation layer 272 and the drain electrode 244 is exposed, wherein the material of the electrode material layer 280 is indium tin oxide or indium zinc oxide, to form an electrode material layer method 280, for example, indium tin oxide or indium zinc oxide layer is formed by sputtering. 由于作为电极材料层280底层的图案化保护层272具有适当厚度,使得在形成电极材料层280时会形成电性绝缘的二部分电极材料层280A与280B。 Since the patterned passivation layer as the electrode material layer 280 of the bottom layer 272 has an appropriate thickness, so that the two parts forming the electrode material layer formed of electrically insulating the electrode material layer 280 280A and 280B in. 详言之,设计者可以适当控制底层图案化保护层272的厚度,并利用电极材料层280的薄膜沉积工艺的非等向性特性,使得电极材料层280根据底层图案化保护层272的厚度落差,形成不连续的二部分电极材料层280A 与280B。 In detail, the designer can appropriately control the thickness of the underlying patterned passivation layer 272, using an electrode material layer 280 of the anisotropic characteristics of the thin film deposition process, such that the gap thickness of the electrode material layer 280 according to the underlying protective layer 272 is patterned , the two-part form a discontinuous layer of electrode material 280A and 280B. 一部分电极材料层280A形成于图案化保护层272上,而另一部分电极材料层280B则形成于基板200与漏极244上。 Part of the electrode material layer 280A is formed on the patterned passivation layer 272, while another portion of the electrode material layer 280B is formed on the substrate 200 and the drain electrode 244. 其中,部分与漏极244 连接的电极材料层280B则构成像素电极282。 Wherein the portion of the drain electrode material layer 244 connected to the pixel electrode 282 constituting 280B. 值得注意的是,不同于公知技术,本实施例利用图案化保护层272的设计,于形成电极材料层280时同步图案化,而完成像素电极282制作,因此本发明可以减少一道光掩模工艺, 并降低工艺的复杂度。 It is noteworthy that, unlike the known art design example using the patterned protective layer 272 of the present embodiment, sync pattern 280 is formed on the electrode material layer, the pixel electrode 282 to complete the production, thus reducing the present invention may be a light-mask process and reduces process complexity. 一般而言,在形成像素电极282之后,更可以将图案化保护层272移除,如图2H所示。 Generally, after forming the pixel electrode 282, but may be patterned passivation layer 272 is removed, shown in Figure 2H. 移除图案化保护层272的方法例如使用剥离液于图案化保护层272与电极材料层280的表面,使得图案化保护层272 的底表面因剥离液的侵入而自薄膜晶体管260表面或栅极绝缘层220表面剥离。 The method of removing the patterned protective layer 272, for example, using a stripping solution to the surface of the protective layer 272 is patterned with the electrode material layer 280, patterned passivation layer such that the bottom surface 272 due to the intrusion of the liquid from the peeling surface or gate thin film transistor 260 surface of the insulating layer 220 peeled off.

12此外,上述形成沟道层232的方法例如可以使用激光剥离工艺来进行制作。 12 In addition, the above-described method of forming the channel layer 232 using a laser lift-off process, for example, can be produced. 图3A〜图3C为一种形成沟道层的激光剥离制作方法示意图。 FIG 3C is a schematic view of FIG 3A~ making laser lift-off method of forming a channel layer. 请先参照图3A,先形成半导体层230于基板200上。 Please 3A, a first semiconductor layer 230 is formed on the substrate 200. 接着参照图3B,提供第二遮罩S2于半导体层230上方,且第二遮罩S2暴露出部分的半导体层230。 Referring next to Figure 3B, a second mask over the semiconductor layer 230 in S2, S2 and the second mask exposes a portion of the semiconductor layer 230. 然后, 使用激光L经过第二遮罩S2照射半导体层230,以移除第二遮罩S2所暴露的部分半导体层230。 Then, using the laser light L passes through the second shield S2 is irradiated semiconductor layer 230, a second mask to remove a portion of the semiconductor layer 230 is exposed S2. 最后如图3C所示,剩余的半导体层230构成沟道层232。 Finally, FIG. 3C, the remaining semiconductor layer 230 constituting the channel layer 232. 特别的是,本实施例的激光L也可利用数字曝光方式来进行半导体层230的剥离程序,其中数字曝光方式具有自动定位以及调整能量的作用,使得激光光束的剥离工艺更为准确。 In particular, the laser light L according to the present embodiment can also be utilized to a digital exposure method peeling procedures semiconductor layer 230, wherein the digital exposure system with automatic positioning and adjusting the energy effect, the laser beam such that the lift-off process more accurate.

此外,图4A〜图4C为一种上述形成源极242以及漏极244的制作方法示意图。 Further, FIG. 4C 4A~ FIG method for manufacturing a schematic diagram 242 and the drain electrode 244 is formed in one of the above sources. 请先参照图4A,先形成第二导电层240于沟道层232与栅极绝缘层220上。 Please 4A, the first form 220 of the second conductive layer 240 on the channel layer 232 and the gate insulating layer. 接着请参照图4B,图案化第二导电层240。 Referring next to Figure 4B, the second conductive layer 240 is patterned. 详言之,例如在栅极212两侧的沟道层232上形成光致抗蚀剂层250,并以此光致抗蚀剂层250 为掩模进行蚀刻工艺,以去除未被光致抗蚀剂层250覆盖的第二导电层240。 In detail, for example, a non-photo-anti photoresist layer 250, and thus the photoresist layer 250 as a mask, an etching process, to remove the channel layer 232 on both sides of the gate electrode 212 etching a second conductive layer covering layers 240,250. 移除光致抗蚀剂层250之后,如图4C所示,在栅极212两侧的沟道层232 上分别形成源极242以及漏极244。 After removing the photo 250, as shown in FIG. 4C, the resist layer, the drain electrode 242 and source 244 are formed on the channel layer 232 on both sides of the gate electrode 212. 在本实施例中,光致抗蚀剂层250还形成于下层电容电极216上方的栅极绝缘层220上,以于进行蚀刻工艺后,形成上层电容电极246,而使得上层电容电极246与下层电容电极216构成储存电容器C。 In the present embodiment, photoresist layer 250 is also formed on the gate insulating layer 220 over the lower capacitor electrode 216, in order to perform the etching process, the upper layer capacitor electrode 246 is formed such that the upper layer and the lower layer capacitor electrode 246 the storage capacitor electrode 216 constituting the capacitor C. 第二导电层240的材质例如为铝(A1)、钼(Mo)、钛(Ti)、钕(Nd)、 上述的氮化物如氮化钼(MoN)、氮化钛(TiN)、其叠层、上述的合金或是其他导电材料。 Material of the second conductive layer 240, for example, aluminum (A1), molybdenum (Mo), titanium (Ti), neodymium (Nd), the above-mentioned nitrides such as molybdenum nitride (MoN), titanium nitride (TiN), which stack layer, alloys or other conductive materials. 在本实施例中,蚀刻工艺例如为进行湿式蚀刻,在其他实施例中, 蚀刻工艺也可以是干式蚀刻。 In the present embodiment, an etching process such as wet etching, in other embodiments, the etching process may be dry etching. 另外,去除光致抗蚀剂层250的工艺例如是湿式蚀刻工艺。 Further, the removal process of the resist layer 250, for example light-induced wet etching process.

当然,在另一实施例中,上述的沟道层232、源极242以及漏极244也可以是同时形成的。 Of course, in another embodiment, the channel layer 232, source electrode 242 and drain electrode 244 may be simultaneously formed. 举例而言,图5A〜图5D为一种同时形成沟道层、源极以及漏极的制作方法示意图。 For example, FIG. 5D 5A~ FIG simultaneously formed as a channel layer, a source electrode and a method for manufacturing a schematic diagram of a drain. 如图5A所示,在形成栅极绝缘层220之后, 依序在栅极绝缘层220上形成半导体层230以及第二导电层240。 5A, after forming the gate insulating layer 220, semiconductor layer 230 are sequentially and the second conductive layer 240 is formed on the gate insulating layer 220. 接着请参照图5B,于栅极212上方的第二导电层240上形成光致抗蚀剂层250。 Referring next to Figure 5B, a photoresist layer 250 is formed on the second conductive layer over the gate electrode 240,212. 如图5B所示,在栅极212上方的光致抗蚀剂层250可分为第一光致抗蚀剂区块250a与位于第一光致抗蚀剂区块250a两侧的第二光致抗蚀剂区块250b,且第一光致抗蚀剂区块250a的厚度小于第二光致抗蚀剂区块250b的厚度,在本实施例中,形成光致抗蚀剂层250的第一光致抗蚀剂区块250a与第二光致抗蚀剂区块250b的方法例如是经过半调式光掩模工艺或灰调式光掩模工艺,在其他实施例中,形成光致抗蚀剂层250的第一光致抗蚀剂区块250a 与第二光致抗蚀剂区块250b的方法也可以例如是使用激光经过遮罩(未氺示示)照射光致抗蚀剂层250而形成。 As shown, gate 212 over the photoresist layer 250 can be divided into the first 250a and the second optical photoresist blocks located in the first block 250a photoresist sides 5B photoresist block 250b, and the first photo-resist thickness less than the thickness of the second block 250a photoresist block 250b, in this embodiment, is formed a photoresist layer 250 the first photoresist block 250a and the second method photoresist block 250b, for example through a photomask halftone process or gray-tone photo mask process, in other embodiments, the anti-photo-formed etching a first layer of photoresist blocks 250 and 250a of the second method photoresist block 250b may be, for example, using a laser through a mask (not shown Shui shown) irradiating the photoresist layer 250 form. 接着,请继续参照图5B,以光致抗t虫剂层250为掩模对第二导电层240进行第一蚀刻工艺。 Next, Still referring to Figure 5B, the light-induced anti-insect t 250 as a mask layer a second conductive layer 240 is a first etching process. 之后,减少光致抗蚀剂层250的厚度,直到第一光致抗蚀剂区块250a被完全移除,如图5C所示, 其中减少光致抗蚀剂层250厚度的方法例如是采用灰化的方式。 Thereafter, to reduce the thickness of the photoresist layer 250, until the first block 250a photoresist is completely removed, as shown in FIG. 5C, wherein reducing the thickness of the photo-resist layer 250 is employed, for example, ashing manner. 请继续参照图5C,在第一光致抗蚀剂区块250a被完全移除之后,再以剩余的第二光致抗蚀剂区块250b为掩模对半导体层230与第二导电层240进行第二蚀刻工艺。 Still referring to Figure 5C, after the first photoresist block 250a is completely removed, then the remaining second photoresist block 250b as a mask layer 230 and the second conductive semiconductor layer 240 performing a second etching process. 在本实施例中,第一蚀刻工艺例如为进行湿式蚀刻,在其他实施例中, 蚀刻工艺也可以是干式蚀刻。 In the present embodiment, the first etching process, for example, wet etching, in other embodiments, the etching process may be dry etching. 接着,请参照图5D,在进行去除剩余的光致抗蚀剂层250的工艺之后,剩余的第二导电层240构成源极242与漏极244, 而半导体层230构成沟道层232。 After Next, referring to Figure 5D, the remaining process of the photoresist layer 250 during the removal of the remaining second conductive layer 240 constituting a source 242 and drain 244, and the semiconductor layer 230 constituting the channel layer 232. 在本实施例中,去除光致抗蚀剂层250的工艺例如是湿式蚀刻工艺。 In the present embodiment, the process of removing the photo-resist layer 250 is, for example, wet etching process. 当然,在本实施例中,光致抗蚀剂层250包括形成于下层电容电极216的上方。 Of course, in the present embodiment, photoresist layer 250 is formed over the lower layer comprising a capacitor electrode 216.

图6A〜图6F为另一种同时形成沟道层、源极以及漏极的制作方法示意图。 FIG 6A~ FIG 6F to another while forming the channel layer, and a method for manufacturing a schematic view of a source drain. 沟道层232、源极242以及漏极244也可以是同时形成的。 A channel layer 232, source electrode 242 and drain electrode 244 may be simultaneously formed. 如图6A所示,在形成栅极绝缘层220之后,依序在栅极绝缘层220上形成半导体层230 以及第二导电层240。 As shown in FIG. 6A, after forming the gate insulating layer 220, semiconductor layer 230 are sequentially and the second conductive layer 240 is formed on the gate insulating layer 220. 接着请参照图6B,在栅极212上方的光致抗蚀剂层250可分为第一光致抗蚀剂区块250a与位于第一光致抗蚀剂区块250a两侧的第二光致抗蚀剂区块250b,且第一光致抗蚀剂区块250a的厚度小于第二光致抗蚀剂区块250b的厚度,在本实施例中,形成光致抗蚀剂层250的第一光致抗蚀剂区块250a与第二光致抗蚀剂区块250b的方法例如是经过半调式光掩模工艺或灰调式光掩模工艺,在其他实施例中,形成光致抗蚀剂层250 的第一光致抗蚀剂区块250a与第二光致抗蚀剂区块250b的方法也可以例如是使用激光经过遮罩(未标示)照射光致抗蚀剂层250而形成。 Referring next to FIG. 6B, the gate 212 of the photoresist layer 250 can be divided over the first light 250a and the second block is within a first photoresist photoresist 250a on both sides of the block photoresist block 250b, and the first photo-resist thickness less than the thickness of the second block 250a photoresist block 250b, in this embodiment, is formed a photoresist layer 250 the first photoresist block 250a and the second method photoresist block 250b, for example through a photomask halftone process or gray-tone photo mask process, in other embodiments, the anti-photo-formed etching a first layer of photoresist blocks 250 and 250a of the second method photoresist block 250b may be, for example, using a laser through a mask (not shown) irradiating the photoresist layer 250 form. 继之,请参照图6C,以光致抗蚀剂层250为掩模对第二导电层240进行第一蚀刻工艺, 并且继续以光致抗蚀剂层250为掩模对半导体层230进行第二蚀刻工艺。 Followed, please 6C, the photoresist layer to 250 as a mask the second conductive layer 240 is a first etching process, and continues to the photoresist layer 250 as a mask for the first semiconductor layer 230 second etching process. It

14后,如图6D所示,减少光致抗蚀剂层250的厚度,直到第一光致抗蚀剂区块250a被完全移除,其中减少光致抗蚀剂层250厚度的方法例如是采用灰化的方式。 After 14, 6D, reducing the thickness of the photoresist layer 250, until the first block 250a photoresist is completely removed, wherein the method of reducing the thickness of the photo-resist layer 250 is, for example, using ashing manner. 接着,请参照图6E,以剩余的第二光致抗蚀剂区块250b为掩模对栅极212上方的第二导电层240进行第三蚀刻工艺,并且继续以剩余的第二光致抗蚀剂区块250b为掩模对半导体层230进行第四蚀刻工艺。 Next, referring to 6E, the remainder to a second block 250b photoresist as a mask the second conductive layer 212 over the gate 240 for the third etching process, and continues to the remaining second light-induced anti corrosion inhibitors block 250b as a mask for the fourth semiconductor layer 230 etching process. 之后, 请参照图6F,在进行去除剩余的光致抗蚀剂层250的工艺之后,剩余的第二导电层240构成源极242以及漏极244,而半导体层230构成沟道层232。 After Next, referring to FIG. 6F, the remaining process of the photoresist layer 250 during the removal of the remaining source 240 constituting the second conductive layer 242 and a drain electrode 244, the semiconductor layer 230 constituting the channel layer 232. 值得一提的是,上述同时形成沟道层、源极以及漏极的制作方法可以利用二次蚀刻工艺或四次蚀刻工艺,当然,在其他实施例中,同时形成沟道层、源极以及漏极的制作方法也可以仅利用一次蚀刻工艺,本发明并不限定同时形成沟道层、源极以及漏极的制作方法的蚀刻次数。 It is worth mentioning that the simultaneous formation of the channel layer, a source and a drain of the manufacturing method may utilize four secondary etching process or an etching process, of course, in other embodiments, the channel layer is simultaneously formed, and a source the method of making the drain may also utilize only the first etching process, the present invention is not limited to the channel layer is formed simultaneously, the number of etching process of the source and drain.

图7A〜图7E为另一种同时形成沟道层232、源极242以及漏极244的制作方法示意图。 FIG 7A~ FIG 7E is a schematic diagram of another while forming a channel layer 232, source 242 and drain 244 of the manufacturing method. 首先请参照图7A,在形成栅极绝缘层220之后,依序在栅极绝缘层220上形成半导体层230以及第二导电层240,并于栅极212上方的第二导电层240上形成图案化光致抗蚀剂层252。 Referring first to Figure 7A, after forming the gate insulating layer 220, semiconductor layer 230 and the second conductive layer 240 are sequentially formed on the gate insulating layer 220, and a pattern is formed on the second conductive layer over the gate electrode 240212 of the photoresist layer 252. 接着,如图7B所示, 以图案化光致抗蚀剂层252为掩模,移除图案化光致抗蚀剂层252所暴露的第二导电层240,其中移除第二导电层240的方法例如为进行湿式蚀刻,而半导体层230的材质可为非晶硅、多晶硅、微晶硅、单晶硅或上述材质的组合。 Next, as shown in FIG. 7B, the patterned photoresist layer 252 as a mask, removing the patterned photo-resist layer, a second conductive layer 252 exposed 240, wherein the second conductive layer 240 is removed method, for example, wet etching, and the semiconductor layer 230 material may be amorphous silicon, polysilicon, microcrystalline silicon composition, or said single-crystal silicon material. 此外,在其他实施例中,也可先在半导体层230的表面形成欧姆接触层(未标示),其中欧姆接触层的制作材质以及目的如上述,于此不再累述。 Further, in other embodiments, may be formed in the surface of the first semiconductor layer 230 is an ohmic contact layer (not shown), wherein a material making ohmic contact layer and the object as described above, this is no longer tired. 请继续参考图7C,使用激光L剥除部分图案化光致抗蚀剂层252,以使图案化光致抗蚀剂层252暴露出部分的第二导电层240。 Please refer to Figure 7C, the use of laser light L is stripped portion of the patterned photoresist layer 252, so that a second patterned photo-conductive layer 240 to expose portions 252 of the resist layer. 特别的是,本实施例的激光L也可利用数字曝光方式来进行图案化光致抗蚀剂层252的剥除, 其中数字曝光方式具有自动定位以及调整能量的作用,使得激光光束的剥离工艺更为准确。 In particular, the laser light L according to the present embodiment using a digital exposure method may be patterned photoresist layer 252 is stripped, wherein the digital exposure system with automatic positioning and adjusting the energy effect, lift-off process such that the laser beam more accurate. 接着,再以图案化光致抗蚀剂层252以及第二导电层240为掩模,移除部分半导体层230,其中移除半导体层230的方法可以利用等向蚀刻工艺或是非等向蚀刻工艺来达成。 Subsequently, then the patterned photoresist layer 252 and the second conductive layer 240 as a mask, removing a portion of the semiconductor layer 230, wherein a semiconductor layer 230 can be removed using isotropic etching process or the like to a non-etching process to achieve. 值得注意的是,如图7C所示,在移除半导体层230的步骤中,第二导电层240可以作为保护层,避免位于栅极212上方的半导体层230被移除,因此,此步骤也可在使用激光L剥除部分图案化光致抗蚀剂层252之前进行。 Notably, FIG. 7C, the step of removing the semiconductor layer 230, the second conductive layer 240 can serve as a protective layer to prevent the semiconductor layer 212 located above the gate electrode 230 is removed, therefore, this step can using a laser L stripping section prior to patterned photo-resist layer 252. 接着,请参照图7D,以图案化光致抗 Next, referring to Figure 7D, the patterned photo-anti

15蚀剂层252为掩模,移除图案化光致抗蚀剂层252所暴露出的第二导电J1 240,以使位于栅极212上方的第二导电层240构成源极242以及漏极244, 而位于栅极212上方的半导体层230构成沟道层232。 15 etch layer 252 as a mask, removing the patterned photo-resist layer 252 of the second conductive exposed by Jl 240, so that the second conductive layer 212 over the gate 240 constituting a source and a drain 242 244, and the semiconductor layer 212 located above the gate electrode 230 constituting the channel layer 232. 最后,如图7E所示, 去除图案化光致抗蚀剂层252后,栅极212、沟道层232、源极242以及漏极244构成薄膜晶体管260。 Finally, as shown in FIG. 7E, after removing the patterned photo 252, gate electrode 212, channel layer 232 the resist layer, a source electrode 242 and drain electrode 244 constitute a thin film transistor 260. 当然,在本实施例中,图案化光致抗蚀剂层252 包括形成于下层电容电极216的上方,以于形成源极242与漏极244的同时, 形成上层电容电极246。 Of course, in the present embodiment, the patterned photoresist layer 252 is formed over the lower layer comprising a capacitor electrode 216 to electrode 244 to form the source and the drain 242 while the upper layer capacitor electrode 246 is formed. 值得注意的是,本实施例不同于公知技术,利用激光L来定义图案化光致抗蚀剂层252的图案,进而同时形成沟道层232、源极242以及漏极244的制作,因此可以减少一道光掩模的工艺以及光掩模的成本。 Notably, the present embodiment is different from the known art, the use of laser light L to define patterned photoresist layer 252 is patterned, thereby simultaneously forming the channel layer 232, a drain 242 and source 244 prepared, it can be reducing the cost of the process and a photomask of a photomask. 此外,上述形成图案化保护层272的方法例如是在形成薄膜晶体管260 之后,形成保护层270于栅极绝缘层220与薄膜晶体管260上。 Further, the above-described method of forming a patterned passivation layer 272 is formed, for example, after the thin film transistor 260, the thin film transistor 220 is formed on the gate insulating layer 260 on the protective layer 270. 接着,再图案化保护层270。 Subsequently, the protective layer 270 and then patterned. 在另一实施例中,形成图案化保护层272的方法也可以例如使用激光剥离工艺来进行制作。 In another embodiment, a patterned protective layer 272 may be, for example, using a laser lift-off process for production. 图8A〜图8C为一种形成图案化保护层的激光剥离制作方法示意图。 FIG 8C is a schematic view of FIG 8A~ laser lift-off method for manufacturing a patterned passivation layer is formed. 请先参照图8A,在形成薄膜晶体管260之后, 接着如图8B,于栅极绝缘层220与薄膜晶体管260上形成保护层270,并提供第三遮罩S3于保护层270上方,且第三遮罩S3暴露出部分的保护层270。 Please Referring to Figure 8A, after forming the thin film transistor 260, then 8B, the protective layer 270 is formed on the gate insulating layer 220 and the thin film transistor 260, and a mask provided above the third protective layer 270 is S3, and the third the protective mask layer to expose portions 270 S3. 然后,使用激光L经过第三遮罩S3照射保护层270,以移除第三遮罩S3所暴露的部分保护层270。 Then, a laser L is irradiated S3 through the third protective layer mask 270, a third mask to remove portions of the protective layer 270 is exposed S3. 最后,如图8C所示,形成图案化保护层272。 Finally, as shown in FIG. 8C, the patterned passivation layer 272 is formed. 值得注意的是,图8C为尚未进行栅极绝缘层220的蚀刻工艺的示意图。 It is noteworthy that the schematic diagram of FIG. 8C Not etching process of the gate insulating layer 220 is. 特别的是,本实施例的激光L也可利用数字曝光方式来进行图案化保护层272的制作,其中数字曝光方式具有自动定位以及调整能量的作用,使得激光光束的剥离工艺更为准确。 In particular, the laser light L according to the present embodiment may also be performed using a digital exposure method to produce patterned passivation layer 272, wherein the digital exposure system with automatic positioning and adjusting the energy effect, the laser beam such that the lift-off process more accurate.

第二实施例 Second embodiment

图9A〜图91为本发明的第二实施例中像素结构的制作方法的示意图, 其中形成沟道层232的方法例如是利用上述图3A〜图3C来进行制作。 The method of making a schematic view of the method according to a second embodiment of the pixel structure of FIG 91 FIG 9A~ present invention, wherein the channel layer 232 is formed of, for example, to 3C was produced using the above-described FIG 3A~ FIG. 此外, 形成源极242以及漏极244的制作方法可以利用上述图4A〜图4C或图5A〜 5D来进行制作,或者是以上述图7A〜图7E来进行制作。 Further, the source electrode 242 and drain electrode 244 may be made using the method of the above-described FIG. 4C or FIG 4A~ FIG 5A~ 5D to produce, or is the above-described FIG. 7E FIG 7A~ be produced. 由于图9A〜图9F 的步骤与第一实施例的图2A〜图2F相似,故此处省略其描述。 Since the step of FIG. 2F 9A~ FIG. 9F is similar to the first embodiment of FIG. 2A~ FIG therefore description thereof is omitted herein.

请参照图9G,在形成图案化保护层272之后,烘烤图案化保护层272, Referring to FIG. 9G, after forming patterned passivation layer 272, patterned passivation layer 272 is baked,

16以使图案化保护层272的顶表面凸出于该图案化保护层的侧壁。 16 so that the top surface of the patterned passivation layer 272 protrudes from the sidewall of the patterned protective layer. 在本实施例中,图案化保护层272的顶表面实质上呈现蕈状顶表面M。 In this embodiment, the top surface of the patterned passivation layer 272 exhibits a substantially mushroom-shaped top surface M. 值得一提的是, 在实务上必须考虑烘烤工艺的温度、加热速度、加热时间等工艺误差,因此图案化保护层272的形状可能因工艺误差而产生些许的变异,大致上其顶表面约略凸出于侧壁使其形状呈现蕈状图案,但本发明的图案化保护层272的顶表面形状并不以此为限。 It is worth mentioning that the baking process must take into account temperature, heating rate, heating time and other errors in practice, so the shape of the patterned passivation layer 272 may be generated due to process variation little error, a top surface substantially approximate its shape protruding from the side wall exhibits a mushroom-like pattern, but the shape of the top surface of the patterned passivation layer 272 according to the present invention is not limited thereto.

然后,请参考图9H,形成电极材料层280,以覆盖图案化保护层272与暴露的漏极244,而形成电极材料层280的方法例如是通过溅镀形成铟锡氧化物层或铟锌氧化物层。 Then, referring to FIG 9H, the electrode material layer 280 is formed to cover the patterned passivation layer 272 and the exposed drain electrode 244, an electrode material layer 280 is formed, for example, indium tin oxide or indium zinc oxide layer by sputtering layer. 由于图案化保护层272的顶表面凸出于图案化保护层272的侧壁为蕈状的顶表面M,因此在形成电极材料层280时会形成电性绝缘的两部分电极材料层280A与280B。 Since the top surface of the patterned protective layer 272 may protrude from the sidewalls of the patterned passivation layer 272 is a top surface M of a mushroom, so that the two portions forming an electrode material layer formed of electrically insulating the electrode material layer 280 280A and 280B . 一部分电极材料层280A形成于图案化保护层272上,另一部分电极材料层280B则形成于基板200以及漏极244上。 Part of the electrode material layer 280A is formed on the patterned passivation layer 272 and another portion 280B of the electrode material layer 200 is formed on the substrate 244, and a drain. 其中,部分与漏极244连接的电极材料层280B则构成像素电极282。 Wherein the portion of the drain electrode material layer 244 connected to the pixel electrode 282 constituting 280B. 值得注意的是,不同于公知技术,在本实施例中利用图案化保护层272的顶表面凸出于该图案化保护层的侧壁的图案的设计,于形成电极材料层280时同步图案化,而完成像素电极282制作,因此可以减少一道光掩模工艺,并降低工艺的复杂度。 It is noted that, unlike known technique, in the present embodiment designs the protective layer using the patterned top surface 272 protrudes from the sidewall of the patterned passivation layer embodiment, forming the synchronization pattern of the electrode material layer 280 , the pixel electrode 282 to complete production, thereby reducing a light-mask process, and reduce the complexity of the process.

一般而言,在形成像素电极282之后,更可以将图案化保护层272移除, 如图91所示。 Generally, after forming the pixel electrode 282, but may be patterned passivation layer 272 is removed, as shown in FIG 91. 移除图案化保护层272的方法例如使用剥离液于图案化保护层272与电极材料层280的表面,使得图案化保护层272的底表面因剥离液的侵入而自薄膜晶体管260表面或栅极绝缘层220表面剥离。 The method of removing the patterned protective layer 272, for example, using a stripping solution to the surface of the protective layer 272 is patterned with the electrode material layer 280, patterned passivation layer such that the bottom surface 272 due to the intrusion of the liquid from the peeling surface or gate thin film transistor 260 surface of the insulating layer 220 peeled off.

基于上述,本发明在像素电极的制作上,不同于公知技术使用一道光掩模来进行像素电极的的制作,而是在形成电极材料层的同时,通过适当图案的图案化保护层直接图案化电极材料层,以形成像素电极,因此相比于公知技术具有减少工艺步骤的优点。 Based on the above, the present invention is in the production of the pixel electrode, unlike the known art using a photomask for manufacturing the pixel electrode, but the electrode material layer is formed at the same time, by patterning the protective layer is suitably patterned direct patterning electrode material layer to form the pixel electrode, as compared to the known technique has the advantage of reducing the process steps. 并且,本发明采用激光照射的方式形成半导体层,而非采用公知的光刻蚀刻工艺,因此本发明所提出的像素结构的制作方法至少具有下列优点: Further, the present invention is by way of laser irradiation of a semiconductor layer is formed, instead of using well-known photolithographic etching process, thus making the proposed method of the pixel structure of the present invention have at least the following advantages:

l.本发明提出的像素结构的制作方法,其像素电极工艺不需使用光刻工艺,故相比于光刻工艺所使用的高精度光掩模工艺,能降低光掩模的制作成本。 l. The method of making a pixel structure proposed by the present invention, which processes the pixel electrode without using a photolithography process, so compared to the photolithography process with high accuracy photomask used in the process, to reduce the manufacturing cost of the photomask.

172。 172. 由于制作像素结构的工艺较少,可以减少冗长的光掩模工艺(如光至i 抗蚀剂涂布、软烤、硬烤、曝光、显影、蚀刻、光致抗蚀剂剥除等)制作像素结构时所产生的缺陷。 Since fewer pixel structure production process, a photomask is possible to reduce the lengthy process (e.g., light-to-i resist coating, soft baking, hard bake, exposure, development, etching, photoresist stripping, etc.) production when defective pixel resulting structure.

3。 3. 本发明所提出的激光剥离部分半导体层的方法可以应用于像素修补中的像素电极的修补,以在像素结构工艺中,移除可能残留的像素电极(ITO residue),解决像素电极之间的短路问题,进而增加生产合格率。 The method of laser lift-off portion of the semiconductor layer proposed by the present invention may be applied to the pixel electrode of the pixel repair patch in order to process the pixel structure, the pixel electrode may remove residual (ITO residue), a short circuit between the pixel electrode solution issue, thereby increasing production yield.

4。 4. 利用数字曝光方式可以使得激光光束自动定位,并可根据膜层的材质以及厚度调整能量,因此可以提高生产合格率。 Using the digital exposure method may be such that the laser beam is automatically positioned, the energy can be adjusted according to the material and thickness of the coating layer, it is possible to improve the production yield.

虽然本发明已以优选实施例公开如上,但其并非用以限定本发明,任何本领域技术人员在不脱离本发明的精神和范围内,当可作些许改动与润饰, 因此本发明的保护范围当视随附的权利要求所界定的范围为准。 While the invention has been disclosed in the above preferred embodiments, but not intended to limit the present invention, anyone skilled in the art without departing from the spirit and scope of the present disclosure, may make various modifications and variations, and the scope of the invention when the view defined by the claims appended scope of equivalents.

Claims (20)

1.一种像素结构的制作方法,包括: 提供基板; 形成第一导电层于该基板上; 提供第一遮罩于该第一导电层上方,且该第一遮罩暴露出部分的该第一导电层; 使用激光经过该第一遮罩照射该第一导电层,以移除该第一遮罩所暴露的部分该第一导电层,而形成栅极; 形成栅极绝缘层于该基板上,以覆盖该栅极; 形成沟道层于该栅极上方的该栅极绝缘层上; 形成源极以及漏极于该栅极两侧的该沟道层上,且该栅极、该沟道层、该源极以及该漏极构成薄膜晶体管; 形成图案化保护层于该薄膜晶体管上,以覆盖该沟道层并暴露出该漏极;以及形成电极材料层,以覆盖该图案化保护层与暴露的该漏极,并且通过该图案化保护层使该电极材料层同步图案化,以形成像素电极, 其中该激光的能量介于10mJ/cm2至500mJ/cm2之间。 1. A method for manufacturing the pixel structure, comprising: providing a substrate; forming a first conductive layer on the substrate; providing a first mask over to the first conductive layer and exposing the first portion of the first mask a conductive layer; using a laser irradiated through the first mask of the first conductive layer, the first mask to remove the exposed portion of the first conductive layer to form a gate; forming a gate insulating layer on the substrate so as to cover the gate electrode; forming a channel layer on the gate insulating layer over the gate electrode; a source electrode formed on the channel layer and a drain to the sides of the gate, and the gate of the channel layer, the source electrode and the drain electrode constituting the thin film transistor; patterning and forming the electrode material layer to cover; forming a patterned passivation layer on the thin film transistor to cover the channel layer and expose the drain the protective layer and the exposed drain electrode, and the passivation layer by patterning the electrode material layer synchronization patterned to form the pixel electrode, wherein the energy of the laser is between 10mJ / cm2 to 500mJ / cm2.
2. 如权利要求1所述的像素结构的制作方法,还包括在形成图案化保护层之后,烘烤该图案化保护层,以使该图案化保护层的顶表面凸出于该图案化保护层的侧壁。 2. The manufacturing method of the pixel structure according to claim 1, further comprising, after forming a patterned protective layer, baking the patterned passivation layer, so that the patterned passivation layer protrudes from the top surface of the patterned passivation sidewall layer.
3. 如权利要求2所述的像素结构的制作方法,其中图案化保护层的顶表面为蕈状顶表面。 3. The manufacturing method of the pixel structure as claimed in claim 2, wherein the top surface of the protective layer is patterned mushroom-shaped top surface.
4. 如权利要求1所述的像素结构的制作方法,还包括在形成该像素电极之后,移除该图案化保护层。 4. The manufacturing method of the pixel structure according to claim 1, further comprising, after forming the pixel electrode, removing the patterned protective layer.
5. 如权利要求1所述的像素结构的制作方法,其中形成该沟道层的方法包括:形成半导体层于该基板上;以及图案化该半导体层,以形成该沟道层。 5. The manufacturing method of the pixel structure according to claim 1, wherein the method of forming the channel layer comprising: forming a semiconductor layer on the substrate; and patterning the semiconductor layer to form the channel layer.
6. 如权利要求1所述的像素结构的制作方法,其中形成该沟道层的方法包括:形成半导体层于该基板上;提供第二遮罩于该半导体层上方,且该第二遮罩暴露出部分的该半导体层;以及使用激光经过该第二遮罩照射该半导体层,以移除该第二遮罩所暴露的部分该半导体层。 6. The manufacturing method of the pixel structure according to claim 1, wherein the method of forming the channel layer comprising: forming a semiconductor layer on the substrate; providing a second mask above the semiconductor layer, and the second mask exposing a portion of the semiconductor layer; and using laser irradiated through the mask of the second semiconductor layer to remove portions of the second semiconductor layer of the mask is exposed.
7. 如权利要求1所述的像素结构的制作方法,其中形成该源极以及该漏极的方法包括-形成第二导电层于该沟道层与该栅极绝缘层上;以及图案化该第二导电层,以形成该源极以及该漏极。 7. The manufacturing method of the pixel structure according to claim 1, wherein forming the source and drain of the method comprises - forming a second conductive layer on the channel layer and the gate insulating layer; and patterning the a second conductive layer to form the source and drain.
8. 如权利要求1所述的像素结构的制作方法,其中形成该图案化保护层的方法包括:形成保护层于该薄膜晶体管上;以及图案化该保护层。 8. The manufacturing method of the pixel structure according to claim 1, wherein the method of forming a patterned passivation layer comprises: forming a protective layer on the thin film transistor; and patterning the protective layer.
9. 如权利要求1所述的像素结构的制作方法,其中形成该图案化保护层的方法包括:形成保护层于该薄膜晶体管上;提供第三遮罩于该保护层上方,且该第三遮罩暴露出部分的该保护层;以及使用激光经过该第三遮罩照射该保护层,以移除该第三遮罩所暴露的部分该保护层。 9. The manufacturing method of the pixel structure according to claim 1, wherein the method of forming a patterned passivation layer comprises: forming a protective layer on the thin film transistor; providing a third mask to the upper protective layer, and the third the mask exposes a portion of the protective layer; and using laser irradiated through the mask of the third protective layer, the third mask to remove the exposed portions of the protective layer.
10. 如权利要求1所述的像素结构的制作方法,其中形成该第一导电层的方法包括通过溅镀、蒸镀以及薄膜沉积技术择其一所形成。 10. The method of manufacturing method of the pixel structure according to claim 1, wherein the first conductive layer is formed by including sputtering, evaporation, and thin film deposition techniques choose one formed.
11. 如权利要求1所述的像素结构的制作方法,其中该激光的波长介于100nm至400nm之间。 11. The manufacturing method of the pixel structure according to claim 1, wherein a wavelength of between 100nm to 400nm range of the laser.
12. 如权利要求1所述的像素结构的制作方法,其中该图案化保护层包括形成于部分该栅极绝缘层上。 12. The manufacturing method of the pixel structure according to claim 1, wherein the patterned layer comprises a protective portion formed on the gate insulating layer.
13. 如权利要求1所述的像素结构的制作方法,其中该图案化保护层的组成包括有机光致抗蚀剂材料。 13. The manufacturing method of the pixel structure according to claim 1, wherein the composition of the patterned protective layer comprises an organic photoresist material.
14. 如权利要求1所述的像素结构的制作方法,还包括在形成该栅极的同时形成下层电容电极,而在形成该源极以及漏极的同时形成上层电容电极,其中该下层电容电极与该上层电容电极构成储存电容器。 14. The manufacturing method of the pixel structure wherein the lower layer capacitor electrode as claimed in claim, further comprising forming a lower capacitor electrode forming the gate at the same time, while simultaneously forming the source and drain of the upper layer capacitor electrode is formed, the upper layer capacitor electrodes and the storage capacitor.
15. 如权利要求1所述的像素结构的制作方法,其中该基板为玻璃或塑胶。 15. The manufacturing method of the pixel structure according to claim 1, wherein the substrate is a glass or plastic.
16. 如权利要求1所述的像素结构的制作方法,其中该沟道层为n型掺杂非晶硅。 16. The manufacturing method of the pixel structure according to claim 1, wherein the channel layer is an n-type doped amorphous silicon.
17. 如权利要求1所述的像素结构的制作方法,其中该第一导电层的材质为铝、钼、钛、钕、氮化钼、氮化钛,或前述材质的组合。 17. The manufacturing method of the pixel structure according to claim 1, wherein the material of the first conductive layer of aluminum, molybdenum, titanium, neodymium, molybdenum nitride, titanium nitride, or combinations of the foregoing materials.
18. 如权利要求1所述的像素结构的制作方法,其中该源极以及漏极的材质为铝、钼、钛、钕、氮化钼、氮化钛,或前述材质的组合。 18. The manufacturing method of the pixel structure according to claim 1, wherein the source and drain is made of aluminum, molybdenum, titanium, neodymium, molybdenum nitride, titanium nitride, or combinations of the foregoing materials.
19. 如权利要求1所述的像素结构的制作方法,其中该电极材料层的材质为铟锡氧化物或铟锌氧化物。 19. The manufacturing method of the pixel structure according to claim 1, wherein the electrode material layer is made of indium tin oxide or indium zinc oxide.
20. 如权利要求1所述的像素结构的制作方法,其中使用激光的步骤还包括:利用数字曝光方式进行激光光束自动定位及调整能量。 20. The manufacturing method of the pixel structure according to claim 1, wherein the step of using a laser further comprises: a digital exposure method using a laser beam positioning and automatically adjust the energy.
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