JPH07221321A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain an electrode structure which does not require any aligning margin and has an aligning property by forming a first electrode of a metal having low transmissivity against X rays so that the electrode can have a self-aligning relation with other electrodes. CONSTITUTION:An X-ray resist 10 is irradiated with X rays from an Si substrate 100 side. The X rays are transmitted through the substrate 100 in areas where no X-ray absorbing material nor W electrode 5 which becomes a reflecting material exist and arrive at the resist 10. As a result, the resist 10 is exposed to the X rays and forms an exposed areas 10b. Since the area with the electrode 5 does not transmit the X rays, the resist 10 on the electrode 5 is not exposed. Since the polymer chain of the resist is cut and the resist becomes soluble in a developing solution in the exposed areas 10b, whereas the unexposed area 10a remains insoluble, when a positive resist is used as the resist 10, the resist 10 can be patterned in a self-aligning way with back gate electrodes 5 and 4. Therefore, the need of an aligning margin can be eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is a high speed, low power consumption LS.
Thin film SOI (Silicon On Insulator) type used as I
The present invention relates to a semiconductor device having a plurality of electrode structures found in a double-gate type MOS transistor used for LSIs and the manufacturing method thereof, and particularly when the thickness of the semiconductor active layer is 0.1 μm.
The present invention relates to a semiconductor device having a double-gate structure applied to a double-gate MOS transistor of a fully-depleted thin-film SOI of m or less, and a method for manufacturing the same.

[0002]

2. Description of the Related Art In a thin film SOI (Silicon On Insulator) MOS transistor, a double gate structure in which another electrode is formed under the channel has a drain withstand voltage reduction, short channel effect suppression, and mutual conductance (good signal transmission). It is known that it has an excellent feature that it has an increase in the (measure of length). In particular, the fully depleted thin film SOIMOS transistor with a semiconductor active layer thickness of 0.1 μm or less is a semiconductor device that can achieve high speed and high integration because it can reduce pn junction capacitance, gate capacitance, and well isolation region. Has been actively researched in recent years. The problem with this thin film SOIMOS transistor is the decrease in drain breakdown voltage. This decrease in drain breakdown voltage becomes an increasingly important problem as the channel length becomes shorter. Therefore, in order to prevent the decrease of the drain breakdown voltage, the impurity concentration of the channel region is increased, but this increases the influence of impurity scattering on the electrons or holes traveling in the channel region,
It causes a decrease in mobility and further a decrease in drain current.
Reduce the benefits of IMOS.

On the other hand, a double gate structure in which another gate electrode (back gate, hereinafter referred to as BG electrode) is formed under the channel is drawing attention as a structure capable of overcoming the above problems. That is, the double gate structure is
Compared to a normal single-gate thin film SOIMOS transistor, the controllability of the channel potential by the gate is improved, and as a result, the electric field concentration is relaxed at the drain edge where the electric field strength is maximized, the short channel effect is suppressed, and the drain breakdown voltage is reduced. The decrease can be suppressed. Furthermore,
By providing two gate electrodes on the upper and lower sides, that is, a front gate (hereinafter referred to as FG electrode) and a BG electrode, the current path becomes double that in the case of a normal single gate, and therefore the drain current is doubled. be able to. As a result, the transconductance, which is a measure of the goodness of signal transmission, can be increased.

[0004]

However, when this double gate structure is to be formed by the conventional method for manufacturing a thin film SOIMOS transistor, after forming the BG electrode, the active layer is formed by using the wafer bonding technique. above
Since the step of forming the FG electrode is followed, it is difficult to align and match the FG electrode and the BG electrode, and at present, the alignment margin (Δ in FIG.
L) is provided to make the BG electrode larger than the target, and as a result, in the process of forming the FG electrode using a mask such as photoresist, the tolerance of mask misalignment is suppressed. Therefore, there is a known problem that the overlap capacitance between the gate and the source / drain increases, and the high frequency characteristics are significantly deteriorated. For example, Tanaka et al. (Technical report of the Institute of Electronics, Information and Communication Engineers SDM92-137-149, Vol. 92, No.424, P.35)
~ 40, January 1993), the degree of this alignment margin is the high frequency characteristics of the device (delay time τd and cutoff frequency ft).
The effect of the above is investigated by simulation, and as a result, when the alignment margin ΔL is 0.1 μm, the ideal ΔL = 0
It is stated that τd is three times slower than μm, ft is reduced to 1/2 or less, and that ΔL = 0.05 μm or less is required to exceed the characteristics of a single gate. However, there is a problem that such alignment accuracy cannot be realized by a conventional technique, for example, a well-known forming method using photolithography and etching which requires mask alignment.

Therefore, in view of the above points, an object of the present invention is to
To provide a semiconductor device having a structure having an embedded electrode and another electrode overlapping with the buried electrode and having a more consistent electrode structure with no need for alignment margin and having good electrical characteristics, and a method for manufacturing the same. is there.

[0006]

In order to solve the above-mentioned problems, the structure of the present invention comprises a first electrode and at least one or more layers which are opposed to each other with an insulating film or a semiconductor active layer separated from each other. In the semiconductor device having the other electrode, the first electrode has a metal having a low X-ray transmittance, and the other electrode and the first electrode have a self-aligned arrangement relationship. According to another aspect of the present invention, there is provided a semiconductor active layer that is insulated and separated from a substrate by an isolation insulating film, a first electrode embedded in the isolation insulating film via a first insulating thin film, and the semiconductor. In a semiconductor device comprising a second electrode formed via a second insulating thin film at a position facing the first electrode on an upper surface sandwiching an active layer, the first electrode is a metal having a low X-ray transmittance. And the second electrode is formed in a self-aligned manner with the first electrode and has an arrangement relationship of overlapping with the same width. In the structure of the invention related thereto, the first electrode is either tungsten (W) or tantalum (Ta) or titanium (Ti) or molybdenum (Mo), or polysilicon (p-Si) and each of the metals. An electrode formed of a multilayer film is a back gate electrode, the second electrode is a front gate electrode, and the semiconductor device is a double gate type SOIMOS transistor.

This invention of the method for manufacturing a semiconductor device is intended to manufacture a semiconductor device having a first electrode and another electrode different from the first electrode facing each other with an insulating film or an insulated semiconductor active layer interposed therebetween. In the method, a first electrode forming step of forming the first electrode with a metal having a low X-ray transmittance as a component, and a self-aligned X-ray exposure method using the first electrode as an X-ray mask after forming the first electrode. And another electrode forming step of forming another electrode. And the structure of the invention of another method is a buried electrode formed by being buried inside the isolation insulating film through the first insulating thin film on the lower surface of the semiconductor active layer which is insulated and separated from the substrate by the isolation insulating film, A method of manufacturing a semiconductor device, comprising: a front surface electrode formed via a second insulating thin film at a position facing the embedded electrode on an upper surface sandwiching the semiconductor active layer, and including a metal having a low X-ray transmittance. A step of forming a buried electrode, in which a buried electrode is formed, and after the buried electrode is formed, X-rays are irradiated from behind the substrate, and the X-ray resist on the surface side is exposed in a self-aligned manner using the buried electrode as a mask. And a front surface electrode forming step of forming an electrode.

[0008]

[Function] In a semiconductor device in which electrodes are arranged to face each other with a semiconductor active layer separated by insulation interposed therebetween, one electrode is formed using a metal having a low X-ray transmittance such as tungsten (W). The other electrode is self-aligned and the other electrode is commonly known L
It is formed by the SI process. Specifically, first, a buried electrode using a metal or polycrystalline silicon having a low X-ray transmittance and a multi-layered film made of these metals is formed by a generally known LSI process. To form the surface electrode, an X-ray resist is applied to the main surface on which polycrystalline silicon is deposited, and X-rays are irradiated from the back side of the substrate. Then, since the embedded electrode region including the metal film having a low X-ray transmittance does not transmit X-rays, the resist on the embedded electrode is not exposed, and the other regions transmit X-rays to the surface. The applied resist is exposed. By using the positive type as the resist, the resist on the buried electrode remains as it is after development, and the resist pattern is formed in self-alignment with the buried electrode region. Using the remaining resist pattern as a mask, the polycrystalline silicon is etched to form a surface electrode.

[0009]

EXAMPLES The present invention will be described below based on specific examples. FIG. 1 is a schematic structural sectional view of a thin film SOIMOS transistor having a double gate electrode structure to which the present invention is applied. Although the basic structure of this transistor is a well-known structure, the electrode material to be formed is specified in the present invention, and this structure realizes a self-aligned structure that could not be achieved in the past. There is.

Bonding poly-Si provided on the substrate 100
The layer 7 is further provided with the isolation insulating layer 6 (SOI structure),
First electrodes 5 and 4 are formed therein. The portion of the first electrode 5 is made of a metal having a low X-ray transmittance such as tungsten (W), and the poly-Si first electrode 4 is provided thereon. On the first electrodes 5 and 4, there is a first insulating thin film 3 that insulates and separates the first electrode, and further, an insulating film 2 is formed around the semiconductor active layer 1a and source / drain regions 1b. ing. This semiconductor active layer 1
a, a source / drain region 1b is formed on this region, which has a well-known MOS type transistor structure, and has a source electrode and a drain electrode 13, and a second electrode 9a is an interlayer insulating film 12 between these electrodes. It is protected and separated, and is formed in self-alignment with the first electrodes 5 and 4.

In this structure, the two electrodes sandwiching the semiconductor active layer 1a from above and below, the double gate electrodes of the first electrodes 5 and 4 and the second electrode 9a, apply an electric field of the same potential from above and below the active layer. The semiconductor active layer 1a is sufficiently affected by it, and can be completely depleted to efficiently function as a transistor. That is, the drain breakdown voltage is reduced,
It has the excellent effects of preventing short channel effects and increasing transconductance, which is a measure of good signal transmission. Conventionally, as described above, the effect is hindered by the size mismatch between the two gate electrodes due to manufacturing reasons. Therefore, by applying the present invention, a self-aligned duffle gate structure can be formed, so that a SOI transistor having a duffle gate structure with almost ideal characteristics can be realized.

A method of manufacturing the thin film SOIMOS transistor having the double gate electrode structure will be described below. (1) As shown in FIG. 2 (a), first, a LOCOS oxide film 2 and a gate oxide film 3 are formed on a Si substrate 1 by a well-known normal IC process, and poly Si4 is further deposited thereon. ,
A W (tungsten) metal (or Ti (titanium) or other metal having a large absorption coefficient for X-rays for exposure) electrode 5 is deposited thereon, and a predetermined back gate (BG) electrode is formed by a method such as dry etching. Pattern into a shape. The gate oxide film 3 is a first insulating thin film, and the W electrode 5 and the poly-Si4 are first electrodes (embedded electrodes).

(2) Next, an insulating film 6 such as SiO ₂ and poly-Si 7 for forming a bonding surface are deposited by the LPCVD method or the like. Then, the surface of the poly-Si 7 is flattened by grinding and polishing (FIG. 2 (b)). (3) Next, the flattened surface of the poly-Si 7 and the mirror surface of the other mirror-polished Si substrate 100 are bonded by a so-called wafer direct bonding method, and high-temperature heat treatment is performed to bond them. Then, the back surface side of the substrate 1 is ground and polished, and the LOCOS oxide film 2 is used as a stopper to selectively polish the film to a thickness of 1 μm or less.
The Si active layer 1a is formed (FIG. 2 (c)). (4) Next, the gate oxide film 8 is formed on the surface of the Si active layer 1a by oxidation. This gate oxide film 8 is the front gate
(FG) It becomes an oxide film (second insulating thin film). Then, poly-Si 9 for the front gate electrode is deposited, and an X-ray resist 10 is applied on it (FIG. 2 (d)).

(5) Here, as shown in FIG. 3E, when X-rays for exposure are irradiated from the Si substrate 100 side, the X-rays are in an area where there is no W electrode 5 serving as an X-ray absorber / reflector. Then, the light passes through the substrate, reaches the X-ray resist 10, and is exposed to light.
0b is formed. On the other hand, in the region where the W electrode 5 is formed, X-rays are not transmitted, so that the resist 10 on the W electrode 5 is not exposed. If a positive type is used as the X-ray resist 10, the polymer chains of the resist are broken in the exposed area 10b to be soluble in the developing solution, while the unexposed area 10a is insoluble, so that the X-ray resist 10a is formed as shown in FIG. As shown in (f), the back gates (BG) 5 and 4 are patterned by self-alignment.

(6) After that, dry etching is performed,
The front gate electrode 9a is formed by etching the poly-Si9 (Fig. 3 (g)), and the source
A double gate type thin film in which a front gate (FG) and a back gate (BG) are formed in a self-aligned manner by forming a drain diffusion layer 1b, an interlayer insulating film 12 such as BPSG, and an aluminum electrode 13.
Obtain a SOIMOS transistor (Fig. 1).

Summarizing the above steps, the method of manufacturing a double gate type thin film SOIMOS transistor semiconductor device includes an insulating film forming step of forming a LOCOS insulating film for insulation separation and a buried gate insulating film on a Si substrate, A buried gate electrode formation process using a low X-ray transmittance metal and a poly-Si film formation process after the isolation insulating film formation process,
After that, a wafer direct bonding step of laminating and adhering the wafer on the poly-Si film, and a Si active layer forming step of forming a semiconductor active layer with a thickness of 1 μm or less by polishing and forming a front gate insulating film on it A front gate electrode formation step of forming a front surface electrode by self-aligned X-ray exposure using an X-ray resist, and a source / drain electrode forming a contact hole by covering the front surface gate electrode with an insulating layer. And a drain electrode forming step. The above can be called the X-ray self-alignment method.

The semiconductor active layer is sandwiched between a first electrode (embedded electrode) formed in a separation insulating film for insulatingly separating the semiconductor active layer and the underlying substrate, below the semiconductor active layer. A second electrode (surface electrode), which is formed on the main surface side of the semiconductor active layer via an insulating thin film at a position facing the first electrode, and which is different from the first electrode and is made of a plurality of materials, or at least one In the semiconductor device including the above multiple electrodes, the first electrode is made of a metal having a low X-ray transmittance, and the one or more multiple electrodes and the first electrode, or the second electrode and the The same effect can be obtained even in a structure such as a semiconductor device characterized by having the same width as the first electrode and having a self-aligned arrangement relationship. This is the case where the number of surface electrodes is not limited to one, and it is desired to form the electrodes in a self-aligned manner such as the structure of a floating gate of EPROM.

Further, depending on the intended semiconductor substrate, a metal having a large absorption coefficient for X-rays for exposure (a metal having a low X-ray transmittance) is not used as an electrode, but is simply formed as a shield mask for electrode formation ( (Shield mask step), and the first electrode and the second electrode may be formed by X-ray exposure based on this. In this case, the difference from the usual X-ray exposure method is that the first electrode and the second electrode are formed in a self-aligned manner by a shield mask.

The first electrode is composed of tungsten (W), tantalum (Ta), titanium (Ti) or molybdenum (Mo), or a multilayer film of polysilicon (p-Si) and each metal. Being an electrode means either a tungsten single layer, a tantalum single layer, a titanium single layer, or a molybdenum single layer, or a composite layer of any of these metals, an alloy layer, or a p-Si layer and a tungsten layer. , A p-Si layer and a tantalum layer, a p-Si layer and a titanium layer, a p-Si layer and a molybdenum layer, and all combinations thereof.

[0020]

As described above, in a semiconductor device having a double gate structure or the like, by the manufacturing method according to the present invention, the first electrode and the buried electrode are self-aligned with the upper second electrode,
A surface electrode can be formed. According to the structure and the manufacturing method such as the double gate type thin film SOIMOS transistor shown in this embodiment, the original effect of the self-aligned double gate structure,
That is, excellent characteristics such as suppression of drain breakdown voltage reduction, suppression of short channel effect, and increase of mutual conductance can be exhibited, and high integration and speedup of a semiconductor device can be realized.

[Brief description of drawings]

FIG. 1 is a schematic structural sectional view of a double gate type SOIMOS transistor of the present invention.

FIG. 2 is a manufacturing process diagram (1) of the transistor of FIG. 1 of the present invention.

FIG. 3 is a manufacturing process diagram (2) of the transistor of FIG. 1 of the present invention.

FIG. 4 is a manufacturing process drawing of a conventional double-gate SOIMOS transistor.

[Explanation of symbols]

1 Silicon substrate 1a Silicon active layer (semiconductor active layer) 1b Source / drain diffusion layer 2 LOCOS oxide film 3 Gate oxide film (first insulating film) 4 Polysilicon (first electrode) 5 Tungsten (W, X-ray transmittance Low metal, back gate (BG), first electrode, buried electrode 6 Separation insulating layer 7 Polysilicon (for forming junction surface) 8 Gate oxide film 9 Polysilicon (front gate (FG), second electrode,
Surface electrode 10 X-ray resist (positive type) 10a X-ray resist (unexposed area) 10b X-ray resist (exposed area) 11 Exposure X-ray 12 Interlayer insulating film 13 Aluminum electrode (source / drain electrode) 100 Substrate

Claims (5)

[Claims] 1. A semiconductor device having a first electrode and another electrode composed of at least one or more layers, which are opposed to each other with an insulating film or a semiconductor active layer separated from each other insulated, wherein the first electrode is X. A semiconductor device comprising a metal having a low linear transmittance, wherein the other electrode and the first electrode are in a self-aligned arrangement relationship. 2. A first electrode formed by being embedded in the inside of the isolation insulating film via a first insulating thin film on the lower surface of the semiconductor active layer which is insulated and separated from the substrate by the isolation insulating film, and the semiconductor active layer. In a semiconductor device comprising a second electrode formed via a second insulating thin film at a position facing the first electrode on both sides of the first electrode, the first electrode includes a metal having a low X-ray transmittance. The semiconductor device is characterized in that the second electrode is formed in a self-aligned manner with the first electrode and has an arrangement relationship in which the second electrode has the same width and overlaps. 3. The first electrode is made of tungsten (W), tantalum (Ta), titanium (Ti), molybdenum (Mo), or a multilayer film of polysilicon (p-Si) and each metal. The semiconductor device according to claim 2, wherein the electrode is a back gate electrode, the second electrode is a front gate electrode, and the semiconductor device is a double-gate SOIMOS transistor. 4. A method for manufacturing a semiconductor device having a first electrode and another electrode different from the first electrode, which are opposed to each other with an insulating film or an insulating semiconductor active layer interposed therebetween, wherein the first electrode has an X-ray transmittance. A first electrode forming step of forming a low metal as a component, and another electrode forming step of forming another electrode by self-aligned X-ray exposure using the first electrode as an X-ray mask after forming the first electrode. A method of manufacturing a semiconductor device, comprising: 5. An embedded electrode formed by being embedded in the inside of the isolation insulating film through a first insulating thin film on the lower surface of the semiconductor active layer that is insulated and separated from the substrate by the isolation insulating film, and the semiconductor active layer. A method of manufacturing a semiconductor device, comprising: a surface electrode formed via a second insulating thin film at a position facing the embedded electrode on the sandwiched upper surface; forming an embedded electrode containing a metal having low X-ray transmittance. A step of forming a buried electrode, and a surface on which a X-ray is irradiated from the back of the substrate after the buried electrode is formed and a surface side X-ray resist is exposed in a self-aligned manner using the buried electrode as a mask to form a surface electrode. A method of manufacturing a semiconductor device, comprising: an electrode forming step.