JPH0721790B2 - Data transmission equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device, and more particularly, to data provided from a preceding stage section at an arbitrary time interval autonomously and selectively in any of a plurality of parallel latter stage sections. The present invention relates to a data transmission device for transmitting data to a car.

[Prior Art] In a processing device such as an electronic computer, a plurality of processing units are coupled via communication by digital signals. Then, the plurality of data processes are distributed to the plurality of processing units and performed. In this way, when data processing is distributed and performed by a plurality of processing units, the contents of data processing in each processing unit are generally different, and the data necessary for performing each data processing and the obtained data are obtained. The results are also different. In such a processing device, if a plurality of processes required for data transfer are connected by wiring for each data process and an input / output port is provided in each processing unit, the hardware becomes very complicated and the device becomes There is a problem that the cost increases as the size increases.

Therefore, the inventors of the present application proposed a data transmission device capable of transmitting different types of data groups using the same data transmission path in Japanese Patent Laid-Open No. 174857/1987.

FIG. 11 is a schematic block diagram of the above-mentioned proposed data transmission device.

First, with reference to FIG. 11, a data transmission device for branching and transmitting data into two transmission lines will be briefly described.

In FIG. 11, each of the data transmission paths 1, 7, and 8 is composed of a data register that holds data and a transfer control unit. An identifier transmission line 2 is provided in parallel with the data transmission line 1. The identifier transmission path 2 transmits an identifier called a tag. This identifier indicates to which of the two data transmission paths 7 and 8 the data transmitted on the data transmission path 1 should be transmitted.

When both data transmission paths 7 and 8 are empty and data can be transmitted, UK signals 5a and 6a are supplied from the data transmission paths 7 and 8 to the control units 5 and 6, respectively. Also, the data transmission path
UL signal 5d from the data transmission line (not shown) in the latter stage of 7,8,
6d is similarly given to the control units 5 and 6, respectively. U
The L signals 5d and 6d are given from the data transmission lines at the subsequent stages of the data transmission lines 7 and 8, and indicate that the data transmission lines are empty and data can be transmitted. When the UK signal 5a, the UL signal 5d, the UK signal 6a, and the UL signal 6a are given, the control units 5 and 6 cause the data transmission path 7 and the subsequent data transmission path, and the data transmission path 8 and the subsequent step transmission. It is determined that the road and the road are free. If the control units 5 and 6 hold the data up to that point, the control units 5 and 6 transfer the data to the data transmission line in the subsequent stage, and enter an active state that enables control to branch the subsequent data.

The NOR gate 4 receives the discrimination signal 5 from the control units 5 and 6 indicating that the respective control units are in the idle state and activated.
When receiving b and 6b, the AK signal is given to the data transmission line 1 and the identifier transmission line 2.

As described above, the data transmission paths 7 and 8 and the data transmission paths 7 and 8 from the control units 5 and 6 are controlled by the UK signal and the UL signal from the data transmission paths in the subsequent stages, based on whether or not the subsequent stages are in the empty state. , 8 is permitted or prohibited, and branching and transmission from the data transmission path 1 to the control unit 5 or 6 are permitted or prohibited.

For example, an identifier indicating that the data transmitted on the data transmission line 1 should be transmitted on the data transmission line 7 is given from the identifier transmission line 2 to the identifier decoding unit 3. The identifier decoding unit 3 decodes the identifier received from the identifier transmission line 2,
The control signal 5c is given to the control unit 5 to activate it. As a result, the data transmitted from the data transmission line 1 can be transmitted to the data transmission line 7 via the control unit 5.

On the contrary, when the identifier indicating that data should be transmitted to the data transmission line 8 is given from the identifier transmission line 2 to the identifier decoding unit 3, the identifier decoding unit 3 gives the control signal 6c to the control unit 6 and sends it. Activate. As a result, the data transmitted to the data transmission line 1 can be transmitted to the data transmission line 8 via the control unit 6.

If, for example, the data transmission path 7 among the data transmission paths 7 and 8 and the data transmission paths subsequent to them are holding data or transmitting data, the UK signal 5a is given to the control unit 5. Absent. Similarly, the UL signal 5d is not given to the control unit 5 even when the data transmission line subsequent to the data transmission line 7 holds or is transmitting data. For this reason, the control unit 5 determines that the data transmission path 7 or the data transmission path at the subsequent stage is in transmission or is in a blocked state. As a result, the control unit 5 stores the data input to the register (not shown) included in the control unit 5 and outputs “H” to one input terminal of the NOR gate 4.
Give level signal. Therefore, the NOR gate 4 is closed and the AK signal is not given to the data transmission line 1 and the identifier transmission line 2.

That is, one of the data transmission paths 7 and 8 and the data transmission paths of the subsequent stages thereof holds or is transmitting data, and the control units 5 and 6 hold data. In this case, the data transmitted to the data transmission line 1 is held in the data transmission line 1 without being input to the control units 5 and 6.

However, if the data transmission line 7 and the subsequent data transmission line or the data transmission line 8 and the subsequent data transmission line and the control unit 5 or 6 complete the data transmission and transition from the blocked state to the empty state, the control unit 5 or 6 are activated. Thereby, the data held in the data transmission path 1 can be autonomously branched again according to the identifier.

[Problems to be Solved by the Invention] In the above-described data transmission device, although the data given from the front stage can be sent to any one of a plurality of parallel rear stages, the data given from the front stage Could not be sent to all of the parallel post-stages.

An object of the present invention is to enable transmission of a plurality of different types of data groups using the same data transmission path, and to autonomously transfer data given from a front stage to any or all of a plurality of parallel rear stages. A data transmission device capable of selectively and selectively transmitting data.

[Means for Solving the Problem] A data transmission apparatus according to the present invention is a data transmission apparatus for sending data given from a front stage section to a plurality of rear stage sections provided in parallel. Prepare

The data transmitted by the data transmission device includes an identifier for designating any one or all of the plurality of subsequent stages. The discriminating means discriminates whether the identifier included in the data given from the front part designates any one or all of the plurality of rear stages, and outputs a signal indicating the discrimination result. The control means, in response to the signal from the determination means, sends the data given from the front stage to any one of the plurality of rear stages or to all of the plurality of rear stages.

[Operation] In the data transmission device according to the present invention, it is determined whether the identifier included in the data given from the front part specifies all or all of the rear parts. Based on the determination result, the data given from the preceding stage is transmitted to any of the plurality of succeeding stages or to all of the plurality of succeeding stages.

Therefore, even if different types of data are input at arbitrary time intervals, each data can be autonomously and selectively transmitted to a desired rear stage or all rear stages. Therefore, it is not necessary to provide an input / output port or a special wiring for each data type.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a data transmission device according to an embodiment of the present invention.

In FIG. 1, the data transmission lines 10 and 20 form an input side transmission line. The data transmission line 10 includes a transfer control unit 11, a data holding circuit 12 and a buffer 13. The data transmission path 20 includes a transfer control unit 21, a data holding circuit 22 and a buffer 23. Further, an output side transmission line composed of the data transmission lines 30 and 40 and an output side data transmission line composed of the data transmission lines 60 and 70 are provided in parallel. The data transmission line 30 includes a transfer control unit 31, a data holding circuit 32, and a buffer 33. Similarly, the data transmission line 40 includes a transfer control unit 41, a data holding circuit 42 and a buffer 43,
The data transmission line 60 includes a transfer control unit 61, a data holding circuit 62 and a buffer 63, and the data transmission line 70 includes a transfer control unit 71, a data holding circuit 72 and a buffer 73.

The data given to the data holding circuit 12 from the previous stage is transmitted to the data holding circuit 22. The data received by the data holding circuit 22 is transmitted only to the data holding circuit 62, or is transmitted to both the data holding circuit 32 and the data holding circuit 62.

As shown in FIG. 2, the data transmitted through the data transmission line of this embodiment is packet data composed of an n-bit first word D1 and an n-bit second word D2. The first word D1 of the packet data includes an m-bit identifier. The identifier indicates whether the packet data should be transmitted only to the data transmission line 60 or the data transmission line 30.
And 60 should be transmitted. The first word D1 and the second word D2 of the packet data are transmitted continuously.

The data transmission apparatus shown in FIG. 1 further includes a branch destination designation bit generation unit 91, a comparison / determination logic unit 92 including a comparator, a control unit 93 including a D type flip-flop, and a frequency divider 94 including a D type flip-flop. , And a buffer 95 are provided.

The transfer control unit 11 receives the transmission signal C1 from the preceding stage unit (not shown).
0 is given. In response to the fall of the transmission signal C10, the data holding circuit 12 is supplied with the first word D1 of the packet data from the preceding stage. The transfer control unit 11 gives the "L" level transmission permission signal AK10 to the preceding stage unit. This "L" level transmission permission signal AK10 indicates a transmission prohibited state. When the "H" level transmission permission signal AK20 is given from the transfer control unit 21, the transfer control unit 11 causes the "L" level transmission signal C20.
Is given to the data holding circuit 12 and the transfer control unit 21 via the buffer 13. This "H" level transmission enable signal AK20
Indicates a transmission permitted state. The data holding circuit 12
In response to the fall of the transmission signal C20, the first word D1 of the packet data given from the previous stage is latched and output.

On the other hand, branch destination designation bit generation unit 91 is preset so as to generate a predetermined branch destination designation bit BR. The comparison / determination logic unit 92 compares the identifier included in the first word D1 of the packet data output from the data holding circuit 12 with the branch destination designation bit BR provided from the branch destination designation bit generation unit 91, and they match. If they do not match, an “L” level match signal is output, and if they do not match, “H”
Output level match signal. The match signal is given to the input terminal D of the control unit 93.

The frequency divider 94 divides the transmission signal C20 given from the transfer control unit 11 via the buffer 13 by two, and the divided signal is used as a clock signal C21 for the clock terminal ▲ ▼ of the control unit 93.
Give to. The clock signal C21 falls once every time the transmission signal C20 from the transfer control unit 11 falls twice. That is, the clock signal C21 falls from the "H" level to the "L" level every time two words pass through the data holding circuit 12. In response to the fall of the clock signal C21, the control unit 93 outputs an inverted signal of the match signal applied to the input terminal D as the control signal ▲ ▼ from the inverted output terminal.

When the control signal ▲ ▼ is at "H" level, the buffer 95 becomes non-conductive and the transfer control section 31 becomes inactive. On the contrary, when the control signal ▲ ▼ is at "L" level, the buffer 95 becomes conductive and the transfer control unit 31
Becomes active. That is, when the identifier included in the first word D1 of the packet data matches the branch destination designation bit BR, the data holding circuit 22 is connected only to the data holding circuit 62. Conversely, when the identifier included in the first word D1 of the packet data does not match the branch destination designation bit BR, the data holding circuit 22 is connected to both the data holding circuit 32 and the data holding circuit 62. In the initial state, when the master reset signal ▲ ▼ of "L" level is applied to the reset terminal of the control unit 93, the control signal ▲
▼ becomes the “H” level. Therefore, in the initial state, the data holding circuit 22 is connected only to the data holding circuit 62.

Next, when the transfer control unit 31 gives the "H" level transmission permission signal AK30 and the transfer control unit 61 gives the "H" level transmission permission signal AK60, the transfer control unit 21 sends the transmission signal. In response to the fall of C20, the transmission signal C30 of "L" level is passed through the buffer 23 to the data holding circuit 22.
And the transfer control units 31 and 61. Data holding circuit
In response to the fall of the transmission signal C30, 22 latches and outputs the first word D1 of the packet data given from the data holding circuit 12. Similarly, the second word D2 of the packet data is also latched and output by the data holding circuit 12 following the first word D1.

When the control signal ▲ ▼ is at "H" level, the first word of the packet data output from the data holding circuit 22.
D1 is given only to the data holding circuit 62. This is called a branch. In response to the fall of the transmission signal C30, the transfer control unit 61 gives the “L” level transmission signal C70 to the data holding circuit 62 and the transfer control unit 71 via the buffer 63. The data holding circuit 62 latches and outputs the first word D1 of the packet data supplied from the data holding circuit 22 in response to the fall of the transmission signal C70. Similarly, the second word D2 of the packet data is also latched and output by the data holding circuit 22. At this time, since the control signal ▲ ▼ is held at the "H" level, the data holding circuit 22
The second word D2 of the packet data output from is supplied only to the data holding circuit 62. The first word D1 of the packet data output from the data holding circuit 62 is similarly latched and output by the data holding circuit 72, and the second word D2 of the packet data output from the data holding circuit 22. Are similarly latched and output by the data holding circuit 62.

Conversely, when the control signal ▲ ▼ output from the control unit 93 is at the “L” level, the first word D1 of the packet data output from the data holding circuit 22 is the data holding circuit 32.
And to the data holding circuit 62. This is called a shunt. The first word D1 of the packet data given to the data holding circuit 32 is latched by the data holding circuit 32 and output, and then latched by the data holding circuit 42 and output. Similarly, the first word D1 of the packet data given to the data holding circuit 62 is latched by the data holding circuit 62 and output, and then latched by the data holding circuit 72 and output. Similarly, the second word D2 of the packet data also passes through the data holding circuit 22 and the data holding circuit 32.
And to the data holding circuit 62, and then to the data holding circuit 42 and the data holding circuit 72, respectively.

3 shows a detailed circuit configuration of the transfer control unit 11, FIG. 4 shows a detailed circuit configuration of the transfer control unit 21, and FIG. 5 shows a detailed circuit configuration of the transfer control unit 31.

As shown in FIG. 3, the transfer control unit 11 includes NAND gates G1 and G1.
2, inverter G3, G4, NAND gate G5, and inverter
Including G6 and G7.

The transmission signal C10 is given to the transmission signal input terminal ▲ ▼ from the previous stage (not shown), and the transmission permission signal output terminal ▲
The transmission permission signal AK10 is output from ▼. The transmission signal C20 is output from the transmission signal output terminal ▲ ▼, and the transmission permission signal AK20 is applied to the transmission permission signal input terminal ▲ ▼ from the transfer control unit 21 (FIG. 1) in the next stage.

Next, the operation of the transfer control unit 11 in FIG. 3 will be described with reference to the timing charts in FIGS. 6 and 7.

FIG. 6 is a timing chart for explaining the operation when the next-stage data transmission path is idle. When the next-stage data transmission path is idle, the "H" level transmission permission signal AK20 is given from the next-stage transfer control unit. Therefore, the potential of the transmission permission signal input terminal () is at "H" level. Transmission signal C10 given from the front part
Goes to the “L” level, the transmission signal input terminal ▲
The potential of ▼ changes to "L" level. This allows NAND
The output of the gate G2 becomes "H" level. As a result, the output of the inverter G4 becomes "L" level, and the transmission permission signal AK10 output from the transmission permission signal output terminal () falls to "L" level. On the other hand, the output of the NAND gate G5 becomes "L" level and the output of the inverter G3 becomes "H" level. At this time, the potential of the transmission permission signal input terminal (3) is at "H" level, so the output of the NAND gate G1 falls to "L" level. As a result, the transmission signal C20 output from the transmission signal output terminal () falls to "L" level.

The transfer control unit 21 at the next stage that receives the transmission signal C20 (Fig. 1)
In response to the fall of the transmission signal C20, the transfer control unit 11
Then, the transmission permission signal AK20 applied to the signal is lowered to "L" level.
Therefore, the transmission permission signal input terminal of the transfer control unit 11
The potential of ▼ falls to the “L” level.

On the other hand, in response to the fall of the output of NAND gate G1 to "L" level, the output of NAND gate G5 becomes "H" level and the output of inverter G3 becomes "L" level. Therefore, NAND
The output of the gate G1 rises to the "H" level again. As a result, the transmission signal C20 rises to the "H" level again. Thus, the transmission signal C20 rises to the "H" level after a lapse of a certain period of time after it falls to the "L" level.

On the other hand, the transmission signal C10 given from the preceding stage rises to the “H” level after a lapse of a certain time. Therefore, the output of the NAND gate G2 falls to "L" level and the output of the inverter G4 rises to "H" level. As a result, the transmission permission signal AK10 rises to the "H" level again.

As described above, when the transmission permission signal AK20 given from the transfer control unit of the next stage is in the permission state (“H” level), the front stage unit responds to the fall of the transmission signal C10 given from the front stage unit. Then, the transmission permission signal AK10 applied to the above is in the prohibited state (“L” level), and after a certain period of time, the transmission signal C20 applied to the transfer control unit of the next stage falls to the “L” level.

In response to the fall of the transmission signal C20, the data holding circuit 12
The data applied to the input terminal (FIG. 1) is latched and output from the output terminal. That is, the data transmission path
Data is transmitted from 10 to the data transmission line 20.

Next, FIG. 7 is a timing chart for explaining the operation when the next stage data transmission path is in a clogged state. In this case, the transmission permission signal AK20 given from the transfer control unit at the next stage is at "L" level. When the transmission signal C10 given from the preceding stage falls to "L" level, N
The output of the AND gate G2 becomes "H" level, and the inverter G
The output of 4 falls to "L" level. As a result, the transmission permission signal AK10 output from the transmission permission signal output terminal ▲ ▼ falls to the "L" level. The output of the NAND gate G1 is at "H" level when the transmission permission signal AK20 given from the transfer control unit at the next stage is at "L" level (prohibited state). Therefore, as long as the transmission permission signal AK20 is at the "L" level, the transmission signal C20 provided to the transfer control unit 21 at the next stage holds the "H" level. Therefore, no data is transmitted from the data transmission line 10 to the data transmission line 20 (see FIG. 1).

When the transmission permission signal AK20 provided from the transfer control unit at the next stage rises to "H" level, the output of the NAND gate G1 falls to "L" level. As a result, the transmission signal C20 applied to the transfer control unit at the next stage falls to "L" level. In response to the fall of the transmission signal C20, the data applied to the data holding circuit 12 is latched and output (see FIG. 1).

On the other hand, the transfer control unit at the next stage responds to the fall of the transmission signal C20 given from the transfer control unit 11 and lowers the transmission permission signal AK20 given to the transfer control unit 11 to "L" level after a lapse of a certain time. . Incidentally, in response to the rise of the transmission permission signal AK20 given from the transfer control unit of the next stage, the transmission permission signal AK10 given to the preceding stage rises to "H" level after a lapse of a certain time.

As described above, when the transmission permission signal AK20 given from the transfer control unit of the next stage is in the prohibited state (“L” level), the transmission signal C20 given to the transfer control unit of the next stage falls to the “L” level. Absent. That is, the next-stage data transmission line 20
When is blocked, no data is transmitted from the data transmission line 10 to the data transmission line 20.

The configurations of the transfer control units 41, 51, 61 are the same as those shown in FIG.

FIG. 4 is a circuit diagram showing the configuration of the transfer control unit 21 shown in FIG.

In the transfer control unit 21 of FIG. 4, an AND gate G8 is further provided. One input terminal of the AND gate G8 is connected to the transmission permission signal input terminal ▲ ▼, and the other input terminal is connected to the transmission permission signal input terminal ▲ ▼. The transmission permission signal AK30 is given to the transmission permission signal input terminal () from the transfer control unit 31 (FIG. 1).
Further, the transmission permission signal AK60 is given to the transmission permission signal input terminal (1) from the transfer control unit 61 (FIG. 1). AN
The output terminal of the D gate G8 is connected to one input terminal of the NAND gate G1. A transmission signal C20 is given to the transmission signal input terminal (1) from the transfer control unit 11 (FIG. 1) in the preceding stage, and a transmission permission signal AK20 is output from the transmission permission signal output terminal (1). Also, send signal output terminal ▲ ▼
From which a transmission signal C30 is output. The configuration of the other parts is the same as the configuration of the transfer control unit 11 in FIG.

Regarding the operation of the transfer control unit 21 in FIG. 4, the waveform of the transmission permission signal AK20 in FIGS.
Equivalent to 8 outputs. Therefore, transmission signal C30 falls to "L" level only when both transmission permission signal AK30 and transmission permission signal AK60 are at "H" level.

FIG. 5 is a circuit diagram showing the configuration of the transfer control unit 31 shown in FIG.

In the transfer control unit 31 shown in FIG. 5, an OR gate G9 is further provided. One input terminal of the OR gate G9 is connected to the transmission signal input terminal ▲ ▼, and the other input terminal is connected to the control signal input terminal ▲ ▼. A transmission signal C30 is given to the transmission signal input terminal () from the transfer control unit 21 (FIG. 1). Control signal input terminal ▲
A control signal ▲ ▼ is given to ▼ from the control unit 93 (FIG. 1). The transmission permission signal AK30 is output from the transmission permission signal output terminal ▲ ▼. Also, send signal output terminal ▲
The transmission signal C40 is output from ▼, and the transfer control unit 41 (FIG. 1) of the next stage is connected to the transmission permission signal input terminal ▲ ▼.
The transmission permission signal AK40 is given from. The configuration of the other parts is the same as the configuration of the transfer control unit 11 in FIG.

Regarding the operation of the transfer control unit 31 in FIG. 5, the waveform of the transmission signal C10 in FIGS. 6 and 7 corresponds to the waveform of the output of the OR gate G9. Therefore, control signal ▲ ▼
Is at "L" level, the operation shown in FIGS. 6 and 7 is performed.

As described above, in the above-described embodiment, the packet data provided via the input-side transmission path is autonomously and selectively supplied to the two output-side transmission paths based on the identifier included in the packet data. One or both of them.

In the above embodiment, the data transmission device for transmitting the packet data consisting of two words to either or both of the two output side transmission lines has been described. However, the structure of data to be transmitted is not limited to 2 words, and may be data of 1 word or 3 words or more. If the data consists of one word, the frequency divider 94 shown in FIG. 1 becomes unnecessary. If the data consists of 3 words or more, the frequency divider 94 corresponding to the number of words of the data.
The division ratio of can be set. Therefore, it is possible to easily branch and divert the packet data composed of an arbitrary number of words.

Further, the number of transmission lines on the output side is not limited to two, and may be three or more.

Further, in the above embodiment, the comparison determination logic unit 92 branches or diverts the packet data based on the comparison result between the identifier included in the packet data and the predetermined branch destination designation bit BR. The packet data may be branched or branched based on whether or not the identifier included in the data is detected.

The data transmission device of the above embodiment is applied to, for example, a data flow type information processing device. FIG. 8 is a block diagram showing an example of the configuration of a data flow type information processing apparatus. FIG. 9 is a diagram showing an example of the field structure of a data packet processed by the information processing apparatus.

The configuration and schematic operation of the data flow type information processing apparatus will be described with reference to FIGS. 8 and 9. Destination information is stored in the destination field and instruction information is stored in the command field of the data packet of FIG.
Operand data is stored in the field or data 2 field. The destination field and instruction field correspond to the first word D1 shown in FIG.
The field and the data 2 field correspond to the second word D2 shown in FIG. The m-bit identifier shown in FIG. 2 is included in the destination information.

In FIG. 8, the program storage unit 100 includes a program memory (not shown), and in the program memory, as shown in FIG. 10, a data flow program including a plurality of destination information and a plurality of instruction information is stored. Have been described. The program storage unit 100 reads out the destination information and the instruction information by addressing based on the destination information of the data packet, stores the information in the destination field and the instruction field of the data packet, and outputs the data packet.

The data-to-data detection unit 200 waits for a data packet output from the program storage unit 100. That is,
The pair data detection unit 200 detects two data packets having the same destination information, stores the operand data of one data packet in a predetermined data field of the other data packet, and outputs the other data packet. At this time, the one data packet disappears.

The data packet output from the pair data detector 200 is
It is transmitted to the arithmetic processing unit 300 via the selective diversion unit 800 or is expanded program storage unit 9 via the selective diversion unit 800.
00 and the arithmetic processing unit 300. The arithmetic processing unit 300 decodes the command information of the data packet output from the paired data detection unit 200, performs a predetermined arithmetic processing on those two operand data, and stores the result in the data field of the data packet. Then, the data packet is output to the branching unit 400.

The branching unit 400 outputs the data packet to the internal data buffer 500 or the external data memory 600 based on the destination information of the data packet. The data packets output from the internal data buffer 500 and the external data memory 600 are given to the merging unit 700, and the merging unit 700 gives these data packets to the program storage unit 100 on a first-come-first-served basis. On the other hand, the extended program storage unit 900 gives the data packet given from the selective diversion unit 800 to the program storage unit 100.

In the data flow type information processing apparatus shown in FIG. 8, the data packet includes a program storage unit 100, a pair data detection unit 200, a selective diversion unit 800, an arithmetic processing unit 300, a branching unit 400, an internal data buffer 500 or External data memory
By continuing to rotate in order of 600, confluence part 700 ...
Calculation processing based on the program stored in the program storage unit 100 proceeds. Also, some data packets
Data is transmitted from the paired data detection unit 200 to the extended program storage unit 900 via the selective flow dividing unit 800.

The data transmission apparatus of the above embodiment can be used as the selective flow dividing unit 800 of the data flow type information processing apparatus of FIG.

The data transmission device of the present invention is not limited to the data flow type information processing device, but can be widely used for various information processing devices and other devices that require data transmission.

[Effects of the Invention] As described above, according to the present invention, even when different types of data are given from an anterior part at arbitrary time intervals, each data is output to a desired posterior part of a plurality of posterior parts or It can be transmitted autonomously and selectively to all subsequent stages. Therefore, wiring is provided for each type of data,
It is not necessary to provide a highly functional input / output port. Also,
Data can be received up to the limit of the physical capacity of the transmission path, and the received data can be sequentially transmitted to any or all of a plurality of subsequent stages without a transmission delay time. Therefore, a high-speed and highly reliable data transmission device can be economically realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a data transmission device according to an embodiment of the present invention. FIG. 2 is a diagram showing a structure of packet data transmitted in the data transmission apparatus of FIG. FIG. 3 is a circuit diagram showing a configuration of a transfer control unit included in the data transmission device of FIG. FIG. 4 is a circuit diagram showing the configuration of another transfer control unit included in the data transmission device of FIG. FIG. 5 is a circuit diagram showing the configuration of still another transfer control unit included in the data transmission apparatus of FIG. FIG. 6 is a timing chart for explaining the operation of the transfer control unit when the next stage data transmission path is idle. FIG. 7 is a timing chart for explaining the operation of the transfer control unit when the next stage data transmission path is in a blocked state. FIG. 8 is a block diagram showing the configuration of a data flow type information processing apparatus to which the data transmission apparatus of the present invention is applied. FIG. 9 is a diagram showing a structure of a data packet circulating in each part of the data flow type information processing apparatus of FIG. FIG. 10 is a diagram showing a data flow program stored in the program storage unit of the data flow type information processing measure shown in FIG. FIG. 11 is a diagram showing a configuration of an example of a conventional data transmission device. In the figure, 10, 20, 30, 40, 60 and 70 are data transmission lines and 11, 2
1, 31, 41, 61, 71 are transfer control units, 12, 22, 32, 42, 62, 72 are data holding circuits, 91 is a branch destination designation bit generation unit, 92 is a comparison judgment logic unit, and 93 is a control unit. , 94 is a frequency division part, and 95 is a buffer. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A data transmission device for transmitting data given from a front stage to a plurality of rear stages arranged in parallel, wherein the data is an identifier for designating one of the plurality of rear stages. Discriminating means for discriminating whether or not the data given from the front-stage portion includes an identifier designating any one of the plurality of rear-stage portions, and outputting a signal indicating the discrimination result. A first transmission control unit for transmitting the data given from the front stage unit to one designated by the identifier among the plurality of rear stage units, and the front stage based on the signal from the determination unit. A second transmission control means for enabling or disabling the transmission of the data given by the section to all but the one designated by the identifier of the plurality of subsequent sections. Data transmission equipment.