JPH07212717A - Wide aspect converter - Google Patents

Abstract

PURPOSE:To obtain an aspect converter in which the aspect ratio is converted with a small circuit scale. CONSTITUTION:When a video signal having an aspect ratio of 4:3 is converted into a video signal whose aspect ratio is 16:9 by using a line memory, data are written in the line memory based on a write clock whose frequency is N and the data written in the line memory are read based on a clock signal whose frequency is M except for a blanking period BLK and a side panel period SP. When the frequency M of the read clock is higher than the frequency N of the write clock, aspect ratio is converted by using the line memory whose data length is a multiple of M/N of data for one line of video signals.

Description

Detailed Description of the Invention

[0001]

This invention has an aspect ratio of 4: 3.
To an aspect ratio of 16: 9 or an aspect ratio of 16: 9 to a 4: 3 aspect ratio.

[0002]

2. Description of the Related Art The aspect ratio (hereinafter, referred to as an aspect ratio) of the screen of a current television receiver is 4: 3. Therefore, according to the signal standard (NTSC), an image signal having an aspect ratio of 4: 3 is used. There is. Recently, wide-screen televisions that allow the realization of theatrical movies at home have been released and have been well received.
This wide TV is called a landscape TV, and has an aspect ratio of 16: 9.
The width is about 1.3 times longer than the receiver. recently,
Wide variety of video software such as VTR and LD (laser disk) have begun to appear.

However, even from the total number of television receivers, the current television receivers occupy the majority for the time being,
In broadcast and video software, the aspect ratio is 4: 3. Wide televisions currently on sale have the compatibility features of current televisions.

Aspect conversion in wide television will be described with reference to FIG. As shown in (a), when the image signal reproduced as a circle when displayed on the current television is displayed on the wide screen as it is without any processing, as shown in (b), the side is extended to the side. The aspect conversion function is required in order to reproduce the extension and to eliminate this extension as shown in (c).

FIG. 5 shows the basic configuration of the aspect conversion unit of the current wide television. Aspect conversion is generally performed by dividing it into a Y signal and a baseband C signal (in the case of NTSC, for example, a signal obtained by mixing the I signal and the Q signal).
For example, the operation will be described with respect to the Y signal. The 1H portion of the Y signal having the aspect ratio of 4: 3 is recorded in the line memory Ma via the switch 1 switched as shown in the drawing. While the above signal is being recorded, the signal of 1H before which is already recorded in the line memory Mb is supplied to the selector 3 via the switch 2 switched as shown in the drawing. The output of the selector 3 adds a side panel signal to the video signal and outputs a 16: 9 aspect-converted Y signal. Normal aspect conversion is, for example, a 4: 3 signal at 10 MHz.
It is sufficient to write at the clock WCK and read at the clock RCK which is 1.33 times as high.

When the recording of the Y signal of 1H is completed in the line memory Ma, the switch 1 is switched to the side opposite to the switching position shown by the read / write switching signal WRa to record the next Y signal of 1H. When the signal of 1H before recorded in the line memory Mb is discharged via the switch 2,
The switch 2 is switched to the side opposite to the illustrated switching position by the read / write switching signal WRb, which has an inverted relationship with the read / write switching signal WRa, and the line memory M
The 1H Y signal recorded in a is read by the selector 3
Supply to.

Regarding the C signal, the switches 4 and 5 which are switched as shown by using the read / write switching signals WRa and WRb are switched at the same timing as the switches 1 and 2, and the C signal is transferred to the line memories Mc and Md. A wide aspect conversion operation can be realized by reading, writing, and performing the same process.

When the write clock frequency and the read clock frequency are the same, the line memory is set to FIFO.
If a (First In First Out) type memory is used, one line memory can be realized. The structure of a general FIFO memory is shown in FIG. A timing chart showing the operation is shown in FIG. Hereinafter, description will be given with reference to FIGS. 6 and 7.

In FIG. 6, it is assumed that the FIFO memory 61 has 8-bit input and 8-bit output. FIFO memory 61
Inputs are a write clock WCK, a read clock RCK, a write reset signal WRST, a read reset signal RRST, a write enable signal WCE, and a read enable signal RCE. FIG. 7 shows a timing chart showing the signal. The write clock WCK and the read clock RCK are the same clock. The FIFO memory 61 internally has a counter CTR that determines write and read addresses, and the CTR is cleared during the L period of the WRST signal and the RRST signal, respectively.

In the example of FIG. 7, one line of the image, that is,
A 910 clock FIFO memory is assumed. Further, the write enable signal WCE is a signal which, when H, holds the write internal counter and counts up in the L period. In addition, the read enable signal RC
When E is H, the internal counter for reading is held,
This signal is counted up in the L period. In the example of FIG. 7, when the input is F, WRST becomes L, and the write internal counter is cleared. Therefore, the input signal F is written in the address 0 of the memory. Hereinafter, G and H are written in the first and second addresses, respectively. The input signal is
When I, J, K, the write enable signal WCE is H
become. At this time, the write internal counter is held at 3. Therefore, the input signals I and J are discarded and K is written at the address 3. Read C
TR is cleared to 0 when RRST falls to L. At this time, (3) written in address 0 is output as the output. Further, when the read enable signal RCE becomes H, the read internal CTR holds 2. At that time, the output continues to output the signal (5) which has already been written in the address 2.

As described above, when the write clock WCK and the read clock RCK are the same clock, the FIFO memory 61 can realize a line memory with one line. However, when the frequency of the write clock WCK and the frequency of the read clock RCK are different, it cannot be realized by one line. An example thereof is shown in FIG.

FIG. 8 shows an example of 3/4 compression when outputting a 4: 3 video signal to a 16: 9 wide screen. That is, when the write clock frequency is 1, the read clock frequency is 4/3. First, FIG. 8A will be described. The vertical axis represents the address. The origin is address 0, and the address increases as it goes upward. The horizontal axis represents time. BLK represents a blanking period, and SP represents a side panel section. WRST and RR
The ST signal is a write reset signal or a read reset signal, and a signal in a period falling to L in the BLK period is used. Normally, the horizontal sync signal is used. In FIG. 8A, the solid line represents writing and the dotted line represents reading.

Writing is started from address 0 at 1H, and writing is sequentially performed up to an address of 1H (until BLK at 2H is started) (solid line). 2H, 3H
The same applies to the eyes. During the BLK period, the write enable signal WCE is set to H and is in a hold state in order to save memory. For the read, the data written at 1H is read at 2H. Since reading has a side panel portion, reading is started after that. Since the clock speed for reading is 4/3 times that for writing, the slope is also 4/3 times. Also, like writing,
In this example, the read enable signal RCE is set to H and held during the BLK period and SP period to save memory.

Here, considering the case where the 1-H black circle is read with a 1-H delay, the data ⊚ of the address corresponding to the 2-H black must be the 1-H delay data. However, at the 2H, since Δ is written in the address corresponding to ● first, the data of ◎ becomes Δ and the data delayed by 1H cannot be output.

On the other hand, when the 16: 9 video signal is reversely aspect-converted to a screen having an aspect ratio of 4: 3, the extra portion of the edge is cut in advance to extend the time as shown in FIG. Sometimes. In that case also, the description is omitted because it is the same as the above case.

In this way, a 4: 3 video signal is converted to 16: 9.
Or when a 16: 9 video signal is aspect-converted to 4: 3 and the write clock frequency and the read clock frequency are different, the line memory (FIFO memory) can be switched alternately. Since this cannot be realized with a single line memory, four line memories are used for Y and C compression, which greatly increases the circuit scale and raises the cost.

[0017]

As described above, the conventional aspect converter converts a 4: 3 video signal into a 16: 3 video signal.
If the write clock frequency and the read clock frequency are different when converting aspect ratio to 9 or vice versa, it can be realized by the method of alternately switching the line memories, but using 4 line memories with Y and C compression. Therefore, there is a drawback that the circuit scale is significantly increased.

An object of the present invention is to provide an aspect conversion device capable of performing aspect conversion without increasing the circuit scale.

[0019]

The aspect conversion device of the present invention is an aspect conversion device for converting a video signal having a first aspect ratio into a video signal having a second aspect ratio by using a line memory. A write clock frequency N for writing the data input to the line memory, a read clock frequency M for reading the data of the line memory written at the write clock frequency N, and the read clock frequency M being higher than the write clock frequency N. When it is large, the aspect ratio conversion is performed using the line memory having a length of M / N times the data amount for one line of the video signal. Further, in the aspect conversion device for converting the video signal having the first aspect ratio into the video signal having the second aspect ratio by using the line memory, a write clock frequency O for writing the data input to the line memory is used. , The write clock frequency N
When the read clock frequency P for reading the data of the line memory written by the above and the write clock frequency O is higher than the read clock frequency P, a length of O / P times the data amount of one line of the video signal. And a means for performing aspect conversion using the line memory.

[0020]

According to the above-mentioned means, a 4: 3 video signal is converted into 1
When performing aspect ratio conversion to a video signal of 6: 9, when reading is performed with a clock that is 4/3 times as large as the writing, the writing address is set to a time that is 1/3 longer than the conventional line memory. The relationship between read address and read address is not reversed, and aspect conversion can be realized with one line memory.

[0021]

Embodiments of the present invention will be described in detail below with reference to the drawings. It is explanatory drawing for demonstrating the wide aspect conversion of one Example by the time compression 1 line memory system of this invention using FIG. 1 (a)-
(C) shows the difference in the positions of the side panels of the wide screen. (A) is a side panel,
When it is at the right end, (b) shows the side panels at both ends, and (c) shows the side panel at the left end. This example demonstrates that the system does not fail no matter where the side panel is located.

The operation of this system will be described with reference to FIG. The vertical axis represents the address. The length of 1H is, for example, 1365 (6 fsc (fsc: color multi-carrier) = 136.
In the case of 5 fH), the position representing the length of 1 H on the vertical axis is the address 910. The horizontal axis represents time. BLK represents a blanking period, and SP represents a side panel period. The time from BLK to SP is the time for scanning 1H. WRST, RRST, WCE, RCE
The signals of write reset, read reset, write enable, and read enable are shown, respectively. Basically, the circuit configuration is the same as that shown in FIG. The write reset signal WRST is a signal for resetting a write address with L, and a read reset signal RR
ST is a signal that resets the read address at L. The write enable WCE signal is a signal that holds the write address in the H period and counts up in the L period. The read enable signal RCE is a signal that holds the read address in the H period and counts up in the L period. In writing, the address is held in the BLK period, and in reading, BL is held.
By holding the address in the K period and the side panel period, the total memory amount is reduced.

Now, at 1H, addresses 0 to 1
Data for H is written in the line memory (solid line in FIG. 1). The write address has a length of 1H when the data of 1H has been written. Next, in the 2H period, which is a BLK period, in this period, the write enable signal WCE is set to H and the write address is held, as described above. When the BLK period ends and the write enable signal WCE becomes L, the memory for which the amount is increased by 1/3 is continuously written. That is, the address is 136
Up to 1820 which is 4/3 times of 5. Address is
The write reset signal WRST is set to L to clear the address when it becomes 4/3 times the address for 1H.
Writing is controlled by repeating this operation.
Reading is performed at 4/3 times the write clock speed. That is, 1H of data is read in the section excluding the BLK and SP periods. Similarly to writing, reading also clears the address when the address becomes 4/3 times as large as 1H. As for the initial value, when writing is started from address 0 at the writing of 1H, reading is started from address 0 at the 2H. For example, suppose that ● is written at a certain write address on the 1st H. As for the data, Δ is output at the same read address as the 2Hth write address. Then write ◎ to this address. The same applies to the additional 1/3 address, and the writing of ◇ at the 2H reads the ♦ at the 3H. The same applies to (b) and (c), and a 1H delay can always be realized.

The same applies to the case of the reverse aspect conversion (16: 9 → 4: 3), and its control is shown in FIGS. 2 and 3. In this case as well, the capacity of the normal line memory (in this case,
1H delay can be realized with a line memory that is ⅓ longer than the capacity of the image effective area).

[0025]

As described above, according to the aspect conversion device of the present invention, since the aspect conversion is realized without increasing the memory capacity so much, the chip size when integrated into a circuit can be reduced and the cost is low. Aspect conversion device can be realized.

[Brief description of drawings]

FIG. 1 is an explanatory diagram for explaining a wide aspect conversion of an embodiment according to a time compression 1 line memory system of the present invention.

FIG. 2 is a schematic diagram for explaining a case of another aspect conversion of the present invention.

FIG. 3 is an explanatory diagram for explaining the embodiment of FIG.

FIG. 4 is an explanatory diagram for explaining the principle of conventional wide aspect conversion.

FIG. 5 is a circuit configuration diagram for explaining a basic configuration example of a conventional wide aspect conversion unit.

FIG. 6 is a basic circuit diagram of a conventional FIFO memory.

FIG. 7 is a timing chart showing the operation of FIG.

FIG. 8 is an operation principle diagram when aspect ratio conversion is performed in the 1-line memory by changing the clock frequency.

[Explanation of symbols]

 BLK ... Blanking period SP ......... Side panel period WRST ... Write reset signal RRST ... Read reset signal WCE ... Write enable signal RCE ... Read enable signal

Claims (4)

[Claims] 1. An aspect conversion device for converting a video signal having a first aspect ratio into a video signal having a second aspect ratio using a line memory, wherein a write clock for writing data input to the line memory A frequency N, a read clock frequency M for reading the data of the line memory written at the write clock frequency N, and a data amount for one line of a video signal when the read clock frequency M is higher than the write clock frequency N And a means for performing aspect conversion using the line memory having a length of M / N times. 2. An aspect conversion device for converting a video signal having a first aspect ratio into a video signal having a second aspect ratio using a line memory, wherein a write clock for writing data input to the line memory A frequency O, a read clock frequency P for reading the data of the line memory written at the write clock frequency N, and data for one line of a video signal when the write clock frequency O is higher than the read clock frequency P. A wide aspect conversion device comprising means for performing aspect conversion using the line memory having a length of O / P times the amount. 3. The wide aspect conversion device according to claim 1, wherein the write clock frequency and the read clock frequency are equal frequencies. 4. The wide aspect conversion device according to claim 1, wherein the line memory is a FIFO type memory whose read / write addresses can be controlled independently.