JPH07212247A - Majority decision processing circuit - Google Patents

Abstract

PURPOSE:To perform suitable majority decision processing corresponding to the exactness of input data. CONSTITUTION:Respective comparators 1 and 2 compare respective threshold values L1 and L2 with the count number of a code counter 63 and when the count number exceeds the respective threshold values L1 and L2, '1' is outputted. The output of a selector 3 is switched according to the output of the respective comparators 1 and 2. When the count number of the code counter 63 is less than L1, a bit bl of a completely majority decision processed control code outputted from an output terminal 68 is turned to '0'. When the count value of the code counter 63 exceeds L2, the bit b1 of the completely majority decision processed control code is turned to '1'. When the count value of the code counter 63 is more than L1 but less than L2, the bit b1 of the completely majority decision processed control code is the same as the last majority decided result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a majority decision processing circuit, more specifically, a majority decision for a code repeatedly sent out in digital transmission, for example, a control code in PCM audio broadcasting such as MUSE or NTSC-BS. The present invention relates to a determination processing circuit.

[0002]

2. Description of the Related Art Generally, a code sent repeatedly in digital transmission is protected against a code error by a majority decision process. For example, MUS
In PCM audio broadcasting such as E system and NTSC-BS system, the same control code is included in a plurality of digitally transmitted audio frames. That is, the same control code is repeatedly sent for a plurality of audio frames. Then, the majority decision processing circuit of the audio decoder performs the majority decision processing of the control code.

A conventional majority decision processing circuit will be described below by taking the MUSE method as an example. The MUSE system is described in detail in "MUSE-Hi-Vision transmission system" (published by The Institute of Electronics, Information and Communication Engineers).

FIG. 3 shows a voice frame structure in the MUSE system. This audio frame structure is described from the p.174, line 16 to the p.184, line 6 of the above document. In the MUSE system, A, A as in the NTSC-BS system
Two audio modes B are set, and the audio frame structures are different from each other. For example, 4 for A mode
There are two audio channels, each of which has 8 × 32 data bits, whereas the B mode has only two audio channels and each has 11 data bits.
× 48 bits. However, the number of bits in one frame (=
1350 bits) and the structure from the beginning to 54 bits are the same in both audio modes. That is, a 16-bit frame sync signal and a 22-bit control code are provided at the beginning of one frame. The frame synchronization signal is a 16-bit PN code similar to the NTSC-BS system, and has a bit pattern of (0001001101011110).

On the other hand, the control code is bit-allocated as shown in FIG. Of the 22-bit control code, bits b1 to b13 and b15 to b22 other than bit b14 (master frame identification) only change when switching between A and B modes and are normally fixed. . Therefore, the majority decision processing is performed for each bit b1 to b13, b15 to b22 of the control code in a master frame unit that is a group of 36 frames or a super frame unit that is a group of 18 frames. Protection against code errors is provided. Also,
Among the bits b1 to b6 indicating the audio format, the bit b1 designates whether the mode is A or B.

FIG. 5 shows a block configuration of an audio decoder used in the MUSE system. The audio decoder comprises a synchronization detection processing unit 51, a control code detection processing unit 52, a PCM decoding processing unit 53, a D / A conversion unit 54, an input terminal 55 and an output terminal 56.

The audio bit stream signal separated from the video signal and subjected to the time axis expansion processing and the frame deinterleaving processing is input to the input terminal 55. The audio bit stream signal has the frame structure shown in FIG. 3, but FIG. 3 is a kind of configuration diagram and does not mean a time series signal as it is. For this,
It is described in detail on lines 181, 8 to 184, 6 of the above document.

The audio bit stream signal is input to the input terminal 55.
From each of the processing units 51 to 53. Synchronization detection processing unit 5
In 1, the frame sync signal is detected, and the sync detection pulse is output based on the detected frame sync signal. Control code detection processing unit 52
Then, the majority decision processing is performed on each of the bits b1 to b13 and b15 to b22 of the control code based on the synchronization detection pulse. In the PCM decoding processing unit 53, the PCM decoding processing of the audio bit stream signal is performed based on the control code and the synchronization detection pulse which have undergone the majority decision processing. That is, in the PCM decoding processing unit 53, it is determined whether the mode is the A mode or the B mode according to the bit b1 of the control code, and the decoding process is switched to each bit b2 to b2.
According to 2, the decoding processing of the audio channel and the independent data is performed. The D / A converter 54 D / A converts the PCM-decoded audio bitstream signal to generate an audio analog signal. The audio analog signal is output from the output terminal 56.

The control code detection processing section 52 is provided with a majority decision processing section for carrying out a majority decision processing for each of the bits b1 to b13 and b15 to b22 of the control code. That is, the control code detection processing units 52 are plural (21).
It is constituted by the majority decision processing unit. Further, as described above, the majority decision processing is performed in the master frame (3
It is performed in units of 6 frames or in units of superframes (18 frames). Here, the case of performing the majority decision processing in units of master frames will be described by taking the majority decision processing unit of bit b1 of the control code as an example.

FIG. 6 shows a majority decision processing unit 60 for the bit b1 of the control code. The majority decision processing unit 60 includes a bit counter 61, a frame counter 62, a code counter 63, a comparator 64, a D (data) flip-flop 65, input terminals 66 and 67, and an output terminal 68. In addition, the bit counter 61 and the frame counter 62 have the bits b1 to b13 of the control code,
It is shared by the majority decision processing units b15 to b22.

The synchronization detection pulse from the synchronization detection processing section 51 is sent from the input terminal 66 to the counters 61 and 62.
On the other hand, the audio bit stream signal is sent from the input terminal 67 to the counters 61 and 63.

The frame counter 62 is counted up for each pulse of the sync detection pulse, outputs a carry out at the 36th count, and is reset at the 37th count. That is, the count number of the frame counter 62 indicates which frame of the 36 master frames the audio bitstream signal input to the input terminal 67 corresponds to.

The bit counter 61 is counted up for each bit of the audio bit stream signal and reset by a sync detection pulse. That is, the count number of the bit counter 61 indicates which bit of the 1350 bits of one frame the audio bit stream signal input to the input terminal 67 is.

The sign counter 63 is a bit counter 61.
When the audio bit stream signal when the count number of is 17 is "1", it is counted up (when it is "0", it is not counted up), and it is reset by carry out from the frame counter 62. As shown in FIGS. 3 and 4, since the bit b1 of the control code is the 17th bit signal in one frame, the bit counter 6
The audio bit stream signal when the count number of 1 is 17 is the bit b1 of the control code. That is, the count number of the code counter 63 indicates how many bits “b1” of the control code are “1” in the master frame.

The comparator 64 compares a predetermined threshold value L0 with the count number of the code counter 63, and outputs "1" when the count number exceeds the threshold value L0. The output of the comparator 64 is the D flip-flop 65.
Is input to the input terminal D of. On the other hand, the frame counter 6
The carry-out from 2 is input to the clock terminal C of the D flip-flop 65. Therefore, the D flip-flop 65 latches the input of the input terminal D every time the carry-out is input to the clock terminal C. Then, the D flip-flop 65 continues to output the input of the input terminal D from the output terminal Q as the bit b1 of the control code that has undergone the majority decision processing until the next carry-out is input.

Usually, the threshold value L0 is set to 1/2 of the number of master frames, that is, 18. Therefore, when the count number of the code counter 63 is 18 or less (that is, when the number of frames in which the bit b1 of the control code is "1" in the master frame is 18 or less), the bit b1 of the control code subjected to the majority decision processing is " It becomes "0".
On the other hand, when the count number of the code counter 63 is 19 or more (that is, when the number of frames in which the bit b1 of the control code is "1" in the master frame is 19 or more), the bit b1 of the control code that has undergone the majority decision processing is " 1 ”.
That is, if 18 or less of 36 bits b1 of the control code in the master frame are "1", the correct value of the bit b1 of the control code (the value of the actually transmitted code) is "0". If 19 or more are “1”, it is determined that the correct value of the bit b1 of the control code is “1”.

The majority decision processing unit 6 configured as described above
Similar to 0, other bits b2 to b13, b1 of the control code
Also in the majority decision processing units 5 to b22, the code counter 63, the comparator 64, and the D flip-flop 6
A circuit corresponding to 5 is provided. Then, the majority decision processing is similarly performed for each of the bits b2 to b13 and b15 to b22 of the control code.

By the way, when performing the majority decision processing in units of superframes, the frame counter 62 is set to 18
Carry out is output at the count and reset at the 19th count. In this case, the count number of the frame counter 62 indicates which frame of the 18 superframes the audio bitstream signal input to the input terminal 67 corresponds to. The other configuration is the same as the majority decision processing in master frame units described above.

[0019]

When a code error occurs over several frames due to the influence of noise during the transmission of the PCM audio signal or the reduction of the received electric field strength, the result of the majority decision processing (D flip-flop). Output of the packet 65) may be different from the code actually transmitted. For example, the number of frames for which the majority decision processing is performed by the influence of random noise (36 in the case of the majority decision processing for each master frame).
When the majority decision processing in units of frames or superframes is received for 18 frames or more), the count number of the code counter 63 is likely to be near the threshold L0. In this case, an error occurs in the majority decision result depending on whether the count number of the code counter 63 is slightly larger or smaller than the threshold value L0.

As described above, once an error occurs in the control code which is the majority decision result, the PCM decoding processing unit 53 performs the PCM decoding process with the erroneous control code until the next majority decision result is output. As a result, the sound reproduction state is adversely affected. For example, when the bit b1 of the control code is incorrect, the PCM decoding processing unit 53 incorrectly determines whether the mode is A or B, and thus a large amount of noise is mixed in the reproduced signal. Similarly, the other bits b2 to b13 and b15 to b2 of the control code
Even if 2 is mistaken, some adverse effects such as noise occur in the reproduced signal.

The present invention has been made in order to solve the above problems, and an object thereof is to make a majority decision capable of performing an appropriate majority decision process in accordance with the accuracy of a binary code for making a majority decision. It is to provide a determination processing circuit.

[0022]

According to a first aspect of the present invention, when a majority decision is made for a predetermined number of binary codes, the number of binary codes having an arbitrary value is within a predetermined range. In the case of (1), the gist is to use the previous majority decision result as the current majority decision result.

According to a second aspect of the present invention, with respect to a predetermined number of binary codes, a counting means for counting binary codes having an arbitrary value, a count value of the counting means and two predetermined threshold values are provided. Comparing means for comparing, and based on the comparison result of the comparing means, when the count value of the counting means is within two thresholds, a selecting output means for outputting the previous majority decision result as the current majority decision result. What is prepared is the gist.

According to a third aspect of the present invention, with respect to a predetermined number of binary codes, a counting means for counting binary codes having an arbitrary value, a count value of the counting means and two predetermined threshold values are provided. Based on the comparison result of the comparison means for comparing and the comparison result of the comparison means and the storage output means for continuously storing and outputting the previous majority judgment result until the result of the majority decision of this time, the count value of the counting means When is within two thresholds, the gist is to provide a selecting means for storing the previous majority decision result stored in the memory output means as the current majority decision result in the memory output means.

The invention according to claim 4 is, in the invention according to claim 2 or claim 3, characterized in that the comparing means comprises a window comparator composed of two comparators.

According to a fifth aspect of the invention, in the invention of the second or third aspect, the counting means is an MU.
The gist is to count the number of "1" or "0" of an arbitrary bit of a control code in PCM audio broadcasting by the SE system or the NTSC-BS system.

According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the counting means counts each frame in a master frame unit or a superframe unit and each bit in one frame. The gist is that it comprises a bit counter for counting and a code counter for counting the number of "1" or "0" of any bit of the control code based on the count of the frame counter and the bit counter.

[0028]

In the invention described in any one of claims 1 to 3, when the accuracy of the binary code for making the majority decision is impaired due to some influence, the binary code of any value is used. There is a high possibility that the number will be around ½ of the predetermined number.

Therefore, in the invention described in claim 1, when the accuracy of the binary code may be impaired by appropriately setting the predetermined range, the accuracy of the binary code may be reduced. Appropriate majority decision processing can be performed according to the degree.

Further, in the invention described in claim 2 or claim 3, when the accuracy of the binary code may be impaired by appropriately setting the two predetermined threshold values, the binary code Appropriate majority decision processing can be performed according to the accuracy of the code.

According to the third aspect of the present invention, the storage output means can reliably store and output the previous majority decision result until the present majority decision result is obtained.

According to the fourth aspect of the present invention, the comparison means can be easily and easily realized by using the window comparator. According to the invention described in claim 5, it is possible to more appropriately determine the majority decision of the control code in the PCM audio broadcasting by the MUSE system or the NTSC-BS system. As a result, a good audio reproduction state can be maintained.

According to the sixth aspect of the invention, the counting means can be easily realized with a simple structure.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In this embodiment, the same components as those in the conventional example shown in FIGS. 3 to 6 are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 1 shows a majority decision processing unit of this embodiment corresponding to FIG. 6 of the conventional example. In other words, this embodiment uses the MU
This is a majority decision processing unit of the bit b1 of the control code in the case of performing the majority decision process in master frame units in the SE decoder. The present example differs from the conventional example only in the following points.

The comparator 64 is replaced by a window comparator consisting of two comparators 1 and 2. Each of the comparators 1 and 2 compares the respective predetermined threshold values L1 and L2 with the count number of the code counter 63, and outputs "1" when the count number exceeds the threshold values L1 and L2. The relationship between the thresholds L1 and L2 is as shown in equation (1).

0 <L1 <L2 <N (1) Note that N is the number of frames for which the majority decision processing is performed. In this embodiment, the majority decision processing is performed for each master frame, so N = 36. The threshold value L1 is 1/3 of N.
(L1 = 12), the threshold L2 is 2/3 of N (L2 = 24)
Stipulated in.

A selector 3 is provided between each of the comparators 1 and 2 and the D flip-flop 65. The output of the selector 3, as shown in FIG.
2 output (that is, the count number of the code counter 63)
It is switched according to.

In the present embodiment thus constructed, the number of counts of the code counter 63 is 11 or less (threshold L
(Less than 1), the bit b1 of the control code output from the output terminal 68 and having undergone the majority decision processing is "0". Further, when the count number of the code counter 63 is 25 or more (when it exceeds the threshold value L2), the bit b1 of the control code which is output from the output terminal 68 and which has undergone the majority decision processing is "1". When the count number of the code counter 63 is 12 or more and 24 or less (L1 or more and L2 or less), the output terminal 68
Bit b of the control code that has been processed by the majority decision output from
1 becomes the same as the previous majority decision result (that is, the previous value is held).

As described above, when the influence of random noise is received for 36 frames or more, the code counter 6
There is a high possibility that the count number of 3 will be near 1/2 (= 18) of N. In such a case, in the present embodiment, the previous majority decision result is output as the present result. In other words, when the count number of the code counter 63 is 12 or more and 24 or less and around 18, it is possible that the majority decision result of this time is erroneous due to some influence (noise during transmission of the PCM audio signal, reduction of received electric field strength, etc.) As a result, the previous majority decision result is retained as it is. Therefore, it is possible to reduce noise generation due to a temporary control code determination error, and it is possible to maintain a good audio reproduction state.

Although only the majority decision processing unit for the bit b1 of the control code has been shown above, the other bits b2 to b13, b1.
The same processing is performed for the majority decision processing units 5 to b22 with the same configuration.

The above embodiment may be modified as follows. 1) When performing the majority decision processing in units of superframes, the frame counter 62 outputs a carry-out at the 18th count and is reset at the 19th count. In this case, the count number of the frame counter 62 indicates which frame of the 18 superframes the audio bitstream signal input to the input terminal 67 corresponds to.

2) Each bit b1 to b13, b of the control code
Rather than providing a majority decision processing unit for each of 15 to b22, each bit is serially processed by one majority decision processing unit. In this case, the circuit scale can be reduced.

3) Thresholds L1 and L2 are set appropriately. For example, when the influence of noise during the transmission of the PCM audio signal or the decrease of the received electric field strength is small, the threshold L1 is set large and the threshold L2 is set small (for example, L1 = 15, L2 =
20). On the other hand, when those influences are large, the threshold L1 is set small and the threshold L2 is set large (for example, L1
= 5, L2 = 30). The thresholds L1 and L2 may be set by the user himself or may be set by the manufacturer at the time of shipping. Further, the noise detection circuit and the received electric field strength detection circuit may be provided so that the optimum threshold values L1 and L2 are automatically set according to the detection results.

4) The same operation is performed in the NTSC-BS system. In this case, since the voice frame structure of the NTSC-BS system and the bit allocation of the control code are different from those of the MUSE system, the counters 61 to 6 are adjusted accordingly.
It is necessary to change the setting of 3.

5) It is applied not only to the majority decision processing circuit for control codes in PCM audio broadcasting such as the MUSE system and NTSC-BS system, but also to the majority decision processing circuit for appropriate codes.

[0047]

As described above in detail, according to the present invention, it is possible to provide a majority decision processing circuit capable of performing appropriate majority decision processing according to the accuracy of a binary code for making a majority decision. It has an excellent effect that it can be done.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment embodying the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of one embodiment.

FIG. 3 is a structural diagram showing a voice frame structure in the MUSE method.

FIG. 4 is a structural diagram showing bit allocation of control codes in the MUSE method.

FIG. 5 is a circuit diagram of an audio decoder used in the MUSE method.

FIG. 6 is a circuit diagram showing a conventional majority decision processing unit.

[Explanation of symbols]

1, 2 Comparator 3 Selector as selection means and selection output means 65 D flip-flop as storage output means and selection output means 61 bit counter 62 frame counter 63 code counter L1, L2 threshold value

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Claims (6)

[Claims] 1. When a majority decision is made for a predetermined number of binary codes, if the number of binary codes that take an arbitrary value is within a predetermined range, the previous majority decision result is given this time. A majority decision processing circuit, which is the majority decision result. 2. A counting means (61 to 63) for counting a binary code having an arbitrary value for a predetermined number of binary codes, a count value of the counting means and two predetermined thresholds (L1, L).
2) and comparing means (1, 2) for comparing with each other, and based on the comparison result of the comparing means, when the count value of the counting means is within two thresholds, the previous majority decision result is the majority decision of this time. A majority decision processing circuit comprising a selection output means (3, 65) for outputting as a result. 3. A counting means (61 to 63) for counting a binary code having an arbitrary value for a predetermined number of binary codes, a count value of the counting means and two predetermined threshold values (L1, L).
Comparing means (1, 2) for comparing with 2), and storage output means (65) for storing and outputting the previous majority decision result until the present majority decision result is output.
And based on the comparison result of the comparison means, when the count value of the counting means is within two thresholds, the previous majority decision result stored in the storage output means is stored as the current majority decision result. A majority decision processing circuit, comprising: a selection means (3) to be stored in the output means. 4. The majority decision processing circuit according to claim 2 or 3, wherein the comparison means is constituted by a window comparator composed of two comparators (1, 2). circuit. 5. The majority decision processing circuit according to claim 2 or 3, wherein the counting means (61 to 63).
Is a PC based on MUSE or NTSC-BS
A majority decision processing circuit which counts the number of "1" or "0" of an arbitrary bit of a control code in M audio broadcasting. 6. The majority decision processing circuit according to claim 5, wherein the counting means (61 to 63) counts each frame in master frame units or superframe units, and one frame. A bit counter (61) for counting each bit in
A majority decision processing circuit comprising a frame counter and a code counter (63) for counting the number of "1" or "0" of an arbitrary bit of a control code based on the count of a frame counter.