JPH0721082A - Method for programming of memory element which is pin-compatible with nonprogrammable memory and which is usable as nonprogrammable memory - Google Patents

Abstract

PURPOSE: To provide compatibility between a programmable buffer chip and an unprogrammable buffer chip by delaying the impression of a reset cancel signal and inputting program data during that delay. CONSTITUTION: When a reset inhibit signal-RS is turned to low level, series of reset operations are executed inside the programmable buffer chip. When a term TRS ends, at an ordinary basic buffer chip, the reset cancel signal is impressed and a reset mode is finished. However, the impression of the reset cancel signal is delayed just for an extended term TEXT over the term TRS in order to input program information to the programmable buffer chip. The program information is inputted to the programmable buffer chip during this delayed term. Namely, by turning a read inhibit signal-W to low level and putting data onto a data line DATA, data are read in.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to programmable buffers made on a single integrated circuit chip and programming methods for such buffers.

[0002]

BACKGROUND OF THE INVENTION A buffer is a data storage element commonly used for data transfer in which a data element can be written to and read from another source. A buffer built on a single chip, whether programmable or not, is called a buffer chip. When such buffers communicate with the external environment, they do so through the I / O (input / output) pins of the buffer chip in which they are provided. Generally, a buffer chip contains buffer status pins assigned to monitor and indicate buffer status, such as full, empty, half full, and so on. Programmable means that the particular buffer state monitored and indicated to the external environment at some buffer status pin can be changed by external selection. The procedure for entering program information is called programming. The buffer chip is programmed by inputting program information into the buffer chip. Once programmable, the user of the buffer chip can change the monitored buffer status state depending on the particular requirements of the application environment in which the buffer chip is configured. Without the programming capability, the monitored buffer status condition cannot be changed, which limits the usefulness of the buffer chip.

Programmable buffer chips are known in the prior art. The programming possibilities themselves are not the subject of the present invention. Rather, the present invention is directed to a particular programming method that eliminates the significant drawbacks common to all programmable buffers in the prior art, as well as buffer chips programmable by such method. One of the serious drawbacks of the programmable buffer chip of the prior art is that it has a compatibility problem, that is, it is inferior to a non-programmable buffer chip.
compatible).

Compatibility in the context of the present invention means interchangeability. One programmable buffer chip is compatible with a non-programmable buffer chip is
Remove this non-programmable buffer chip from its position in the original circuit, without causing malfunction in the original circuit,
This is the case when the pins match the programmable buffer chip and can be replaced. The original circuit, if not replaced with a programmable buffer chip, will continue to operate as if it were operating with the original non-programmable buffer chip. Compatibility in this sense is backwards compatibility, as more sophisticated buffer chips that have programming capabilities maintain compatibility with basic buffer chips that do not have programming capabilities. However, compatibility has never been achieved. Prior art programmable buffer chips that are compatible with non-programmable basic buffer chips with the same number of functional I / O pins are not yet known.

[0005]

In the prior art, the use of dedicated programming pins is one reason why compatibility has not been achieved in the past. A dedicated programming pin is one in which the signal applied to it is only relevant for programming the buffer chip. Having such a dedicated programming pin on a programmable buffer chip can cause many failures when replacing the programmable buffer chip with the original non-programmable buffer chip. There may be situations where the pin counts do not match or the original system, which was not designed to work with the programmable buffer chip, signals a dedicated programming pin. In either case, the system cannot get a proper response from the replaced buffer chip.

According to one aspect of the present invention, there is provided a method of inputting program information to a programmable buffer chip, the programmable buffer chip and a non-programmable basic buffer chip having the same number of I / O pins. Achieve compatibility between. The present invention is
It creates a spoofed time period as an extended reset period, which is added at the end of the actual reset period. During this camouflage time period, program information is input to the buffer chip, thus programming the buffer chip. The program information selects the buffer status condition to monitor. The monitored condition is indicated by at least one status pin.

According to another aspect of the present invention, there is provided a programmable buffer chip to which the programming method of the present invention is applied. The programmable buffer chip receives program information during a time period, which is disguised as an extension of the reset period, added at the end of the normal reset period.

[0008]

SUMMARY OF THE INVENTION The present invention is based on the existence of a non-programmable basic buffer chip reset mechanism. The basic buffer chip is
Responsive to the reset signal, a reset mode is entered for a predetermined minimum duration, during which a reset operation is performed to return the buffer chip to a predetermined initial state (eg, setting a flag indicating that the buffer is empty). I am trying. After this period, the basic buffer chip exits reset mode, enters normal non-reset buffer operation, receives, stores, and outputs data elements in response to the reset release signal. The period provided for reset must be sufficient to complete the reset operation.

According to the present invention, when the reset signal is generated, the programmable buffer chip enters the reset mode for a sufficient predetermined duration to perform the reset operation. The reset release signal is not applied to the programmable buffer chip for a longer time period following the reset period. At the end of this longer time period, the reset release signal is applied. Thus, the longer time period is added at the end of the actual reset period and appears to disguise the extension of the reset period. Program information is input to the buffer chip during this camouflage time period, and the programmable buffer is programmed during this period.

The above-described programming method requires performing a reset operation every time the buffer chip is programmed, since the programming is performed during the camouflage extension period of the reset period. According to another embodiment of the invention, the actual reset operation is prohibited during the normal reset period preceding the impersonation period for programming,
The reset operation is not started every time the programmable buffer chip is about to be programmed.

According to the present invention, when the programmable buffer chip is replaced with a non-programmable basic buffer chip in the original system designed to operate with the non-programmable basic buffer chip,
Pin-to-pin compatibility between a programmable buffer chip and a non-programmable basic buffer chip is achieved. The original system does not operate to add an extended replacement period at the end of the normal reset period unless there is a malfunction, and the program information is stored in the buffer chip during such additional time period disguised as an extension of the reset period. Since no attempt is made to input, the above-mentioned problem due to replacement cannot occur.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1A shows a non-programmable basic buffer chip 2. It has multiple I / O pins, but only a few are identified in FIG. 1A. P1 is
A read control pin for initiating a read operation, when a Read Bar signal (ReadBar) is applied to P1 and it goes low, a buffer read is initiated. P2 is a write control pin for starting a write operation, and is write-protected (Write B
ar) signal is applied to P2 and when it goes low, a write operation is initiated. P3 is a reset control pin for starting a series of reset operations in the buffer chip 2, and a reset inhibit (Reset Bar) signal is applied to P3.

The reset inhibit signal has two functional roles. When the reset inhibit signal becomes low level, if both P1 and P2 are high level at that time, it acts as a reset signal for putting the buffer chip into the reset mode and performing the reset operation. The reset period starts when the reset signal is applied. When the reset inhibit signal changes to high level, reset release (Res
et Release) signal to terminate the reset mode and thus bring the buffer chip out of the reset mode to perform normal non-reset buffer operation.

P4 to P12 are data input pins for a 9-bit data word, P18 to P26.
Up to and is the data output pin for a 9-bit data word. P14 is a control signal pin and has no functional meaning during the time when the basic buffer is in the reset mode and is performing the reset operation. Therefore, it can be any of a number of control pins on the basic buffer chip. P15, P16, and P17 are buffer status pins, which monitor a certain buffer status state by the signal level shown here. P15 monitors the buffer full condition by generating a predetermined signal level when the buffer is full. P16 monitors the half full condition of the buffer by generating a predetermined signal level when more than half the buffer position has been written but not yet read. P17 generates a predetermined signal level when the buffer is empty,
Monitor the buffer empty status. In the basic buffer chip 2, the buffer status states of full, half full, and empty are fixed and cannot be changed. Therefore, the basic buffer chip 2 is not programmable.

The illustrated basic buffer chip performs data transfer in a first-in-first-out procedure. The data elements are
They are read from the buffers in the buffer chip and output from the buffer chip in the same order as they were input to and written to the buffer chip. A buffer is considered empty when no data elements have been written to the buffer or when all elements written to the buffer have been read. Also, a buffer is considered full when it is filled with data elements and they have not been read at all. A buffer is also considered to be half full when more than half of the buffer locations contain data elements written to the buffer but not yet read.

A programmable buffer chip 4 is shown in FIG. 1B. This has the same number of I / O pins as the basic buffer chip 2 in the same physical arrangement.
Each pin of the basic buffer chip has a pin corresponding to this programmable buffer chip. Similar to the basic buffer chip, the programmable buffer chip also has a read control pin P1 and a write control pin P.
2, reset control pin P3, data input pins P4 to P12, buffer status pins P15 to P17
(The monitored state can be changed by programming), data output pins P18 to P26, and data direction pin (Data Direction Pin).
It has P14.

The data direction pin P14 of the programmable buffer chip is used to realize a function of selectively inputting program information to the chip from one of two sets of I / O pins. One level signal applied to pin P14 indicates that the data pins P4 to P12 are used to input program information, and the other level signal applied to pin 14 is normally Indicates that the data output pins P18 to P26 are used for inputting program information.
Since the corresponding pin P14 in the basic buffer chip described above has no functional meaning during the reset mode, P14 is used for programming by the programmable buffer chip so that this buffer chip is in the reset mode. If programmed in, compatibility with basic buffer chips can be achieved. In another embodiment, where the pin identity used to enter program information is fixed, the data direction pin P14 need not be provided for pin selection purposes. Rather, the data direction pin P14 may have the same function as the corresponding pin of the basic buffer chip.

In programmable buffer chip 4, the just-before-full state (defined when the buffer is full, except for a certain number of positions specified by an offset value entered into the buffer chip by the user as part of the program information). almost-full condition
on) can be monitored by P15. Also,
The last-empty condition defined when the buffer is empty, except for a certain number of positions specified by an offset value entered by the user into the buffer chip as part of the program information.
on) can be monitored by P17. Furthermore,
One instruction in the program information input to the buffer chip can cause P16 to monitor either the half-full state of the buffer, or the full or empty state of the buffer. When having P16 monitor a buffer full or buffer empty condition, to determine which state is indicated by P16, check the status of the pre-empty condition indicated by P15 or the pre-empty condition indicated by P17. Good. If the buffer is almost full, the positive indication at P16 will be interpreted by the outside world as full. Also, if the buffer is nearly empty, the positive indication at P16 will be interpreted by the outside world as empty. Simple gating logic is used to make this interpretation. In addition, the program information is monitored by pins P15, P16 to monitor the same conditions as those monitored by P15, P16 and P17 of the basic buffer chip.
And can also include instructions such as setting P17.

Although the physical pin arrangement is the same between the basic buffer chip 2 and the programmable buffer chip 4, the specific arrangement shown in FIGS. 1A and 1B is merely for convenience of illustration. belongs to. In order to achieve compatibility that allows a programmable buffer chip to replace a basic buffer chip in a system that is not designed for programming, only the programming method, that is, the pins that already exist on the basic buffer chip, is used. What is needed is a method for entering program information into the programmable buffer chip that is utilized.

The program information contemplated by the preferred embodiment of the present invention is in the form of two 9-bit program instruction words. In the first command word, 7 for specifying the offset (first offset data) for the state immediately before full
Bits are allocated. The increment of each offset is
Corresponds to a 2-byte offset in the buffer. Therefore, if the first offset in this instruction word corresponds to a condition where the buffer is full except for 2 bytes of data, the pre-fill condition covers a range containing 127x2 bytes from the actual full condition. To do. Similarly, the second
7 bits for designating an offset (second offset data) with respect to the buffer empty state are allocated to the instruction word. Each offset increment corresponds to a 2-byte offset in the buffer. Thus, if the first offset in this instruction word corresponds to a state in which the buffer is empty except for 2 bytes of data, the just-before-empty state covers a range containing 127x2 bytes from the actual empty state. Depending on the size of the buffer itself, it may be desirable to have more or less offset bits in the instruction word. For a 1Kx9-bit FIFO buffer, the proper choice is to have 7 bits for the offset bit in each instruction word. 512x9 bit FI
In the FO buffer, the offset bit in each instruction word is 6
Making a bit is a good choice. Also, how many bytes correspond to each offset increment depends on the application environment and may change in different embodiments.

FIG. 2 shows the first and second program command words. The first program instruction word is stored in the full flag program register, while the second program instruction word is stored in the empty flag program register incorporated in programmable buffer chip 4 of FIG. 1B. These program registers are used to receive and store program information. Since the basic buffer chip 2 is not programmable, it does not include any program register for storing program information. Both program registers are
It stores a program instruction word of 9 bits in length and 9 bits each. The full flag program register operates to store a first instruction word including offset information (first offset data) for the immediately preceding full state, and the empty flag program register has a second instruction including the offset information for the immediately previous empty state. It operates to store the command word of.

Bit 7 of the first and second program instruction words (8th bit counting from bit zero) is reserved for later offset extension. Until then, they may not be used, so dummy bits may be included.

Bit 8 of the first program instruction word (the ninth bit counting from bit zero) is hereinafter referred to as a program instruction bit. Bit 8 determines whether the programmable buffer 4 is initialized to monitor one or more of the same conditions monitored by the basic buffer chip 2. In one embodiment, when this program indication bit is set low, the programmable buffer responds, as in the case of a basic buffer chip, using P15 to indicate a buffer full condition and P16 to indicate a buffer full condition. Is intended to indicate a half-full condition, and P17 is used to indicate a buffer empty condition. When the program instruction bit is set to a high level, the programmable buffer chip uses P15 to indicate the state just before full according to the first offset data in the first instruction word of the program information, and uses P17. , Is intended to indicate the immediately preceding empty state according to the second offset data in the second instruction word of the program information, and to indicate both the full and empty states using P16. When indicating both the full state and the empty state using P16, the identification of the indicated state is P15.
, And P17. If the just before full instruction is given at P15, the positive instruction at P16 will represent a full condition. Just before the sky is P
If given at 17, the affirmative indication at P16 will represent an empty condition. Thus, when the program indication bit is set high, four conditions are monitored: just before full, just before empty, full and empty. The full and empty states are indicated by the same buffer status pin.

In another embodiment, the program indication bit is P16 if P16 is a basic buffer chip.
It only determines whether or not it functions similarly. P15
Indicates the state immediately before full or is initialized to indicate the full state like P15 of the basic buffer chip depends on the value of the first offset data. Whether P17 indicates the state immediately before empty or whether it is initialized to indicate the empty state like P17 of the basic buffer chip depends on the value of the second offset data. If the first offset data is zero, the programmable buffer chip responds by acting to indicate that P15 is full (as in the basic buffer chip). If the first offset data is non-zero, the programmable buffer chip automatically responds to this by using the offset specified by the first offset data, P1
5 acts to indicate the state just before full. If the second offset data in the second program word is zero,
In response, the programmable buffer chip responds to the P1
7 acts to indicate an empty state (as in the basic buffer chip). If the second offset data is non-zero, the programmable buffer chip automatically responds to this by using the offset specified by P1 second offset data to cause P17 to indicate an immediate empty state. To do. In the present embodiment, of course, the programmable buffer chip is provided with a logic circuit that checks the value of each offset data, and the basic buffer chip is combined with the combination of the program instruction bit, the first offset data and the second offset data. Together indicates whether the buffer status condition monitored by the same or different from that monitored by the corresponding pin of the basic buffer chip.

Bit 8 of the second program instruction word (the 9th bit counting from bit zero) inhibits the reset operation if the programmable buffer chip is legally in the reset mode if not disabled next time. Determine whether or not. This is a reset prohibition instruction bit. The importance of this mechanism will be clear in view of the subsequent discussions herein. This gives the option of not resetting the buffer each time the programmable buffer chip is programmed. In another embodiment where this option is not given, the reset inhibit indicator bit need not be included in the program information.

In order to gain a proper understanding of the programming method according to the invention, the reset mechanism of the basic buffer chip 2 will first be described.

Resetting means initializing the buffer to a predetermined state, ready to receive a new set of data elements. For example, if the buffer is half full after receiving the first group of data elements,
Resetting restores the buffer to its initial state, as if it had no data elements written to it and is now empty. After reset, the buffer is ready to receive a new set of data elements. If pointers are used in the buffer to point to certain buffer positions with respect to the current state of the buffer, then these pointers will be initialized to the state with respect to the initial buffer state.

In basic buffer chip 2, if both the read inhibit and write inhibit signals are high, the buffer chip is set to the reset mode when the reset signal is applied to pin P3, and the buffer chip is set to a series. Start the reset operation. After a sufficient period of time to complete the reset operation, the reset release signal is applied to pin P3 to bring the buffer chip out of reset mode and start the next non-reset buffer operation, thereby resetting the reset mode. To finish.

The programming method according to the present invention is predicated on the operation of the basic buffer chip as it enters and exits the reset mode. Therefore, the programmable buffer chip that intends to use the programming method according to the present invention must have the same mechanism for entering and exiting the reset mode if backward compatibility with the basic buffer chip is to be achieved.

The programming method according to the invention adds an extension time period, which is disguised as an extension of the reset period, at the end of the reset period. During this impersonation time period, program information has been input to the programmable buffer chip and the reset operation has already completed, but the chip is in the idle state as if it was still reset. By thus inputting the program information, the programmable buffer chip can be made compatible with the corresponding non-programmable basic buffer chip. This is because when the programmable buffer chip is placed in the environment designed for the basic buffer chip, the circuit in that environment generates a spoofed reset extension period and adds it to the normal reset period, so that the program information is provided during that period. This is because you will not try to enter it. Without the impersonation reset extension period for programming, the programmable buffer chip operates as if it were not programmable.

FIG. 3 shows two program instruction word formats.
Program information to programmable buffer chip 4
Occurs in a series of steps taken to enter
It shows the operation timing. First of all,
Set prohibition signal, read prohibition signal, and write prohibition
The signals are all high. Reset disable signal is low
When it comes to the default, like the case of the basic buffer chip 2
In addition, a series of reset operations are
It will be started inside P4. The predetermined period of the shortest duration is
It is necessary to perform a series of reset operations. this period
Is T in FIG._rsAs shown. Usually basic
In the buffer chip, the period T_rsReset at the end of
Release signal (reset prohibition signal converted to high level)
Applied to terminal P3 to end the reset mode. Shi
Programmable buffer chip for program information
4, the reset release signal is applied for a period of time.
T _rsBeyond the extension period T_extJust delayed. This period T
_extIs a forged extended reset period, during which
Input program information to programmable buffer chip
To do. As shown in FIG. 3, the period T_extIs normal
Reset period T_rsIs added at the end of. Period T
_extDuring this period, the read inhibit signal initially goes low,
Check that the program information is input.
Notify the Tiffa Chip 4. Next, the read inhibit signal
Converted to a higher level. In another embodiment, this purpose is
Any other signal may be used for this purpose. I need only one
Is the period T _rsIs followed by a signal
The first and second program command words reach the chip
It is to inform that. After this, the first and second
Program command word is programmable buffer chip 4
Are input in order.

For each command word, the write inhibit signal is
Before the command word is input, the level is initially low.
The write inhibit signal remains low for a period of time and transitions to its initial state in preparation for going low again. In this way, the write inhibit signal is sent twice,
That is, it is switched once each time each program command is input. As previously mentioned, the first program instruction word contains offset information regarding the buffer's near full state and is stored in the full buffer flag register. The second program command word includes offset information relating to the immediately preceding empty state of the buffer and is stored in the empty buffer flag register. In another embodiment, the sets of first and second program instruction words may be opposite.

In the embodiment with the data direction pin P14, the direction signal DIR is changed to the data direction pin P14 immediately before the write inhibit signal is first switched during the _Text period.
Applied to. In this way, the state of the DIR signal is
Programmable buffer chip 4, P4 or P1
2 or either set of pins P18 to P26
Whether or not to transmit the program command word to be input to the programmable buffer chip 4 is notified. In one embodiment, pins P4-P12 are selected when in the low state,
In the high level state, the pins P18 to P26 are selected. This selection may be the opposite in other embodiments.

As described above, the program information is T _ext.
It is input to the programmable buffer chip 4 during the period, that is, during the camouflage extension of the normal reset period. The input process in the particular embodiment shown here is to bring the read inhibit signal low, apply the direction signal DIR to pin P14, and once to enter one program command word, and The second includes switching the write inhibit signal once again to input the 2 program command word (the command word is input through the I / O pin of the set selected by the signal of the pin P14).

According to the above-described embodiment, every time the programmable buffer chip is programmed, the reset operation is also performed during the period T _rs preceding the period T _ext . This may not be desirable. In another embodiment, the programmable buffer chip is performed next time if not aborted,
An instruction as to whether or not to start the reset operation may be included in the program information. Bit 8 of the second program instruction word (the 9th bit counting from bit zero) is used for this purpose. One state of this bit, that is the next T _rs period should not perform a reset operation, shown in the programmable buffer chip 4, the other state of this bit, to be normally stopped in the next T _rs period It indicates to the programmable buffer chip 4 that it should be reset, as done.

The above-mentioned basic buffer chip is provided with one reset pin, in which both a reset signal (reset prohibition signal transiting to low level) and a reset release signal (reset prohibition signal converting to high level) are provided. However, some other basic buffer chips have different configurations. For basic buffer chips that have separate pins for receiving reset and release reset signals, compatible programmable buffer chips must have corresponding separate pins.

FIG. 4A illustrates an assertion of a near full signal (flag) AFF according to a preferred embodiment of the present invention.
region and deassertion (deassert)
4B similarly shows the assertion and deassertion of the immediately preceding empty signal (flag) AEF. For convenience of illustration, a 2-byte offset is assumed for the state just before full, while a 2-byte offset is also assumed for the state just before empty (first
And each offset increment in the second offset data is
It corresponds to a 2-byte offset in the buffer).

During normal buffer operation, a write cycle of one data element, that is, one byte of data is started each time the write inhibit signal goes low. The write inhibit signal must be set before the next write cycle begins.
Switch to higher levels. During the write cycle, one data byte is written to the buffer chip. When the data element is written, the write cycle ends. During normal buffer operation, a read cycle of one data element, or one byte of data, is initiated each time the read inhibit signal goes low. The read inhibit signal transitions high before the start of the next read cycle. During a read cycle, one data byte is read from the buffer. The read cycle ends when a data byte is read.

As shown in FIG. 4A, before the buffer is full, the write inhibit signal goes low for the second to last available buffer positions to try to store the corresponding data element. Then, flag A just before full
This results in the FF going low. In this embodiment,
A low level of AFF represents a state just before full. If the program information specifies that the pre-full condition has been monitored and indicated, then an AFF is provided on the corresponding buffer status pin. The arrow pointing from the falling edge of the write inhibit signal to the falling edge of AFF indicates that the former caused the latter. Therefore, 2 from the time when the write inhibit signal shifts to the low level and the assertion of the flag immediately before full is triggered.
When the write cycle is complete and there is no intervening read cycle, the buffer is full. After this, when the second read inhibit signal goes high after the buffer is full, AFF goes high and is deasserted. The arrow pointing from the rising edge of the second read inhibit signal to the rising edge of AFF after the buffer is full indicates that the former caused the latter. At the completion of the two read cycles after the buffer is full, AFF is deasserted without the intervention of a write cycle.

As shown in FIG. 4B, when the read inhibit signal shifts to the low level for the second to the last buffer positions including the data elements which have not been read yet, the immediately preceding empty flag AEF is set to the low level. Will be moved to. In this example, the low level AEF represents the state just before empty. An AEF is provided on the buffer status pin if the program information specifies to monitor and direct the information immediately before empty. The arrow pointing from the falling edge of the read inhibit signal to the falling edge of AEF indicates that the former caused the latter. Therefore, when two read cycles are completed from the time when the read inhibit signal shifts to the low level and the assertion of the flag immediately before empty is triggered, the buffer becomes empty if there is no intervening write cycle. After this, when the second write inhibit signal goes high after the buffer is full, AEF is turned high and deasserted. The arrow pointing from the rising edge of the second write inhibit signal to the rising edge of AEF after the buffer is full indicates that the former caused the latter. At the completion of the two write cycles after the buffer is empty, AEF is deasserted if there is no intervening read cycle.

FIG. 5 is a block diagram showing a structural layout of a programmable buffer chip according to an embodiment of the present invention. It is intended to be programmed by the programming method of the invention described above. The buffer / buffer controller 20 comprises a buffer having a cell array for storing data elements and a corresponding access control circuit for reading and writing the buffer. The status monitor / flag generator 22 monitors the status status of the buffer, and according to the program information input to the buffer chip,
Represents a circuit that provides corresponding instructions on the buffer status pins. Program storage unit 24 represents a circuit that receives program information during a period in which the buffer chip is programmed and then stores the received program information. The above-mentioned first and second program registers are arranged in this part of the buffer chip. The reset / reset canceller 26 operates to reset the buffer chip in response to the application of a reset signal that puts the buffer chip in the reset mode, and further resets the buffer chip in response to the application of the reset cancellation signal. Represents a circuit that exits the mode and causes normal non-reset buffer operation. The reset operation is performed by initializing the pointer inside the status monitor / flag generator 22 that indicates the current position inside the buffer, and the buffer unit 2
It may also include the initialization of any access circuit within 0. The connection between the reset / reset cancellation unit 26 and the program storage unit 24 starts at the end of a normal predetermined reset period, and the latter receives the program information during the period ended when the reset release signal is applied. It shows that it operates.

FIG. 6 is a block diagram showing a structural layout of a programmable buffer chip according to another embodiment of the present invention. It is also intended to be programmed by the programming method of the invention described above. The configuration of this embodiment is the same as that shown in FIG. 5, except that a reset prohibition function is added to the block 26 and a data direction signal is applied to the program storage portion 24. The reset prohibition function is implemented by providing a corresponding circuit in the block 26. In response to an instruction in the program information stored in the program storage section 24, this circuit prohibits the reset performed when the next reset signal is generated if there is no such instruction. In the present embodiment, the program storage unit receives the program information in response to the data direction signal using one of the two sets of data pins indicated by the data direction signal.

The block constructs of the block diagrams of FIGS. 5 and 6 will not be explicitly described in more detail as they are easily conceivable by those skilled in the art in connection with conventional logic circuits. Moreover, the exact circuit of each block construction will vary from application to application depending on the circumstances involved and the construction of other constructions. The programmable buffer chip of the present invention can be easily constructed by those skilled in the art by referring to the programming method described above. For example, a counter or comparator can be used to keep track of how many buffer locations were written and where they were read. Also, when resetting,
It is also possible to store a predetermined value in the counter so that the count value identifies the position where the writing or reading will be performed next.

The above description merely relates to the preferred embodiment of the present invention. Those skilled in the art should recognize that other embodiments, although not specifically disclosed, are within the scope of the claims.

[Brief description of drawings]

FIG. 1A is an I / I related to a disclosed embodiment of the invention.
FIG. 6 is an external plan view of a non-programmable basic buffer chip having O pins. B is an external plan view of a programmable buffer chip with I / O pins, related to the disclosed embodiments of the present invention.

FIG. 2 is a diagram showing two program registers included in a programmable buffer chip according to one embodiment of the present invention.

FIG. 3 illustrates the timing of operations in disclosed embodiments of steps included in a method in accordance with the present invention.

FIG. 4A is a diagram showing assertion and deassertion of a flag just before full according to program information input to a programmable buffer chip. FIG. 9B is a diagram showing assertion and deassertion of an immediately-before-empty flag according to program information input to the programmable buffer chip.

FIG. 5 is a block diagram showing a structural layout of a programmable buffer chip according to an embodiment of the present invention.

FIG. 6 is a block diagram showing a structural layout of a programmable buffer chip according to another embodiment of the present invention.

[Explanation of symbols]

 20 buffer / buffer control unit 22 status monitor / flag generator 24 program storage unit 26 reset / reset release unit

[Procedure amendment]

[Submission date] January 7, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Correction content]

[Claims]

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction content]

The program information contemplated by the preferred embodiment of the present invention is in the form of two 9-bit program instruction words. In the first command word, 7 for specifying the offset (first offset data) for the state immediately before full
Bits are allocated. The increment of each offset is
Corresponds to a 2-byte offset in the buffer. Therefore, if the first offset in this instruction word corresponds to a condition where the buffer is full except for 2 bytes of data, the pre-fill condition covers a range containing 127x2 bytes from the actual full condition. To do. Similarly, the second
7 bits for designating an offset (second offset data) with respect to the buffer empty state are allocated to the instruction word. Each offset increment corresponds to a 2-byte offset in the buffer. Thus, if the second offset in this instruction word corresponds to a state where the buffer is empty except for 2 bytes of data, the just-before-empty state covers a range containing 127x2 bytes from the actual empty state. Depending on the size of the buffer itself, it may be desirable to have more or less offset bits in the instruction word. For a 1Kx9-bit FIFO buffer, the proper choice is to have 7 bits for the offset bit in each instruction word. 512x9 bit FI
In the FO buffer, the offset bit in each instruction word is 6
Making a bit is a good choice. Also, how many bytes correspond to each offset increment depends on the application environment and may change in different embodiments.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

In another embodiment, the program indication bit is P16 if P16 is a basic buffer chip.
It only determines whether or not it functions similarly. P15
Indicates the state immediately before full or is initialized to indicate the full state like P15 of the basic buffer chip depends on the value of the first offset data. Whether P17 indicates the state immediately before empty or whether it is initialized to indicate the empty state like P17 of the basic buffer chip depends on the value of the second offset data. If the first offset data is zero, the programmable buffer chip responds by acting to indicate that P15 is full (as in the basic buffer chip). If the first offset data is non-zero, the programmable buffer chip automatically responds to this by using the offset specified by the first offset data, P1
5 acts to indicate the state just before full. If the second offset data in the second program word is zero,
In response, the programmable buffer chip responds to the P1
7 acts to indicate an empty state (as in the basic buffer chip). If the second offset data is non-zero, the programmable buffer chip automatically responds to this by using the offset specified by P1 second offset data to cause P17 to indicate an immediate empty state. To do. In this embodiment, of course, the programmable buffer chip has a logic circuit for testing the value of each offset data, program instruction bits, the first offset data, and a combination of the second offset data, the programmable buffer
Together, they indicate whether the buffer status conditions monitored by the chip are the same or different as monitored by the corresponding pins of the basic buffer chip.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0040

[Correction method] Change

[Correction content]

As shown in FIG. 4B, when the read inhibit signal shifts to the low level for the second to the last buffer positions including the data elements which have not been read yet, the immediately preceding empty flag AEF is set to the low level. Will be moved to. In this example, the low level AEF represents the state just before empty. An AEF is provided on the buffer status pin if the program information specifies to monitor and direct the information immediately before empty. The arrow pointing from the falling edge of the read inhibit signal to the falling edge of AEF indicates that the former caused the latter. Therefore, when two read cycles are completed from the time when the read inhibit signal shifts to the low level and the assertion of the flag immediately before empty is triggered, the buffer becomes empty if there is no intervening write cycle. After this, when the second write inhibit signal goes high after the buffer is empty , AEF goes high and is deasserted. The arrow pointing from the rising edge of the second write inhibit signal to the rising edge of AEF after the buffer is empty indicates that the former caused the latter. After the buffer is empty, the two write cycles are complete

Claims (26)

[Claims] 1. A method for inputting program information into a programmable memory device, said memory device comprising:
Pin compatible and functionally interchangeable with a memory device designed for use as a non-programmable memory device, the programmable memory device comprising data storage means and at least one flag program register. , Compatible input data pins, compatible output pins, compatible condition / status pins, compatible read / write control pins,
And a compatible reset pin,
Applying the active clock signal, having at least a first duration, to the compatible reset pin to set the memory device in a reset mode for the first duration; Holding the reset clock signal active for a second duration after the first duration and setting the memory device in a program mode for the second duration; Compatible read / write during period
Inputting at least a first active enable signal to one of the write control pins, via one of the compatible input pin and the compatible output pin for the second duration. Inputting at least a portion of the program information, storing the program information in the at least one flag program register for the second duration, and second active after the second duration. A valid enable signal to one of the compatible read / write control pins, via the compatible input pin when the second active enable signal corresponds to a write operation, Inputting non-program data to the data storage means, the second active enable signal Outputting non-programmed data from the data storage means via the compatible output pin when responding to a read operation, and in response to the second active enable signal Via a condition / status pin to provide a programmable requested status of the data currently stored in said data storage means as defined in a flag program register,
Outputting data buffer condition / status data, wherein the programmable memory device is responsive to a first value of a programmed bit currently stored in the at least one flag register to reset the reset mode. And the programmable memory device is not reset during the reset mode when the value of the programmed bit is other than the first value. 2. A method for inputting program information into a programmable memory device, said memory device comprising:
A pin compatible and functionally interchangeable with a memory device designed for use as a non-programmable memory device, said programmable memory device comprising data storage means and at least one flag program. Registers, compatible input data pins,
A compatible output pin, a compatible condition / status pin, a compatible read / write control pin, and a compatible reset pin, the method comprising at least a first duration. Applying an active clock signal to the compatible reset pin to set the memory element in a reset mode for the first duration, and a second after the first duration. Holding the reset clock signal active for a duration of time and setting the memory device in a program mode for the second duration of time, the compatible read for the second duration of time. /
Inputting at least a first active enable signal to one of the write control pins, via one of the compatible input pin and the compatible output pin for the second duration. Inputting at least a portion of the program information, storing the program information in the at least one flag program register for the second duration, and second active after the second duration. A valid enable signal to one of the compatible read / write control pins, via the compatible input pin when the second active enable signal corresponds to a write operation, Inputting non-program data to the data storage means, the second active enable signal Outputting non-programmed data from the data storage means via the compatible output pin when responding to a read operation, and in response to the second active enable signal Outputs via a condition / status pin, a data buffer condition / status data which provides a programmable requested status of the data currently stored in said data storage means defined in a flag program register. The at least first active enable signal comprises:
Furthermore, a data direction signal is selectively included to selectively determine an input direction of the program information via either the compatible input pin or the compatible output pin. How to enter program information 3. The programmable buffer chip inputs information for determining a buffer status condition, which is monitored by at least one buffer status pin during a period disguised as an extension period for a reset extension operation, A method of achieving compatibility between the programmable buffer chip and a non-programmable basic buffer chip having the same number of I / O pins, comprising:
The basic buffer chip is operable to enter a reset mode for resetting in response to a reset signal and then exit the reset mode in response to a reset release signal. A reset signal to reset the buffer chip to a predetermined initial state, and to set the reset mode for a predetermined shortest duration, the buffer chip for an extension period exceeding the predetermined reset period. To start a non-reset buffer operation, stop applying a reset release signal to the programmable buffer chip, and input program information to the programmable buffer chip, an extended reset period. Disguised as a time window Forming program information for determining a selection of a buffer status condition monitored by the at least one buffer status pin when the programmable buffer chip is in the normal mode during the spoofed reset period. Inputting to the programmable buffer chip, and applying the reset release signal to the programmable buffer chip after the input step, thereby putting the programmable buffer chip into a normal mode, whereby the The programmable buffer chip is provided with compatibility with the basic buffer chip, and part of the program information is such that when the reset signal is generated, the programmable buffer chip enters a reset mode. Indicating whether to inhibit the initiation of a reset operation, whereby the programmable buffer chip, when the program information stored in the programmable buffer chip indicates such inhibition, then Operating to inhibit entry into a reset mode when a reset signal is applied. 4. The programmable buffer chip inputs information for determining a buffer status condition, which is monitored by at least one buffer status pin during a period disguised as an extension period for a reset extension operation, A method of achieving compatibility between the programmable buffer chip and a non-programmable basic buffer chip having the same number of I / O pins, comprising:
The basic buffer chip is operable to enter a reset mode for resetting in response to a reset signal and then exit the reset mode in response to a reset release signal. A reset signal to reset the buffer chip to a predetermined initial state, and to set the reset mode for a predetermined shortest duration, the buffer chip for an extension period exceeding the predetermined reset period. To start a non-reset buffer operation, stop applying a reset release signal to the programmable buffer chip, and input program information to the programmable buffer chip, an extended reset period. Disguised as a time window Forming program information for determining a selection of a buffer status condition monitored by the at least one buffer status pin when the programmable buffer chip is in the normal mode during the spoofed reset period. Inputting to the programmable buffer chip, and applying the reset release signal to the programmable buffer chip after the input step, thereby putting the programmable buffer chip in a normal mode, whereby the The programmable buffer chip is provided with the compatibility with the basic buffer chip, and the input step includes the step of inputting program information to the data element during the normal mode unless the program information is input. Via the data pins used to output data elements from the buffer memory during the normal mode, unless the program information is input. Applying a direction signal to the programmable buffer chip, the direction signal corresponding to a control pin of the basic buffer chip, through a pin having no functional meaning during reset of the basic buffer chip, The method of claim 1, wherein the program information is applied to the programmable buffer chip and during the input step, the program information is input through a pin indicated by the direction signal. 5. The programmable buffer chip inputs information for determining a buffer status condition, which is monitored by at least one buffer status pin during a period disguised as an extension period for a reset extension operation, A method of achieving compatibility between the programmable buffer chip and a non-programmable basic buffer chip having the same number of I / O pins, comprising:
The basic buffer chip is operable to enter a reset mode for resetting in response to a reset signal and then exit the reset mode in response to a reset release signal. A reset signal to reset the buffer chip to a predetermined initial state, and to set the reset mode for a predetermined shortest duration, the buffer chip for an extension period exceeding the predetermined reset period. To start a non-reset buffer operation, stop applying a reset release signal to the programmable buffer chip, and input program information to the programmable buffer chip, an extended reset period. Disguised as a time window Forming program information for determining a selection of a buffer status condition monitored by the at least one buffer status pin when the programmable buffer chip is in the normal mode during the spoofed reset period. Inputting to the programmable buffer chip, and applying the reset release signal to the programmable buffer chip after the input step, thereby putting the programmable buffer chip in a normal mode, whereby the The programmable buffer chip is provided with compatibility with the basic buffer chip, and the program information is stored in a buffer monitored by the at least one buffer status pin of the basic buffer chip. A fast status condition includes a particular indication of whether it is the same as or different from that monitored by a respective buffer status pin of the programmable buffer chip. 6. The method of claim 5, wherein a buffer memory within the programmable buffer chip and a buffer memory within the basic buffer memory maintain a first-in first-out procedure for data transfer. 7. The method of claim 6, wherein the reset signal is a signal level applied to a reset pin of the programmable buffer chip and the reset release signal is applied to a reset pin of the programmable buffer chip. Another signal level according to the present invention. 8. The method of claim 5, wherein the basic buffer chip has two buffer status pins and the programmable buffer chip has two corresponding buffer status pins. The first status pin of the basic buffer chip indicates a buffer full state, the second status pin of the basic buffer chip indicates a buffer empty state, and the first and second status pins of the basic buffer chip are When the particular indication specifies that the same buffer status being monitored is monitored by corresponding first and second status pins of the programmable buffer chip, the first buffer of the programmable buffer chip is Status pin buffer full It indicates the state, and the second status pin of said programmable buffer chip represents a buffer empty state, wherein the. 9. The method of claim 8, wherein a buffer status condition different from that monitored by the first and second status pins of the basic buffer chip causes a corresponding first and second buffer status of the programmable buffer chip. The first status pin of the programmable buffer chip is designated by the first offset data contained in the program information when the particular indication specifies to be monitored by a second status pin. The buffer is full, indicating a buffer full state, except for a number of storage locations, and the second status pin of the programmable buffer chip is designated by a second offset data contained in the program information. Said buffer, except for the number of storage locations It is empty, showing a buffer empty state just before, wherein the. 10. The method of claim 9, wherein the basic buffer chip comprises a third buffer status pin, while the programmable buffer chip comprises a corresponding third buffer status pin, The buffer status pin of the basic buffer chip monitors a buffer state intermediate between a full state and an empty state, and the same buffer status state monitored by the third buffer status pin of the basic buffer chip is The third status pin of the programmable buffer chip is connected to the third buffer status of the basic buffer chip when the particular indication specifies to be monitored by the corresponding buffer status pin of the programmable buffer chip. Monitoring the same state and being monitored by taspine, wherein the. 11. The method of claim 10, wherein a buffer status condition different from that monitored by the third buffer status pin of the basic buffer chip is monitored by a corresponding buffer status pin of the programmable buffer chip. When the specific instruction specifies that the third status pin of the programmable buffer chip is
Monitoring both buffer full and buffer empty conditions. 12. The method according to claim 9, wherein the specific instruction in the program information includes the first offset data and the second offset data, and the first offset data has a predetermined value. , The first buffer status pin of the programmable buffer chip is connected to the first buffer status pin of the basic buffer chip.
The buffer status pin of the programmable buffer chip indicates that the buffer full state is indicated, and when the second offset data has a predetermined value, the second buffer status pin of the programmable buffer chip is Two
A method of indicating that the buffer is empty, as with the buffer status pin of. 13. The method of claim 12, wherein when the first offset data has a value other than the predetermined value, the first offset data of the programmable buffer chip.
The buffer status pin of indicates that the buffer is about to be full immediately in accordance with the offset specified by the first offset data, and the second offset data has a value other than the predetermined value, The second of the programmable buffer chip
A buffer status pin indicating that the buffer status pin is in the state immediately before the buffer empty state according to the offset specified by the second offset data. 14. The method according to claim 11, wherein the specific instruction in the program information includes a program instruction bit, and one binary level of the program instruction bit is the first bit of the basic buffer chip. 3 indicates that the same state monitored by three buffer status pins is monitored by the corresponding third buffer status pin of the programmable buffer chip, the other binary level of the program indication bit is the basic level. Indicating that a different condition of the buffer chip monitored by the third buffer status pin is monitored by a corresponding third buffer status pin of the programmable buffer chip. 15. The method according to claim 14, wherein the specific instruction in the program information includes the first offset data and the second offset data, and the first offset data has a predetermined value. When taking a value, the first buffer status pin of the programmable buffer chip is changed to the first buffer status pin of the basic buffer chip.
The buffer status pin of the programmable buffer chip indicates that the buffer full state is indicated, and when the second offset data has a predetermined value, the second buffer status pin of the programmable buffer chip is Two
A method of indicating that the buffer is empty, as with the buffer status pin of. 16. The method according to claim 15, wherein the first offset data of the programmable buffer chip is different from the first offset data when the first offset data has a value other than the predetermined value.
The buffer status pin of indicates that the buffer is about to be full immediately in accordance with the offset specified by the first offset data, and the second offset data has a value other than the predetermined value, The second of the programmable buffer chip
A buffer status pin indicating that the buffer status pin is in the state immediately before the buffer empty state according to the offset specified by the second offset data. 17. The method of claim 11, wherein the reset signal is one signal level applied to a reset pin of the programmable buffer chip, and the reset release signal is a reset pin of the programmable buffer chip. The other signal level being applied. 18. The method according to claim 16, wherein the reset signal is one signal level applied to a reset pin of the programmable buffer chip, and the reset release signal is applied to a reset pin of the programmable buffer chip. The other signal level being applied. 19. The method of claim 11, wherein both the buffer on the programmable buffer chip and the buffer on the basic buffer chip maintain a first-in first-out procedure for data transfer. 20. The method of claim 11, wherein each of the first and second offset data is a binary value, each increment of which corresponds to a 2-byte offset in the programmable buffer. How to characterize. 21. The method according to claim 11, wherein the specific instruction in the program information is a single program instruction bit, and one binary level of the program instruction bit is the basic buffer chip. First, second, and third
Indicating that the same state monitored by the buffer status pins of the programmable buffer chip is monitored by the corresponding first, second, and third buffer status pins of the programmable buffer chip. The progress level is different from that monitored by the first, second, and third buffer status pins of the basic buffer chip when the corresponding first, second, and third states of the programmable buffer chip are different. A method of indicating by a buffer status pin that each is monitored. 22. The method of claim 21, wherein the reset signal is one signal level applied to a reset pin of the programmable buffer chip, and the reset release signal is a reset pin of the programmable buffer chip. The other signal level being applied. 23. The method of claim 13, wherein the program information includes two data words,
One data word includes the first offset data,
The other data word includes the second offset data, and during the inputting step, the first and second data words are continuously input to the programmable buffer chip. how to. 24. The method according to claim 5, wherein a part of the program information prohibits the programmable buffer chip from entering a reset mode and starting a reset operation when the reset signal is generated. When the program information already input to the programmable buffer chip indicates such prohibition, the programmable buffer chip enters the reset mode when the reset signal is next applied. A method of operating to prohibit the use of. 25. The method according to claim 5, wherein said inputting step is performed by inputting program information, if said program information is not input, data used for inputting said normal mode data element to a buffer memory. A programmable directional signal that indicates whether through a pin, or through a data pin that is used to output a data element from the buffer memory during the normal mode if the program information is not input. Applying to a buffer chip, the direction signal corresponding to a control pin of the basic buffer chip, having no functional meaning during resetting of the basic buffer chip, is applied to the programmable buffer chip through a pin, During the input step, the program Broadcast is input through the pin indicated by the direction signal, and wherein the. 26. The method according to claim 24, wherein the inputting step is performed by inputting program information, unless the program information is input, data used for inputting the data element to the buffer memory during the normal mode. A programmable directional signal that indicates whether through a pin or through a data pin used to output a data element from the buffer memory during the normal mode if the program information is not input. Applying to a buffer chip, the direction signal corresponding to a control pin of the basic buffer chip, having no functional meaning during reset of the basic buffer chip, is applied to the programmable buffer chip through a pin, During the input step, the program Information is input through the pin indicated by the direction signal, and wherein the.