JP2572195B2 - Method of programming a memory device that is pin compatible with a non-programmable memory and can be used as a non-programmable memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to a programmable buffer made on a single integrated circuit chip and to a programming method for such a buffer.

[0002]

2. Description of the Related Art A buffer is a data storage element commonly used for data transfer, from which data elements can be written and read out by one data source. Buffers, whether programmable or not, built on a single chip are called buffer chips. When such buffers communicate with the external environment, they are performed through I / O (input / output) pins of the buffer chip in which they are provided. Generally, buffer chips include buffer status pins assigned to monitor and indicate buffer status, such as full, empty, half full, and the like. Being programmable means that the particular buffer state monitored and indicated by the external environment at certain buffer status pins can be changed by external selection. The procedure for inputting program information is called programming. By inputting the program information to the buffer chip, the buffer chip is programmed. Once programmed, the user of the buffer chip can change the monitored buffer status state according to the specific requirements of the application environment in which the buffer chip is configured. Without the programming capability, the monitored buffer status state cannot be changed, thereby limiting the usefulness of the buffer chip.

[0003] Programmable buffer chips are known in the prior art. The programming possibilities themselves are not the subject of the present invention. Rather, the present invention is directed to a specific programming method that eliminates significant drawbacks common to all programmable buffers in the prior art, as well as buffer chips that can be programmed by such a method. A significant drawback of the prior art programmable buffer chip is the compatibility problem, i.e., lower than the non-programmable buffer chip.
ward) compatible.

[0004] Compatibility in the context of the present invention means interchangeability. One programmable buffer chip is compatible with a non-programmable buffer chip.
Remove this non-programmable buffer chip from the position in the original circuit, without causing malfunction in the original circuit,
This is the case when the pins match the programmable buffer chip and can be replaced. If the original circuit is not replaced with a programmable buffer chip, it will continue to operate as if it were operating with the original non-programmable buffer chip. Compatibility in this sense is backwards compatible, as more sophisticated buffer chips with programming capabilities remain compatible with basic buffer chips without programming capabilities. However, compatibility has never been achieved. Prior art programmable buffer chips that are compatible with non-programmable basic buffer chips having the same number of functional I / O pins are not yet known.

[0005]

The use of dedicated programming pins in the prior art is one reason that compatibility has not been achieved in the past. Dedicated programming pins are such that the signals applied thereto are only relevant to the programming of the buffer chip. If the programmable buffer chip has such dedicated programming pins, many problems can occur when replacing the programmable buffer chip with the original non-programmable buffer chip. There may be situations where the pin numbers do not match or the original system, which was not designed to work with a programmable buffer chip, would signal a dedicated programming pin. In either case, the system cannot get a proper response from the replaced buffer chip.

In accordance with one aspect of the present invention, there is provided a method for inputting program information to a programmable buffer chip, comprising the steps of: combining a programmable buffer chip with a non-programmable basic buffer chip having the same number of I / O pins; Achieve compatibility between The present invention
A spoofed time period is generated as an extended reset period, which is added at the end of the actual reset period. During this spoofing time, program information is input to the buffer chip, thus programming the buffer chip. The program information selects the buffer status state to be monitored. The monitored condition is indicated by at least one status pin.

[0007] According to another aspect of the present invention, there is provided a programmable buffer chip to which the programming method of the present invention is applied. The programmable buffer chip receives program information during a time period added at the end of the normal reset period and spoofed as an extension of the reset period.

[0008]

SUMMARY OF THE INVENTION The present invention is based on the existence of a non-programmable basic buffer chip reset mechanism. The basic buffer chip is
In response to the reset signal, a reset mode is entered for a predetermined minimum duration, during which a reset operation is performed to return the buffer chip to a predetermined initial state (eg, setting a flag indicating that the buffer is empty). Like that. After this period, in response to the reset release signal, the basic buffer chip exits reset mode, enters normal non-reset buffer operation, receives, stores, and outputs data elements. The period provided for the reset must be sufficient to complete the reset operation.

According to the present invention, when a reset signal is generated, the programmable buffer chip enters a reset mode for a sufficient predetermined duration to perform a reset operation. The reset release signal is not applied to the programmable buffer chip for a longer time period following the reset period. At the end of this longer time period, a reset release signal is applied. Thus, a longer period of time is added at the end of the actual reset period, and appears to disguise the extension of the reset period. Program information is input to the buffer chip during the camouflage period, and the programmable buffer is programmed during this period.

The above-described programming method requires that a reset operation be performed every time the buffer chip is programmed, since the programming is performed during the disguise extension period of the reset period. According to another embodiment of the present invention, during a normal reset period prior to a camouflage period for programming, the actual reset operation is inhibited,
The reset operation is not started each time the programmable buffer chip is about to be programmed.

According to the present invention, when a programmable buffer chip is replaced with a non-programmable basic buffer chip in the original system designed to operate with the non-programmable basic buffer chip,
Pin-to-pin compatibility between a programmable buffer chip and a non-programmable basic buffer chip is achieved. The original system will not operate to add an extended replacement period at the end of the normal reset period unless there is a malfunction, and the program information will be stored in the buffer chip during such additional time period disguised as an extension of the reset period. Is not intended to be input, so that the above-described trouble due to the exchange cannot occur.

[0012]

1A shows a non-programmable basic buffer chip 2. FIG. It has multiple I / O pins, but only a few are identified in FIG. 1A. P1 is
This is a read control pin for starting a read operation. When a read inhibit signal (ReadBar) is applied to P1 and it goes low, reading of the buffer is started. P2 is a write control pin for starting a write operation, and a write inhibit (Write B)
ar) When a signal is applied to P2 and it goes low, a write operation is started. P3 is a reset control pin for starting a series of reset operations in the buffer chip 2, and a reset inhibit (Reset Bar) signal is applied to P3.

The reset inhibit signal has two functional roles. When the reset inhibit signal goes low, if both P1 and P2 are high at that time, the buffer chip operates as a reset (Reset) signal for performing the reset operation by setting the buffer chip to the reset mode. The reset period starts when a reset signal is applied. When the reset inhibit signal changes to high level, reset release (Res
et Release) signal to terminate the reset mode, thus releasing the buffer chip from the reset mode and performing a normal non-reset buffer operation.

P4 to P12 are data input pins for a 9-bit data word, and P18 to P26
Even the data output pins for the 9-bit data word. P14 is a control signal pin, and has no functional meaning during the time when the basic buffer is in the reset mode and performing the reset operation. Thus, this may be any of a number of control pins on the basic buffer chip. P15, P16, and P17 are buffer status pins for monitoring a certain buffer status state based on the signal levels shown here. P15 monitors the fullness of the buffer by generating a predetermined signal level when the buffer is full. P16 monitors a buffer half full by generating a predetermined signal level when more than half of the buffer location has been written but not yet read. P17 generates a predetermined signal level when the buffer is empty,
Monitors buffer empty status. In the basic buffer chip 2, the buffer status states of full, half full, and empty are fixed and cannot be changed. Therefore, the basic buffer chip 2 is not programmable.

The illustrated basic buffer chip performs data transfer in a first-in-first-out procedure. The data element is
They are read from the buffer in the buffer chip and output from the buffer chip in the same order as they were input to and written to the buffer chip. The buffer is considered empty when no data elements have been written to the buffer or when all elements written to the buffer have been read. Also, when the buffer is full of data elements and they have not been read at all, the buffer is considered full. Also, a buffer is considered half full when more than half of the buffer locations contain data elements written to the buffer but have not yet been read.

FIG. 1B shows the programmable buffer chip 4. This has the same number of I / O pins as the basic buffer chip 2 in the same physical arrangement.
Each pin of the basic buffer chip has a pin corresponding to the programmable buffer chip. Like the basic buffer chip, the programmable buffer chip also has a read control pin P1, a write control pin P
2. Reset control pin P3, data input pins P4 to P12, buffer status pins P15 to P17
(The state to be monitored can be changed by programming), data output pins P18 to P26, and a data direction pin (Data Direction Pin).
P14 is provided.

The data direction pin P14 of the programmable buffer chip is used to realize a function of selectively inputting program information from one of two sets of I / O pins to the chip. One level signal applied to pin P14 indicates that data pins P4 through P12 are being used to input program information, and the other level signal applied to pin 14 is typically Indicates that the data output pins P18 to P26 are used for inputting program information.
Since the corresponding pin P14 in the basic buffer chip described above has no functional significance during the reset mode, by using P14 for programming by the programmable buffer chip, while this buffer chip is in the reset mode, If the program is executed in the same manner as above, compatibility with the basic buffer chip can be realized. In another embodiment, where the role of the pins used to input program information is fixed, there is no need to provide a data direction pin P14 for the purpose of selecting a pin. Rather, the data direction pin P14 may have the same function as the corresponding pin of the basic buffer chip.

In the programmable buffer chip 4, a state immediately before the buffer is full, defined when the buffer is full, except for a certain number of positions specified by an offset value entered into the buffer chip as part of the program information by the user. almost-full condition
on) can be monitored by P15. Also,
Almost-empty condition defined when the buffer is empty, except for a certain number of locations specified by the offset value entered into the buffer chip as part of the program information by the user.
on) can be monitored by P17. Furthermore,
One indication in the program information input to the buffer chip can cause P16 to monitor a half-full state of the buffer, or either a full or empty buffer state. When monitoring the buffer full or buffer empty state by P16, to determine which state is indicated by P16, check the status of the immediately full state indicated by P15 or the immediately empty state indicated by P17. Good. If the buffer is almost full, a positive indication at P16 will be interpreted by the outside world as full. Also, if the buffer is almost empty, a positive indication at P16 will be interpreted by the outside world as empty. To make this interpretation, simple gating logic is used. In addition, the program information is provided on pins P15, P16 so as to monitor the same state as monitored by the basic buffer chips P15, P16 and P17.
And setting of P17.

Although the physical pin arrangement is the same between the basic buffer chip 2 and the programmable buffer chip 4, the specific arrangement shown in FIGS. 1A and 1B is merely for convenience of illustration. belongs to. To achieve compatibility, which allows a programmable buffer chip to replace a basic buffer chip in a system that is not designed for programming, only the programming method, i.e., pins that are already present on the basic buffer chip, are used. A method for inputting program information into a programmable buffer chip to be used is required.

The program information contemplated by the preferred embodiment of the present invention is in the form of two 9-bit program instructions. The first instruction word has a value of 7 for designating an offset (first offset data) for the state immediately before being full.
Bits are assigned. The increment of each offset is
Equivalent to a 2-byte offset in the buffer. Thus, if the first offset in this instruction corresponds to a state in which the buffer is full except for two bytes of data, the state just before full covers the range including 127 × 2 bytes from the actual full state. I do. Similarly, the second
Are assigned 7 bits for designating an offset (second offset data) with respect to the buffer empty state. Each offset increment corresponds to a two byte offset in the buffer. Thus, if the second offset in this instruction corresponds to a state in which the buffer is empty except for two bytes of data, the state immediately before empty includes a range including 127 × 2 bytes from the actual empty state. Depending on the size of the buffer itself, the number of offset bits in the instruction word may be more or less. In a 1K.times.9-bit FIFO buffer, it is a proper choice to make the offset bits in each instruction word 7 bits. 512x9-bit FI
In the FO buffer, the offset bit in each instruction word is set to 6
Bits are a good choice. Also, how many bytes correspond to each offset increment depends on the application environment and may vary in different embodiments.

FIG. 2 shows the first and second program command words. The first program instruction is stored in a full flag program register, while the second program instruction is stored in an empty flag program register incorporated in the programmable buffer chip 4 of FIG. 1B. These program registers are used to receive and store program information. Since the basic buffer chip 2 is not programmable, it does not include any program registers for storing program information. Both program registers are
It is 9 bits long and stores a program instruction word of 9 bits each. The full flag program register operates to store a first command word including offset information (first offset data) for a state immediately before full, and the empty flag program register stores a second instruction including offset information for a state immediately before empty. In order to store the instruction word.

Bit 7 (eighth bit counting from bit zero) of the first and second program instructions is reserved for later offset extension. Until then, they are not used and may include dummy bits.

Bit 8 (the ninth bit counted from bit zero) of the first program instruction word is hereinafter referred to as a program instruction bit. Bit 8 determines whether the programmable buffer 4 is initialized to monitor one or more of the same states as monitored by the basic buffer chip 2. In one embodiment, when the program indicator bit is set low, the programmable buffer responds, as in the case of the basic buffer chip, indicating buffer full using P15 and buffering using P16. It is intended to indicate a half-full state of, and indicate an empty buffer state using P17. When the program instruction bit is set to a high level, the programmable buffer chip uses P15 to indicate the state immediately before full according to the first offset data in the first command word of the program information, and uses P17. It is intended to indicate a state immediately before empty according to the second offset data in the second instruction word of the program information, and to indicate both a full state and an empty state using P16. When indicating both a full state and an empty state using P16, the identification of the indicated state is determined by P15
, And P17. If an instruction immediately before being full was given at P15, the affirmative instruction at P16 would indicate a full state. P just before the sky
If given at 17, the affirmative indication of P16 would indicate an empty state. Thus, when the program indicator bit is set high, four states are monitored: just before full, just before empty, full and empty. Full and empty states are indicated by the same buffer status pin.

In another embodiment, the program indicator bit is P16 if P16 is a basic buffer chip.
It only determines whether or not it functions in the same way as. P15
Indicates whether the state is just before the full state or is initially set to indicate the full state like P15 of the basic buffer chip, depending on the value of the first offset data. Whether P17 indicates the state immediately before emptying or is initially set to indicate the empty state like P17 of the basic buffer chip depends on the value of the second offset data. If the first offset data is zero, the programmable buffer chip responds by acting to indicate that P15 is full (as in a basic buffer chip). If the first offset data is non-zero, the programmable buffer chip automatically responds to P1 using the offset specified by the first offset data.
5 acts to indicate the state immediately before full. If the second offset data in the second program word is zero,
The programmable buffer chip responds by
7 acts to indicate an empty state (as in the case of a basic buffer chip). If the second offset data is non-zero, the programmable buffer chip automatically responds by using the offset specified by P1 second offset data to cause P17 to indicate a just-before-empty condition. I do. In this embodiment, of course, the programmable buffer chip is provided with a logic circuit for checking the value of each offset data, and the programmable buffer chip uses a combination of the program instruction bit, the first offset data, and the second offset data to generate the programmable buffer chip.
Together, they indicate whether the buffer status state monitored by the chip is the same as or different from that monitored by the corresponding pin of the basic buffer chip.

Bit 8 (the ninth bit counted from bit zero) of the second program command is used to determine whether the reset operation is prohibited if the programmable buffer chip is legally placed in reset mode unless disabled next time. Determine whether or not. This is a reset prohibition instruction bit. The significance of this mechanism will be apparent in light of the discussion that follows herein. This gives the option of not resetting the buffer each time the programmable buffer chip is programmed. In another embodiment where this option is not provided, it is not necessary to include a reset prohibition instruction bit in the program information.

In order to obtain a proper understanding of the programming method according to the invention, the reset mechanism of the basic buffer chip 2 will first be described.

Resetting means initializing the buffer to a predetermined state and preparing to receive a new set of data elements. For example, if the buffer is half full after receiving the first group of data elements,
Resetting resets the buffer to its initial state, as if no data elements had been written to the buffer and it is now empty. After reset, the buffer is ready to receive a new set of data elements. If pointers in the buffer are used to point to certain buffer locations relative to the buffer's current state, these pointers will be initialized to the state associated with the initial buffer state.

In the basic buffer chip 2, if the read inhibit and write inhibit signals are both high, when a reset signal is applied to pin P3, the buffer chip is set to the reset mode, and the buffer chip goes through a series of Start the reset operation. After a sufficient time period to complete the reset operation has elapsed, a reset release signal is applied to pin P3, causing the buffer chip to exit the reset mode and start the next non-reset buffer operation, thereby causing the reset mode to begin. To end.

The programming method according to the present invention assumes operation when the basic buffer chip enters and exits reset mode (rely on). For this reason, the programmable buffer chip which intends to use the programming method according to the present invention must have the same mechanism for entering and exiting the reset mode if the backward compatibility with the basic buffer chip is to be achieved.

The programming method according to the present invention adds an extended time period, which is disguised as an extension of the reset period, at the end of the reset period. During this spoofing time period, the program information is input to the programmable buffer chip and the reset operation has already been completed, but the chip is still in an idle state as if it had been reset. By inputting the program information in this way, the programmable buffer chip can be made compatible with the corresponding non-programmable basic buffer chip. This means that when the programmable buffer chip is placed in the environment designed for the basic buffer chip, the circuit in that environment will generate the spoofed reset extension period and add the program information during that period, as well as add to the normal reset period. Because they don't even try to enter them. Without the camouflage reset extension period for programming, the programmable buffer chip operates as if it were not programmable.

FIG. 3 shows the format of two program command words.
Transfer program information to programmable buffer chip 4
Occurs in a series of steps taken to enter
It shows the timing of the operation. First of all,
Set inhibit signal, read inhibit signal, and write inhibit
All signals are high. Reset disable signal is low level
The basic buffer chip 2
In addition, a series of reset operations
It starts inside the loop 4. The predetermined period of the shortest duration is
It is necessary to perform a series of reset operations. this period
Is T in FIG._rsIt is shown as Normally basic
Buffer buffer chip, the period T_rsReset at the end of
The release signal (the reset inhibit signal that has been
The reset mode is applied to the reset signal P3. I
Program information
4, the reset release signal is applied for a period of time.
T _rsExtension period T beyond_extOnly late. This period T
_extIs the disguised extended reset period, during which time
Input program information to programmable buffer chip
You do it. As shown in FIG._extIs normal
Reset period T_rsHas been added to the end. Period T
_extDuring this time, the read inhibit signal first goes low,
Confirm that the program information is input.
Buffer tip 4 is notified. Next, the read inhibit signal is
Converted to a higher level. In another embodiment, for this purpose,
Some other signal may be used for this. I just need one
Is the period T _rsFollowed by a signal
The first and second program instructions arrive at the programmer chip.
Is to inform you that After this, the first and second
Program instruction word is programmable buffer chip 4
Are input in order.

For each command word, the write inhibit signal is
Before a command word is input, it is initially low.
The write inhibit signal remains low for a certain duration and transitions to its initial state in preparation for going low again. Thus, the write inhibit signal is output twice,
That is, switching is performed once each time each program command is input. As already mentioned, the first program instruction contains offset information about the buffer just before full condition and is stored in the full buffer flag register. The second program command includes offset information on the buffer immediately before the empty state, and is stored in the empty buffer flag register. In another embodiment, the set of first and second program instructions may be reversed.

In the embodiment having the data direction pin P14, just before the write inhibit signal is switched for the first time during the T _ext period, the direction signal DIR is set to the data direction pin P14.
Is applied to Thus, the state of the DIR signal is
P4 through P1
2, or which set of pins P18 to P26
It is notified whether a program command to be input to the programmable buffer chip 4 is transmitted. In one embodiment, when in the low level state, select pins P4-P12,
In the high level state, pins P18 to P26 are selected. This choice may be reversed in other embodiments.

As described above, the program information is T _ext
During the period, that is, during the disguise extension of the normal reset period, the input is made to the programmable buffer chip 4. The input process in the specific embodiment shown here includes: setting the read inhibit signal to low level, applying the direction signal DIR to the pin P14, and once to input one program command, and Switching the write inhibit signal once more to input the second program command (the command is input through the set of I / O pins selected by the signal on pin P14).

[0035] According to the above-described embodiment, each time the programmable buffer chip is programmed, performed also reset operation during the period T _rs prior to the period T _ext. This may not be desirable. In another embodiment, the programmable buffer chip performs the next stop unless stopped.
An instruction as to whether or not to start the reset operation may be included in the program information. Bit 8 (the ninth bit from bit zero) of the second program command is used for this purpose. One state of this bit indicates to the programmable buffer chip 4 that the reset operation should not be performed during the next T _rs period, and the other state of this bit is normally not stopped during the next T _rs period. The action to be taken is shown in the programmable buffer chip 4 to be reset.

The above-described basic buffer chip has a single reset pin, where both a reset signal (a reset prohibition signal that transits to a low level) and a reset release signal (a reset prohibition signal that transits to a high level) are provided. Is applied, but some other basic buffer chips have different configurations. For a basic buffer chip that has separate pins for receiving reset and reset release signals, a compatible programmable buffer chip must have corresponding separate pins.

FIG. 4A illustrates the assertion (assess) of the just before full signal (flag) AFF according to a preferred embodiment of the present invention.
rtion) and deassertion (deassert)
FIG. 4B shows the assertion and deassertion of the signal (EF) AEF just before empty. For convenience of illustration, a two-byte offset is assumed for the state just before full, while a two-byte offset is also assumed for the state just before empty (first).
And each offset increment in the second offset data is
(In a buffer, this is equivalent to a 2-byte offset.)

During normal buffer operation, each time the write inhibit signal goes low, a write cycle of one data element, ie, one byte of data, is started. Before the next write cycle starts, the write inhibit signal
Switch to a higher level. During a write cycle, one data byte is written to the buffer chip. When the data element has been written, the write cycle ends. During normal buffer operation, each time the read inhibit signal goes low, a read cycle of one data element, ie, one byte of data, is initiated. The read inhibit signal transitions high before the start of the next read cycle. During a read cycle, one data byte is read from the buffer. When the data bytes have been read, the read cycle ends.

As shown in FIG. 4A, before the buffer is full, the write inhibit signal goes low for the second to last available buffer locations and attempts to store the corresponding data element. Then, just before full flag A
This results in FF going low. In this embodiment,
The low level AFF indicates a state immediately before being full. If the program information specifies that a just-full condition has been monitored and indicated, an AFF is provided to the corresponding buffer status pin. An arrow pointing from the falling edge of the write inhibit signal to the falling edge of the AFF indicates that the former has caused the latter. Therefore, the write inhibit signal shifts to the low level, and the assertion of the immediately before full flag is triggered from the time when the write inhibit signal is asserted.
When the first write cycle is completed, the buffer is full without the intervention of a read cycle. Thereafter, when the second read inhibit signal goes high after the buffer is full, the AFF goes high and is deasserted. An arrow pointing from the rising edge of the second read inhibit signal to the rising edge of the AFF after the buffer is full indicates that the former caused the latter. At the completion of the two read cycles after the buffer is full, AFF is deasserted if no write cycle is involved.

As shown in FIG. 4B, when the read inhibit signal goes low for the second to last buffer positions including the data elements that have not been read yet, the immediately preceding empty flag AEF goes low. Will be transferred to. In this embodiment, the low level AEF indicates a state immediately before empty. AEF is provided on the buffer status pin if the program information specifies to monitor and indicate the just before empty information. An arrow pointing from the falling edge of the read inhibit signal to the falling edge of AEF indicates that the former caused the latter. Therefore, when two read cycles are completed from the time when the read inhibit signal goes low to trigger the assertion of the just-before-empty flag, the buffer becomes empty unless a write cycle is involved. Thereafter, when the second write inhibit signal after the buffer is emptied goes high, AEF goes high and is deasserted. Arrows pointing from the rising edge of the second write inhibit signal after the buffer is emptied to the rising edge of AEF indicate that the former caused the latter. After the buffer is emptied, AEF is deasserted at the completion of the two write cycles and without the intervention of a read cycle.

FIG. 5 is a block diagram showing a structural arrangement of a programmable buffer chip according to one embodiment of the present invention. This is intended to be programmed by the programming method of the present invention described above. The buffer / buffer control unit 20 includes a buffer having a cell array for storing data elements, and a corresponding access control circuit for performing reading and writing with the buffer. The status monitor / flag generator 22 monitors the status of the buffer, and according to the program information input to the buffer chip,
Represents a circuit that supplies a corresponding indication to a buffer status pin. Program storage unit 24 represents a circuit that receives program information during a period in which the buffer chip is programmed, and then stores the received program information. The first and second program registers described above are located in this part of the buffer chip. The reset / reset release unit 26 operates to reset the buffer chip in response to the application of the reset signal for setting the buffer chip to the reset mode, and further resets the buffer chip in response to the application of the reset release signal. A circuit for exiting the mode and performing a normal non-reset buffer operation. The reset operation is performed by initializing a pointer in the status monitor / flag generator 22 indicating the current position in the buffer,
It can also include initialization of any of the access circuits inside 0. The connection between the reset / reset release unit 26 and the program storage unit 24 starts at the end of a normal predetermined reset period, and during the period that ends when the reset release signal is applied, the latter receives program information. It indicates that it operates.

FIG. 6 is a block diagram showing a structural arrangement of a programmable buffer chip according to another embodiment of the present invention. This is also intended to be programmed by the programming method of the present invention described above. The configuration of this embodiment is the same as the configuration shown in FIG. 5 except that a reset prohibition function is added to the block 26 and a data direction signal is applied to the program storage section 24. The reset prohibition function is implemented by providing a corresponding circuit in the block 26. This circuit, in response to an instruction in the program information stored in the program storage unit 24, prohibits a reset performed when the next reset signal is generated without this instruction. In this embodiment, in response to the data direction signal, the program storage unit receives the program information using one of the two data pins indicated by the data direction signal.

The block components of the block diagrams of FIGS. 5 and 6 will not be described in further detail here, as they are all readily apparent to those skilled in the art in connection with conventional logic circuits. Furthermore, the exact circuit of each block component will vary from application to application, depending on the context involved and the structure of the other components. The programmable buffer chip of the present invention can be easily constructed by those skilled in the art by referring to the above-described programming method. For example, a counter or a comparator can be used to track how many buffer locations have been written and from which locations have been read. Also, when performing a reset,
A predetermined value may be stored in the counter, and the count value may identify a position to be next written or read.

The above description merely relates to the preferred embodiment of the invention. One of ordinary skill in the art should recognize that other embodiments, although not specifically disclosed, are within the scope of the following claims.

[Brief description of the drawings]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is an illustration of I / O associated with a disclosed embodiment of the invention
FIG. 4 is an external plan view of a non-programmable basic buffer chip having O pins. B is an external plan view of a programmable buffer chip having I / O pins, according to a disclosed embodiment of the present invention.

FIG. 2 illustrates two program registers included in a programmable buffer chip, according to one embodiment of the present invention.

FIG. 3 shows the timing of the operation of the steps included in the method according to the invention in the disclosed embodiment.

FIG. 4A is a diagram showing assertion and deassertion of a flag immediately before being full based on program information input to a programmable buffer chip. FIG. 4B is a diagram illustrating assertion and deassertion of an immediately preceding empty flag based on program information input to a programmable buffer chip.

FIG. 5 is a block diagram showing a structural arrangement of a programmable buffer chip according to one embodiment of the present invention.

FIG. 6 is a block diagram showing a structural arrangement of a programmable buffer chip according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 20 buffer / buffer control unit 22 status monitor / flag generator 24 program storage unit 26 reset / reset release unit

Claims (5)

(57) [Claims] A method for inputting program information to a programmable memory device, said programmable memory device having a pin compatibility with a memory device designed for use as a non-programmable memory device. Yes,
And functionally interchangeable, wherein the programmable memory element comprises at least one data storage means.
One flag program register and a compatible input pin
A compatible output pin, a compatible condition / status pin, a compatible read / write control pin, and a compatible reset pin, the method comprising: Active reset with a duration of
The door clock signal, is applied to the reset pin of the compatible, the step of setting said in the first duration programmable note <br/> Li element in the reset mode, the after the first duration between the two of duration, the Aku
The Restorative reset clock signal held in the active state during said second duration, the step of setting said programmable note <br/> Li elements in the program mode, during said second duration, said compatibility Reading with
One of the write control pins has at least a first active
Inputting a buoy enable signal, during said second duration, through one of the output pins on the compatible input pin and having the compatibility, the step of inputting at least part of said program information, the during the second duration, the program information, wherein the step of storing at least one flag program register, after said second duration, read / write the second activator buoy enable signal, with the compatible inputting to the one control pin, step second activator buoy enable signal when corresponding to the write operation, via the input pin of the compatible inputs unprogrammed data in the data storage device, when the second activator buoy enable signal corresponds to a read operation, from the data storage means, said each other Via an output pin of gender, the step of outputting the non-program data, and in response to said second activator buoy enable signal, via the condition / status pin with the compatible, the small
Outputting data buffer condition / status data providing a programmably requested status of the data currently stored in said data storage means, as defined in at least one flag program register; Wherein the programmable memory device is reset during the reset mode in response to a first value of a programmed bit currently stored in the at least one flag register; and A program information input method, wherein the reset is not performed during the reset mode when the value of the programmed bit is other than the first value. 2. A method for inputting program information to a programmable memory device, said programmable memory device being pin compatible with a memory device designed for use as a non-programmable memory device. There is, and is intended functionally interchangeable, the programmable memory device includes a data storage means, and at least one flag program register, incoming compatible
A power pin , a compatible output pin, a compatible condition / status pin, a compatible read / write control pin, and a compatible reset pin, the method comprising: Active reset with a duration of 1
The door clock signal, is applied to the reset pin of the compatible, the step of setting said in the first duration programmable note <br/> Li element in the reset mode, the after the first duration between the two of duration, the Aku
The Restorative reset clock signal held in the active state during said second duration, the step of setting said programmable note <br/> Li elements in the program mode, during said second duration, said compatibility Reading with
One of the write control pins has at least a first active
Inputting a buoy enable signal, during said second duration, through one of the output pins on the compatible input pin and having the compatibility, the step of inputting at least part of said program information, the during the second duration, the program information, wherein the step of storing at least one flag program register, after said second duration, read / write the second activator buoy enable signal, with the compatible inputting to the one control pin, step second activator buoy enable signal when corresponding to the write operation, via the input pin of the compatible inputs unprogrammed data in the data storage device, when the second activator buoy enable signal corresponds to a read operation, from the data storage means, said each other Via an output pin of gender, the step of outputting the non-program data, and in response to said second activator buoy enable signal, via the condition / status pin with the compatible, the small
Providing programmably requested status of data currently stored in said data storage means, defined in at least one flag program register;
Step of outputting data buffer condition / status data consists, at least a first activator buoy enable signal further input pin of said compatible or via any of the output pins with the compatible A program information input method including a data direction signal for selectively determining an input direction of the program information. 3. Inputting information to a programmable buffer chip to determine a buffer status state, which is monitored by at least one buffer status pin during a period disguised as an extension period for a reset extension operation, A method for achieving compatibility between said programmable buffer chip having the same number of I / O pins and a non-programmable basic buffer chip, comprising:
The non-programmable basic buffer chip is operable to enter a reset mode for resetting in response to a reset signal, and then to exit reset mode in response to a reset release signal. A reset signal is applied to the buffer chip to reset the programmable buffer chip to a predetermined initial state .
Step of setting a reset period between the reset mode, for an extended period exceeding the predetermined reset time period, the flop
The programmable buffer chip is set to a normal mode to start a non-reset buffer operation, to stop applying a reset release signal to the programmable buffer chip, and to extend program input to the programmable buffer chip. Forming a spoofed time window as the reset period, wherein during the spoofed reset period, when the programmable buffer chip is in the normal mode, a buffer status state monitored by the at least one buffer status pin is set. Inputting program information for determining a selection to the programmable buffer chip; and, after the inputting step, applying the reset release signal to the programmable buffer chip, thereby The step of logging llama Bull buffer chip to the normal mode, consists, thereby, provide compatibility with the non-programmable basic buffer chip to the programmable buffer chip, a part of the program information, upon occurrence of the reset signal, Indicates whether to inhibit the programmable buffer chip from entering reset mode and initiating a reset operation, whereby the program information stored in the programmable buffer chip indicates such inhibition. Wherein the programmable buffer chip operates to inhibit entering a reset mode the next time the reset signal is applied. 4. Inputting information for determining a buffer status state, which is monitored by at least one buffer status pin, during a period disguised as an extension period for a reset extension operation, to a programmable buffer chip, A method for achieving compatibility between said programmable buffer chip having the same number of I / O pins and a non-programmable basic buffer chip, comprising:
The non-programmable basic buffer chip is operable to enter a reset mode for resetting in response to a reset signal, and then to exit reset mode in response to a reset release signal. A reset signal is applied to the buffer chip to reset the programmable buffer chip to a predetermined initial state .
Step of setting a reset period between the reset mode, for an extended period exceeding the predetermined reset time period, the flop
The programmable buffer chip is set to a normal mode to start a non-reset buffer operation, to stop applying a reset release signal to the programmable buffer chip, and to extend program input to the programmable buffer chip. Forming a spoofed time window as the reset period, wherein during the spoofed reset period, when the programmable buffer chip is in the normal mode, a buffer status state monitored by the at least one buffer status pin is set. Inputting program information for determining a selection to the programmable buffer chip; and, after the inputting step, applying the reset release signal to the programmable buffer chip, thereby Consists step, to the log llama Bull buffer chip to the normal mode, by which the given compatibility with the non-programmable basic buffer chip to the programmable buffer chip, wherein the input step, the input of the program information, the program information If not, the data element during the normal mode is input through a data pin used to input to the buffer memory, or if the program information is not input, the data element is output from the buffer memory during the normal mode. Applying to the programmable buffer chip a direction signal indicating whether to perform via a data pin used for outputting, the direction signal corresponding to a control pin of the non-programmable basic buffer chip, Non Programmer
Being applied to the programmable buffer chip through a pin that has no functional meaning during reset of the blue basic buffer chip, wherein during the input step, the program information is input via a pin indicated by the direction signal. Features method. 5. Inputting information to a programmable buffer chip for determining a buffer status state, which is monitored by at least one buffer status pin during a period disguised as an extension period for a reset extension operation, A method for achieving compatibility between said programmable buffer chip having the same number of I / O pins and a non-programmable basic buffer chip, comprising:
The non-programmable basic buffer chip is operable to enter a reset mode for resetting in response to a reset signal, and then to exit reset mode in response to a reset release signal. A reset signal is applied to the buffer chip to reset the programmable buffer chip to a predetermined initial state .
Step of setting a reset period between the reset mode, for an extended period exceeding the predetermined reset time period, the flop
The programmable buffer chip is set to a normal mode to start a non-reset buffer operation, to stop applying a reset release signal to the programmable buffer chip, and to extend program input to the programmable buffer chip. Forming a spoofed time window as the reset period, wherein during the spoofed reset period, when the programmable buffer chip is in the normal mode, a buffer status state monitored by the at least one buffer status pin is set. Inputting program information for determining a selection to the programmable buffer chip; and, after the inputting step, applying the reset release signal to the programmable buffer chip, thereby The step of logging llama Bull buffer chip to the normal mode, consists, thereby, provide compatibility with the non-programmable basic buffer chip to the programmable buffer chip, said program information, the non-programmable BASIC <br/> Kubaffa The buffer status state monitored by the at least one buffer status pin of the chip includes a specific indication of whether it is the same or different from that monitored by a respective buffer status pin of the programmable buffer chip. The method characterized by that.