JP2910055B2 - Microprocessor system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of processing after reset of a microprocessor system.

<Related Art> Generally, a microprocessor fetches several bytes such as a program counter initial value (reset vector) as a process after reset. At this time, a specific value is assigned to the address issued by the microprocessor, and the reset vector area specified by this specific address must use a non-volatile memory (ROM) to hold data when power is turned off. No.

For example, a 68000-based microprocessor performs an initialization process after the
00,000002,000004,000006 are continuously transmitted, and a predetermined process is executed by accessing a corresponding location (reset vector area) of the ROM.

<Problems to be Solved by the Invention> By the way, for the sake of system construction, for example, as shown in FIG. 4, the address space 000000 to 200,000 is a readable / writable RAM area, and the address space F80000 to FFFFFF is used.
May be required as a ROM area.

In such a case, for example, a decoding circuit as shown in FIG. 5 is configured and installed in the microprocessor to access the memory area.

That is, address lines A23 to A4 from a microprocessor (not shown) are given to gates g1 to g4, and address lines A23 to A1
9 is given to gate g5. The outputs of the gates g1 to g4 and the address line A3 are input to the gate g6, and the outputs of the gates g5 and g6 are applied to the gate g7. The output of the gate g6 and the address lines A23 to A21 are supplied to the gate g8.

By such a decoding circuit, after reset, the address from the microprocessor is 000000,000002,000004,00000.
When 6 is transmitted, the output of the gate g8 for giving an address to the RAM is inhibited by the gates g1 to g4 and g6, and the ROM selection signal is output via the gate g7. This allows the microprocessor to access the reset vector area of the ROM and perform a predetermined initialization process.

However, the decoding circuit shown in FIG. 5 cannot access the ROM unless several stages of gates are provided, and thus has a disadvantage that the decoding time is long and hinders the speeding up of the system.

Further, a RAM selection signal may be output before a ROM selection signal is output due to a difference in signal passing speed of each gate, which may cause a malfunction in the system. Therefore, it is necessary to delay RAM access.

As described above, the conventional method has a problem in that it takes time to determine whether or not the area is the reset vector area during decoding.

The present invention aims to solve such a problem,
An object of the present invention is to eliminate unnecessary processing time when a high-speed access to a memory area is realized in a microprocessor system.

<Means for Solving the Problems> The present invention for solving the above problems focuses on the number of address occurrences at this time without directly decoding an address generated by a microprocessor when a reset signal is given. The configuration is as follows.

That is, the present invention provides a read / write RAM area,
In a microprocessor system having a non-volatile memory having an address space different from that of the RAM area and transmitting a reset vector area designation address for initialization processing when a reset signal is applied, a reset signal is applied. A counter that counts the number of addresses sent by the microprocessor at the time of access, and, when the reset signal is applied, sends a selection signal to the nonvolatile memory to access the RAM area until the counter counts up. And a determination unit for prohibiting the operation of the microprocessor system.

<Operation> The microprocessor system of the present invention operates as follows.

Upon receiving the reset signal, the microprocessor outputs an address signal specifying the reset vector, and outputs an address signal validating the address signal.
Output strobe signal. In response to the reset signal, the determination unit immediately outputs a ROM selection signal and prohibits access to the RAM. On the other hand, the counter outputs a count-up signal to the determination unit when the number of occurrences of the address known in advance, that is, the address strobe signal and the number of occurrences are counted as a predetermined number, whereby the determination unit accesses the prohibited RAM. To release.

<Embodiment> FIG. 1 is an overall configuration diagram of a microprocessor according to the present invention.

In this figure, 1 is a microprocessor such as 68000, AB is an address bus, DB is a data bus, CB is a control bus, 2 is a nonvolatile memory (ROM), and 3 is a decoder which is a core of the present invention. . In addition, a RAM area and the like are provided in addition to the above.

The decoder 3 is supplied with a reset signal, an address strobe signal, and the like from the upper bit group on the address bus AB and the control bus CB, and supplies a ROM selection signal to the ROM 2.

The ROM 2 is supplied with a ROM selection signal from the lower-order bit group on the address bus AB and the control bus CB, and outputs data to the data bus DB.

The outline of the operation of the microprocessor system of the present invention is as shown in the flowchart of FIG.

FIG. 2 shows the operation when a reset signal is given to the system of FIG.

When the reset signal is given, the decoder 3 sends a ROM selection signal to the control bus CB. This allows
The ROM 2 is accessed by the reset vector area designation address sent from the microprocessor 1 to execute initialization processing.

On the other hand, a counter provided inside the decoder 3 counts an address strobe signal sent from the microprocessor 1 a predetermined number of times as the number of times of address generation.
This address strobe signal is a signal for validating the reset vector area designation address signal output from the microprocessor 1 by the reset signal, and the microprocessor 1 is in the process of being initialized until it counts a predetermined number of times.

When using 68000 as microprocessor 1,
As described above, the reset vector area designation address is
000000,000002,000004,000006, and the address strobe signal is transmitted four times in response to these address signals.

When the counter has counted up, the microprocessor 1 regards that the initialization processing has been completed, and the decoder 3
The normal access to (not shown) is released, and decoding according to the system is started.

Thereafter, the system performs a normal process according to the address sent from the microprocessor 1 and monitors whether or not a reset signal has been given.

The above is the outline of the operation of the microprocessor system of the present invention. Next, FIG. 3 shows the internal configuration of the decoder 3, and the operation will be described in detail.

The decoder 3 roughly includes a count circuit 31, a count determination circuit 32, and a decode circuit 33.

The count circuit 31 counts the address strobe signal ▼ sent from the microprocessor 1 in response to the reset signal ▼.
The count determination circuit 32 outputs the reset signal ▲
Or a D flip-flop (LS74) for inverting its output Q by the count circuit 31.

The decode circuit 33 includes gates g331 and A23 for inputting A23 to A19 among the address lines A23 to A1 of the address bus AB.
Gate g for inputting ~ A21 and the output of the count determination circuit 32
332, the output of gate g331 and count determination circuit 32
OR gate g333 for inputting the Q output of

In such a decoder 3, the reset signal ▲
When ▼ is given, the following operation is performed.

The reset signal ▲ ▼ causes the count determination circuit 32 to invert its output Q, close the gate g332, and
The access to the area, that is, the decoding function is stopped. On the other hand, the gate g333 is opened and a ROM selection signal is supplied to ROM2.

This causes the microprocessor 1 to send out
Address 000000,00000 specifying the reset vector area
2,000004.000006 is given directly to ROM2, and the reset vector stored at the address F80000, F80002, F80004, F80006 of ROM2 is fetched.

During this time, the microprocessor 1 sends the address to be sent.
000000,000002,000004,000006 Each of which outputs an address strobe signal ▲ ▼ for validating, and the counting circuit 31 counts the number of occurrences of the address strobe signal ▲ ▼.

The count circuit 31 outputs the address strobe signal ▲
A count-up signal QC is output when ▼ is counted four times. As a result, the outputs Q, Q
Is inverted, and the gate g332 is opened.

Then, by opening the gate g332, the RAM area can be accessed, and normal processing according to the system starts.

As described above, when the reset signal ▲ ▼ is applied, the ROM selection signal is immediately output to select ROM2, and the reset vector area designation address (000000,000002,000004,000) output from the microprocessor 1 is selected.
006) can be given to the ROM 2 to execute the initialization processing.

The number of occurrences of the reset vector area designation address, that is, the number of occurrences of the address strobe signal ▼ is known in advance, and if this number of occurrences is counted, the access is switched to the normal access.

<Effect of the Invention> As described above, according to the microprocessor system of the present invention, the number of gate stages from the given address to the output of the ROM selection signal or the RAM selection signal is reduced, and the high-speed access of the memory is achieved. Becomes possible. In addition, since the decoding function is stopped briefly during several accesses, the circuit configuration itself is simplified.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of a microprocessor of the present invention, FIG. 2 is a flowchart showing the operation of the system of the present invention,
FIG. 3 is an internal configuration diagram of the decoder 3 in the system of the present invention,
FIG. 4 is a diagram showing an address space of a memory area in the system of the present invention, and FIG. 5 is a diagram showing a detailed configuration of a decoder in the conventional system. 1 ... Microprocessor, 2 ... ROM, 3 ... Decoder, 31 ... Count circuit, 32 ... Count determination circuit, 33 ... Decode circuit, g331, g332 ... Gate, g323 ... OR gate, g1 , g2, g3, g4, g5, g6, g7, g8 ... gate, AB ... address bus, DB ... data bus, CB ... control bus.

Claims (1)

(57) [Claims] A readable / writable RAM area and this RAM
It has a non-volatile memory with a different address space from the area,
In a microprocessor system for sending a reset vector area designation address for initialization processing when a reset signal is given, a counter for counting the number of addresses sent by the microprocessor when a reset signal is given A microprocessor for transmitting a selection signal to the non-volatile memory when the reset signal is supplied, and prohibiting access to the RAM area until the counter counts up. ·system.