JPH07210492A - Slave board recognizing device - Google Patents

Abstract

PURPOSE:To provide a slave board recognizing device capable of changing and adding the kind of the slave board without changing H/W. CONSTITUTION:The device compares slot ID outputted from a slot 10 output control part 14 and the contents of slot number data 20 held by the pertient slot in advance, sends a command when both of them are coincident, and sends the contents of characteristic board ID and slot number data 20 to CPU 12 by this command.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a slave board recognition device for recognizing the existence and type of a slave board as one component of a microcomputer system.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a schematic configuration of a conventional slave board recognition apparatus disclosed in, for example, Japanese Patent Laid-Open No. 1-315855. In the figure, 1 is a host CPU which sends an address ADDRESS-1 for accessing an identification code register of a specific slave board, which will be described later, to the system bus 2 via the data bus 1a, and 3 is an address ADDRESS-1 sent from this host CPU.
, An ACK signal generator for generating a response signal ACK and transmitting it to the host CPU 1, and a response signal generator 5 comprising these decoder 3 and ACK signal generator 4, Reference numeral 6 is a CPU board on which the response signal generator 5 and the host CPU 1 are mounted.

Reference numeral 7 is an input / output device connected to the system bus 2 via the data bus 7a, and 8 is a host CP via the data bus 1b, the system bus 2 and the address bus 7b.
A decoder 9 which decodes and outputs ADDRESS-1 sent from U1, 9 is chip-selected by the output CS of this decoder 8 and reads an identification code for identifying itself stored in advance, and the data bus 7a, system bus 2 and the data bus 1a, the host CPU 1
ID register 10 to be sent to the identification code register 10 composed of these decoder 8 and ID register 9
Reference numeral 1 denotes a slave board on which the identification code register 10 and the input / output device 7 are mounted, and a plurality of slave boards are connected to the system bus 2.

In the conventional slave board recognition device having the above-mentioned structure, the identification code stored in the ID register 9 in advance is specified by the address ADDRESS-1 and accessed by the specific slave board 11.
Is not connected to the system bus 2 and the identification code data is not present in the system bus 2, the system bus 2 is terminated with a constant voltage, for example, 3.5 volts (corresponding to level “H”), If it is a so-called Low-Active bus logic that recognizes that data exists when the level is "L", the host CPU 1 can read the data as "00" (in the case of the opposite High-Active, it becomes "FF").

Therefore, if the specific slave board 2 is set to be identified by an appropriate value other than the data "00", for example, "01", the host CPU 1 can make the data bus 7
If the identification code data sent via the a, the system bus 2 and the data bus 1a is "01", it is recognized that the specific slave board 11 exists, and the data is "0".
If it is 0 ", it can be recognized that the specific slave board 11 does not exist.

Thus, the host C on the CPU board 6
PU1 is an address AD for reading the identification code from the identification code register 10 on the specific slave board 11.
The DRESS-1 is replaced by the response signal generator 5 on the CPU board 6 and the identification code register 1 on the slave board 11.
0, receives the response signal ACK generated by being decoded in the response signal generation unit 5 of the own board, receives the data read from the ID register 9 of the identification code register 10 of the specific slave board 11, and receives the data. If the received data is the specific data “00” (or “FF”), it is recognized that the specific slave board 11 does not exist, and the received data has an identification code other than the specific data “00” (or “FF”). If the data is "01", it is recognized that the specific slave board 11 exists, and the identification code data is "
The type is identified by "01".

[0007]

Since the conventional slave board recognition device is constructed as described above, in order to recognize the slave board 11, a decoder 8 corresponding to a specific address is required, and Slave board 11
When changing or adding the above, there is a problem that the H / W of the CPU board 6 must be changed.

The present invention has been made in order to solve the above problems, and it is not necessary for the CPU board to have an address decoder corresponding to a specific slave board.
Moreover, it is an object of the present invention to provide a slave board recognition device capable of recognizing the existence and type of a slave board without changing the H / W when changing or adding a board.

[0009]

A slave board recognition device according to claim 1 of the present invention includes a host CPU connected to a system bus via a data bus and sequentially sending destination commands via a local bus during a recognition operation. , A CPU board which is connected to the host CPU via a local bus and sequentially sends out slot IDs corresponding to respective destination slots according to respective destination commands to the system bus via the address control signal bus. , And a slot ID comparator which compares each slot ID introduced from the system bus via the address control signal bus with the slot number data previously held in the slot and sends a command when the two match. When,
It has a plurality of slave boards, each of which is composed of a board ID register that outputs the unique board ID and slot number data that are held in advance by the instruction of the slot ID comparator to the system bus via the data bus, and that is housed in each slot. It is a thing.

The slave board recognition apparatus according to claim 2 of the present invention is a host CPU which is connected to a system bus via a data bus and sequentially sends commands corresponding to the number of slots via an address control signal bus during a recognition operation. And a daisy chain signal generation unit that is connected to the host CPU via the address control signal bus and sequentially generates a daisy chain signal according to each command and sends out the daisy chain signal via a unique signal line, and a daisy chain signal generation unit The daisy chain controller is connected in a daisy chain form via a unique signal line and sends a command when the daisy chain signal is input, and the daisy chain signal that is subsequently input is transferred to the lower order sequentially and the command of the daisy chain controller. Unique board I pre-owned by
A board ID register for outputting D to the system bus via the data bus is provided, and a plurality of slave boards housed in the respective slots are provided.

According to a third aspect of the present invention, in the slave board recognition device, the daisy chain signal generated by the daisy chain signal generating section in the second aspect is excited by repeating "H" and "L" at a constant cycle. It is a signal.

According to a fourth aspect of the present invention, a slave board recognition device is a host CPU which is connected to a system bus via a data bus and sequentially outputs commands for the number of slots via an address control signal bus during a recognition operation. And a board identifying signal generator connected to the host CPU via the address control signal bus and sequentially generating board identifying signals according to each command and sending the board identifying signals through the respective unique signal lines, and the unique signal lines. A board identification signal receiver connected to the board identification signal generator through the board and sending a command when the board identification signal is input, and a unique board ID stored in advance by the command of the board identification signal receiver.
I to output the data to the system bus via the data bus
It is provided with a plurality of slave boards each of which is composed of a D register and is housed in each slot.

In the slave board recognition device according to a fifth aspect of the present invention, the board identification signal generated by the board identification signal generation section in the fourth aspect is a constant cycle.
This is an excitation signal in which H "and" L "are repeated.

A slave board recognition device according to a sixth aspect of the present invention is a host CPU which continuously accesses a predetermined address space and issues an address response signal read command after the completion of all accesses. CPU boards, a plurality of slave boards that are housed in each address space and generate address response signals when applicable to an access from the host CPU, and monitor the presence or absence of address response signals from each slave board, If the address response signal is not detected within the time, the response signal is generated and the host CPU of the CPU board
To the host and the response signal generation monitor that stores the response address in the address memory when the address response signal is detected, and releases the address memory by the response signal read command from the host CPU It is provided with an address check board consisting of a memory decoder for sending to the CPU.

[0015]

The slot ID comparator of the slave boat recognition apparatus according to claim 1 of the present invention compares the slot ID output from the slot ID output control unit with the slot number data previously held in the slot,
If the two match, a command is sent, and the board ID register sends a unique board ID and slot number data to the host CPU according to the command from the slot ID comparator.

Further, when the daisy chain control unit of the slave board recognition device according to the second aspect of the present invention inputs the daisy chain signal output from the daisy chain signal generation unit, the daisy chain control unit sends a command and the daisy signal to be subsequently input. Chain signals are transferred to the lower order,
The board ID register sends a unique board ID to the host CPU in response to a command from the daisy chain controller.

Further, the daisy chain control unit of the slave board recognition device according to the third aspect of the present invention has a constant cycle output from the daisy chain signal generation unit.
When a daisy chain signal consisting of an excitation signal that repeats H "and" L "is input, the command is sent and the daisy chain signals that are input subsequently are sequentially transferred to the lower order, and the board ID register controls this daisy chain. A unique board ID is issued to the host CPU by a command from the department
Send to.

Further, the board identification signal receiving section of the slave board identification device according to claim 4 of the present invention sends a command when the board identification signal output from the board identification signal generating section is inputted, and the board ID register is , A unique board ID by command from this board identification signal receiver
To the host CPU.

Further, the board identification signal receiving section of the slave board identification device according to claim 5 of the present invention is a board which is an excitation signal output from the board identification signal generating section and repeating "H" and "L" at a constant cycle. When the identification signal is input, a command is sent out, and the board ID register sends a unique board ID to the host CPU according to the command from the board identification signal receiving section.

According to a sixth aspect of the present invention, the response signal generation monitoring section of the slave board recognition device is a host CPU.
The presence or absence of the address response signal from the slave board that is generated in the case of access from the slave is monitored, and if this address response signal is not detected within a certain period of time, a response signal is generated and sent to the host CPU. In addition, when the address response signal is detected, the response address is stored in the address memory, and the address check board releases the address memory by the response signal read command from the host CPU and stores the stored response address. Send to host CPU.

[0021]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a block diagram showing a configuration of a slave board recognition device according to a first embodiment of the present invention. In the figure, 12 is a host CPU that performs overall control of the entire system.
Then, the data bus 12a is connected to the system bus 13, and the local bus 12b is connected to a slot ID output control unit described later. Reference numeral 14 is a slot ID output control unit for controlling the output of a slot ID for recognizing a slave board, which will be described later.
It is connected to the address control signal bus 17 and the system bus 13 via 6.

Reference numeral 18 denotes a CPU board on which the host CPU 12 and the slot ID output control section 14 are mounted, and 19
Is a plurality of slave boards housed in each slot, 20 is provided for each slot, slot number data holding a slot number unique to each slave board 19 housed, 21 is a system bus via a data bus 21a An input / output device 22 connected to the slot 13 is connected to the system bus 13 via the address control signal bus 22a, and is connected to the slot number data 20 respectively, and is introduced into the slot I via the address control signal bus 22a.
The slot ID from the D output control unit 14 is compared with the slot number held in the slot number data 20, and if they match, a slot ID comparator for sending a command, 23 is held in advance by a command from this comparator 22. Board I for outputting the unique board ID stored therein and the unique slot number held in the slot number data 20 to the system bus 13 via the data bus 21a.
It is a D register.

Next, the operation of the slave board recognizing device according to the first embodiment constructed as described above will be described. For example, when it is necessary to recognize the slave board 19 existing in the system at the time of power-on, the host CPU 12 first sends the slot I via the local bus 12a.
The D output control unit 14 has a slave board 19 in the system.
Slot ID for the first of the slots
Send a destination command to output. The slot ID output control unit 14 receiving this destination command, the address buffer 15,
16 to control the slot I corresponding to the first slot
D via the address control signal bus 17 to the system bus 1
Output to 3.

When the slave board 19 is present in the first slot, the slot ID comparator 22 mounted on the slave board 19 is a slot input via the system bus 13 and the address control signal bus 22a. The ID is compared with the unique slot number held in the slot number data 20, and if the contents match, a command is sent out. Next, the board ID register that has received this command has a unique board ID that indicates the type of the slave board 19 that it has in advance, and the like.
The unique slot number held in the slot number data 20 and the system bus 13 are transmitted via the data bus 21a.
Output to.

The board ID and slot number output in this manner are input to the host CPU 12 via the system bus 13 and the data bus 12a, and the host C
The PU 12 determines whether the input slot number corresponds to the slot designated by its own destination command, and if they match, interprets the board ID to recognize the existence and type of the slave board 19. . In addition, if the judgment results are inconsistent, it is judged that a temporary malfunction or failure due to noise or the like has occurred, and recovery processing such as retry operation, or if there is a disagreement in retrying, an error is generated. Execute the process.

On the other hand, the slave board 1 is placed in the first slot.
When 9 is not present, the board ID and slot number are not returned as a matter of course, so that it is recognized that the slave board 19 is not present in the first slot. Thereafter, the host CPU 12 sequentially issues destination commands for the second and subsequent slots to the slot ID output control unit 14 to recognize the existence and types of all slave boards 19.

As described above, according to the first embodiment, the slot ID is compared with the unique slot number held for each slot in which each slave board 19 is accommodated, and the slot number in case of coincidence and the slot number The unique board ID held by the slave board 19 is used by the host CPU 12
It is possible to change or add the type of the slave board 19 without changing the H / W. Furthermore, the host CP
In U12, it is determined whether the slot number that can be known corresponds to the slot specified by the destination command of itself, and if it is determined that the slot number does not correspond, error processing is executed. It is possible to avoid the occurrence of a system down or the like due to the erroneous recognition of the slave board.

Example 2. Second Embodiment FIG. 2 is a block diagram showing the configuration of a slave board recognition device according to a second embodiment of the present invention. In the figure, 24 is a host CPU that is connected to the system bus 13 via a data bus 24a and that controls the entire system, and 25 is a daisy chain signal generation unit that is connected to the host CPU 24 via an address control signal bus 25a. Is a CPU board on which the host CPU 24 and the daisy chain signal generator 25 are mounted.

27 is an input / output device connected to the system bus 13 via a data bus 27a and an address control signal bus 27b, and 28 is a daisy chain connected to a daisy chain signal generator 25 via a unique signal line 29. The controller 30 has a unique board ID and is connected to the system bus 13 via the daisy chain controller 28 and the data bus 27a, respectively, and 31 is the input / output device 27 and the daisy chain controller. In a plurality of slave boards each having a board 28 and a board ID register 30, each daisy chain controller 28 is connected by a unique signal line 29.

Next, the operation of the slave board recognizing device according to the second embodiment having the above configuration will be described. First, the host CPU 24 uses the address control signal bus 2
The daisy chain signal generator 25 is instructed to output the daisy chain signal via 5a.
When receiving this command, the daisy chain signal generator 25
Is a daisy chain control unit 28 of the slave board 31 housed in the first slot via a unique signal line 29.
On the other hand, a daisy chain signal that is an excitation signal that repeats a constant cycle "H" and "L" is transmitted. Next, when the excitation signal that repeats the constant cycles "H" and "L" is input, the daisy chain control unit 28 instructs the board ID register 30 to output the board ID.

Upon receiving this instruction, the board ID register 3
At 0, a unique board ID indicating the type of the slave board 31 that the user owns in advance is output to the system bus 13 via the data bus 27a. Then, the daisy chain control unit 28 stores that the output of the board ID is completed, the daisy chain signal sent next is transferred to the daisy chain control unit 28 of the next slave board 31, and so on. When the output of its own board ID is completed, each daisy chain control unit 28 sequentially inputs the daisy chain signals subsequently input to the daisy chain control units 28 of the lower slave boards 31.
Transfer to. Then, the host CPU recognizes the existence and type of each slave board 31 by detecting each unique board ID sequentially output from the board ID register 30 of each slave board 31 as described above.

As described above, according to the second embodiment, the daisy chain signal is transmitted from the daisy chain signal generating section 25 through the unique signal line 29 as many times as the number of slots in which the slave board 31 is accommodated. However, since the host CPU 24 can know each unique board ID that is sequentially returned from the board ID register 30 of each slave board 31 in response to the daisy chain signal, the type of the slave board 31 can be changed. Changes and additions are possible without changing the H / W, and since the excitation signal is used for the daisy chain signal, this will occur if the "L" or "H" is fixed due to a failure. Therefore, it is possible to prevent the system from going down.

Example 3. FIG. 3 is a block diagram showing the configuration of a slave board recognition device according to the third embodiment of the present invention. In the figure, 32 is a host CPU that is connected to the system bus 13 through a data bus 32a, and that controls the entire system, 33 is a board identification signal generation unit that is connected to the host CPU 32 through an address control signal bus 33a, 34 Is a CPU board on which the host CPU 32 and the board identification signal generator 33 are mounted.

Reference numeral 35 is an input / output device connected to the system bus 13 via a data bus 35a and an address control signal bus 35b, and 36 is a board identification connected to a board identification signal generator 33 via a unique signal line 37. The signal receiving unit 38 has a unique board ID, and is connected to the system bus 13 via the board identification signal receiving unit 36 and the data bus 35a.
Reference numeral 9 denotes these input / output device 35 and board identification signal receiver 36.
In a plurality of slave boards each having a board ID register 38 and a board ID register 38, each board identification signal receiving section 36 is connected to the board identification signal generating section 33 via a different unique signal line 37.

Next, the operation of the slave board recognizing device according to the third embodiment constructed as described above will be described. First, the host CPU 32 uses the address control signal bus 3
The board identification signal generator 33 is instructed via 3a to output the board identification signal to the slave board 39 housed in the first slot. Upon receiving this command, the board identification signal generation unit 33 generates a board identification signal and sends it to the board identification signal reception unit 36 of the slave board 39 via the unique signal line 37 at a constant cycle.
A board identification signal which is an excitation signal for repeating H "and" L "is transmitted.

Next, when a board identification signal, which is an excitation signal, is input, the board identification signal receiving section 36 determines the board ID.
The register 38 is instructed to output the board ID. In response to this instruction, the board ID register 38 outputs a unique board ID, which indicates the type of the slave board 39, which it holds in advance, to the system bus 13 via the data bus 35a. Then, the host CPU 32 recognizes the existence and type of the first slave board 39 by detecting the board ID sent from the board ID register 38. Similarly, the board identification signal generator 33 sequentially sends the board identification signals to the slave boards 39 via the respective signal lines 37,
The board IDs returned from the board ID registers 38 are detected by the host CPU 32, and the existence and type of each slave board 39 are sequentially recognized.

As described above, according to the third embodiment, the unique signal lines 3 from the board identification signal generator 33 are different from each other.
The board identification signal is sequentially sent to the board identification signal receiving unit 36 of each slave board via the board 7 so that the host CPU 32 can know each unique board ID sequentially returned from each board ID register 38. Therefore, it is possible to change or add the type of the slave board 39 without changing the H / W. Further, since the excitation signal is used as the board identification signal, "L" or "" is caused by a failure or the like.
This can be determined when the fixed state of "H" is reached, and system down or the like can be prevented.

Example 4. Fourth Embodiment FIG. 4 is a block diagram showing the configuration of a slave board recognition device according to a fourth embodiment of the present invention. In the figure, reference numeral 40 denotes a host CPU 4 mounted on a CPU board 41 and connected to a system bus 13 via a data bus 40a and an address control signal bus 40b.
Reference numeral 2 is an input / output device mounted on each of the plurality of slave boards 43 and connected to the system bus 13 via the data bus 42a and the address control signal bus 42b.

Reference numeral 44 is a response signal from the input / output device 42 of each slave board 43 in response to access from the host CPU 40 existing on the system bus 13, and 45 is a response signal generation for monitoring the presence or absence of the response signal 44 on the system bus 13. The monitoring unit 46 is an address storage unit, and via the memory decoder 46a connected to the system bus 13 and the response signal generation monitoring unit 45 via the address control signal bus 47, and the local data bus 48, the respective buffers 49, 50. The address memory 46b is connected to the system bus 13 via the data bus 51 and the address control signal bus 47 under the control of. The response signal generation monitoring unit 45 and the address storage unit 46 are mounted on the address check board 52.

Next, the operation of the slave board recognizing device according to the fourth embodiment having the above configuration will be described. First, the host CPU 40 of the CPU board 41 continuously accesses a predetermined address space. At this time, the response signal generation monitor 45 of the address check board 52 monitors the presence or absence of the response signal 44 on the system bus 13. Then, when no response signal 44 is generated from any of the slave boards 43 for this access even after a lapse of a predetermined time, the response signal 44 is generated and output to the CPU board 41.

When the occurrence of the response signal 44 is detected within a predetermined time, the buffer 50 is controlled and opened, and the response signal 44 is detected by the address memory 46b via the address control signal bus 47 and the local data bus 48. Response signal 44
Memorize the address of. On the other hand, when the host CPU 40 of the CPU board 41 completes the continuous access to the predetermined address space, the address control signal bus 40
The address for reading the address memory 46b via b is output to the system bus 13.

This address is the system bus 13
When input from the address control signal bus 47 via the address decoder 46a, the memory decoder 46a detects this and gives a data output command to the address memory 46b and controls and releases the buffer 49 to release the address memory 46b.
The contents inside, that is, the response signal generation address is output to the system bus 13 via the data bus 51. Host CP
The U40 recognizes the address space in which the slave board 2 exists by searching the response signal generation address output in this way, and accesses the address space to further determine the type of the slave board 43. , Recognize.

As described above, according to the fourth embodiment, since the slave board 2 is recognized by the dedicated circuit mounted on the address check board 52, the type of the slave board 43 can be changed or added by H / H. This is possible without changing W, and it is not necessary to mount a dedicated circuit for recognizing the board on the CPU board 41 or each slave board 43.

[0044]

As described above, according to the first aspect of the present invention, the host CPU connected to the system bus through the data bus and sequentially sending the destination command through the local bus during the recognition operation, and the local bus. Via host CPU
Connected to the CPU board, which is a slot ID output control unit for sequentially sending the slot IDs corresponding to the respective slots of the respective destinations to the system bus via the address control signal bus, and the address control from the system bus. Each slot ID introduced via the signal bus
And the slot number data previously held in the relevant slot are compared, and if the two match, a slot ID comparator that sends a command, and a unique board ID and slot previously held by the command of the slot ID comparator It has a plurality of slave boards each consisting of a board ID register that outputs number data to the system bus via the data bus, and each slave board is stored in each slot, so you can change the type of slave board without changing H / W. A slave board recognition device that can be added can be provided.

According to the second aspect of the present invention, the host CPU is connected to the system bus through the data bus and sequentially outputs the command for the number of slots through the address control signal bus during the recognition operation, and the address control. A CPU board which is connected to a host CPU via a signal bus and sequentially generates a daisy chain signal according to each command and sends out the daisy chain signal via a unique signal line, and a unique signal line for the daisy chain signal generating unit Are connected in a daisy chain via the daisy chain signal, and when a daisy chain signal is input, a command is sent and the daisy chain signals that are input subsequently are sequentially transferred to the lower order. The unique board ID that is present on the system bus via the data bus. Since it has a plurality of slave boards each consisting of a board ID register and stored in each slot, a slave board recognition device that can change or add the type of slave board without changing the H / W is provided. Can be provided.

According to a third aspect of the present invention, the daisy chain signal according to the second aspect is "at a constant cycle".
Since the excitation signal repeats H "and" L ", the type of slave board can be changed or added without changing H / W, and failure can be easily determined. A slave board recognition device can be provided.

According to a fourth aspect of the present invention, the host CPU is connected to the system bus via the data bus and sequentially outputs the command for the number of slots via the address control signal bus during the recognition operation, and the address control. A CPU board which is connected to the host CPU via a signal bus and which sequentially generates a board identification signal according to each command and sends out the board identification signal via each unique signal line; and
A board identification signal receiving unit connected to the board identification signal generating unit via a unique signal line and transmitting a command when the board identification signal is input, and a unique board ID stored in advance according to a command from the board identification signal receiving unit. It has a plurality of slave boards each consisting of a board ID register that outputs to the system bus via the bus, and each slave board is stored in each slot, so you can change or add the type of slave board without changing the H / W. It is possible to provide a slave board recognition device capable of performing the above.

According to a fifth aspect of the present invention, the board identification signal in the fourth aspect is changed to "H", "at a constant cycle".
Since the excitation signal repeats L ", the type of slave board can be changed or added without changing H / W, and a slave board recognition device that can easily determine a failure etc. Can be provided.

Further, according to claim 6 of the present invention, each CPU board which is a host CPU for continuously accessing a predetermined address space and for issuing an address response signal read command after the completion of all accesses, Multiple slave boards, each of which is stored in the address space and generates an address response signal when the access from the host CPU is applicable, and the presence or absence of the address response signal from each slave board is monitored, and the address is addressed within a fixed time. When the response signal is not detected, the response signal is generated and sent to the host CPU of the CPU board, and when the address response signal is detected, the response signal generation monitoring unit that stores the response address in the address memory, and the host CP.
Since an address check board consisting of a memory decoder that releases the address memory by sending a response signal read command from U and sends the stored response address to the host CPU is provided, the slave board type can be changed without changing the H / W. It is possible to provide a slave board recognition device capable of changing or adding.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a slave board recognition device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a slave board recognition device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a slave board recognition device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a slave board recognition device according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional slave board recognition device.

[Explanation of symbols]

12, 24, 32, 40 Host CPUs 12a, 21a, 24a, 27a, 32a, 35a, 40a, 42a, 51 Data bus 13 System bus 14 Slot ID output controller 15, 16, 49, 50 Buffer 17, 22a, 25a , 27b, 33a, 35b, 40b, 42b, 47 Address control signal bus 18, 26, 34, 41 CPU board 19, 31, 39, 43 Slave board 20 Slot number data 21, 27, 35, 42 I / O device 22 slots ID comparator 23, 30, 38 Board ID register 25 Daisy chain signal generation unit 28 Daisy chain signal control unit 29, 37 Unique signal line 33 Board identification signal generation unit 36 Board identification signal reception unit 44 Response signal 45 Response signal generation monitoring unit 46 address storage unit 46a memory decoder 46b address memory 48 local data bus 52 Address check board

Claims (6)

[Claims] 1. A host CPU connected to a system bus via a data bus and sequentially sending destination commands via a local bus during a recognition operation; and a host CPU connected to the host CPU via the local bus according to the destination commands. A CPU board comprising a slot ID output control unit for sequentially sending out a slot ID corresponding to each slot of each destination to the system bus via an address control signal bus, and from the system bus via an address control signal bus. Each slot ID to be introduced is compared with the slot number data held in advance in the slot concerned, and if the two match, a slot ID comparator for sending a command, and a slot ID comparator for holding the command in advance The unique board ID and slot number data above. It has a plurality of slave boards each consisting of a board ID register for outputting to the system bus via a bus and housed in each of the slots, and the existence and type of each slave board depending on the presence or absence and the contents of the output of the board ID register. A slave board recognition device characterized in that it recognizes. 2. A host CPU connected to a system bus via a data bus and sequentially transmitting commands corresponding to the number of slots via an address control signal bus during a recognition operation, and to the host CPU via the address control signal bus. A CPU board, which is connected to a daisy chain signal generation unit that sequentially generates daisy chain signals according to the above-mentioned commands and sends out the daisy chain signals through a unique signal line, and the daisy chain signal generation unit through the unique signal line. When the daisy chain signal is connected in a circular pattern, a command is transmitted and the daisy chain signal that is subsequently input is stored in advance by a daisy chain control unit that sequentially transfers to the lower order and a command from the daisy chain control unit. Unique board ID via the data bus to the system bus A plurality of slave boards each consisting of a board ID register for outputting to each slot and housed in each of the slots, and the existence and type of each slave board are recognized by the presence or absence of the output of the board ID register. A slave board recognition device. 3. The daisy chain signal generated by the daisy chain signal generator is "H", "L" at a constant cycle.
3. The slave board recognition device according to claim 2, wherein the slave board recognition device is an excitation signal that repeats. 4. A host CPU connected to a system bus via a data bus and sequentially sending commands for the number of slots via an address control signal bus during a recognition operation, and to the host CPU via the address control signal bus. A CPU board comprising a board identification signal generation unit which is connected and sequentially generates a board identification signal according to each of the above-mentioned commands and sends it out through each unique signal line, and to the above-mentioned board identification signal generation unit through the above-mentioned unique signal line. A board identification signal receiving unit that sends a command when connected and inputs the board identification signal, and outputs a unique board ID stored in advance by a command from the board identification signal receiving unit to the system bus via a data bus It has a plurality of slave boards each consisting of a board ID register and stored in each of the above slots. A slave board recognition device characterized in that the existence and type of each slave board are recognized by the presence or absence of the output of the ID register and the contents. 5. The slave board recognition device according to claim 4, wherein the board identification signal generated by the board identification signal generation unit is an excitation signal in which "H" and "L" are repeated in a constant cycle. 6. A C, which is a host CPU, which continuously accesses a predetermined address space and issues an address response signal read command after the completion of all accesses.
PU boards, a plurality of slave boards housed in each of the address spaces and generating address response signals when corresponding to the access from the host CPU, and monitoring for presence or absence of address response signals from the slave boards If the address response signal is not detected within a fixed time, a response signal is generated and sent to the host CPU of the CPU board, and if the address response signal is detected, a response address is stored in the address memory. Signal generation monitoring unit and the host CPU
In response to a response signal read command from the host, the address memory is released and the stored response address is stored in the host C.
Slave board recognition characterized by comprising an address check board consisting of a memory decoder for sending to the PU, and recognizing the address space in which the slave boards exist from the response addresses sent from the address memory apparatus.