JPH0720811A - Horizontal afc circuit - Google Patents

Horizontal afc circuit

Info

Publication number
JPH0720811A
JPH0720811A JP15957693A JP15957693A JPH0720811A JP H0720811 A JPH0720811 A JP H0720811A JP 15957693 A JP15957693 A JP 15957693A JP 15957693 A JP15957693 A JP 15957693A JP H0720811 A JPH0720811 A JP H0720811A
Authority
JP
Japan
Prior art keywords
circuit
horizontal
pulse
output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15957693A
Other languages
Japanese (ja)
Inventor
Hiromi Arai
洋実 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP15957693A priority Critical patent/JPH0720811A/en
Publication of JPH0720811A publication Critical patent/JPH0720811A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide fixed pull-in sensitivity even when horizontal synchronizing signals with various frequencies are inputted by varying a pulse width of an output pulse of a waveform shaping circuit according to the frequency of the horizontal synchronizing signal. CONSTITUTION:This circuit is provided with the waveform shaping circuit generating a fixed width pulse according to the horizontal synchronizing signal, a phase comparator 1 comparing phase of the output pulse of the waveform shaping circuit with phase of a flyback pulse from a horizontal deflection coil and a smoothing circuit 2 smoothing the output signal of the phase comparator 1. Further, the circuit is constituted so as to be provided with a horizontal oscillation circuit 3 whose oscillation frequency is changed according to the output DC signal of the smoothing circuit 2 and impressing the oscillation output signal to the horizontal deflection coil and a control circuit 8 varying the pulse width of the output pulse of the waveform shaping circuit according to the frequency of the horizontal synchronizing signal. Thus, even when the horizontal synchronizing signals with various frequencies are inputted, fixed pull-in sensitivity is provided. Further, the sensitivity of a horizontal AFC circuit is fixed without increasing the number of elements and increasing the external components of an IC.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、コンピュータなどに利
用されるCRTディスプレイ装置の水平AFC(自動周
波数制御)回路に関するもので、特に種々の周波数の水
平同期信号に対応可能な水平AFC回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal AFC (automatic frequency control) circuit of a CRT display device used in a computer or the like, and more particularly to a horizontal AFC circuit capable of supporting horizontal synchronizing signals of various frequencies.

【0002】[0002]

【従来の技術】映像信号中の水平同期信号にロックし
て、水平偏向コイルに安定に水平出力パルスを印加する
水平AFC回路が知られている。TV受像機において
は、前記水平AFC回路に印加される水平同期信号のパ
ルス幅は、ほぼ一定である。しかしながら、コンピュー
タなどに利用されるCRTディスプレイ装置では、種々
のソースからの映像信号が印加され、該ソースによって
水平同期信号のパルス幅は、種々に変化する。例えば、
同じ30KHzの周波数の水平同期信号でもそのパルス
幅は異なる場合がある。該パルス幅が異なると、後段の
水平AFC回路における位相比較器の動作時間が異な
り、水平AFC回路の応答感度が変動してしまう、とい
う問題があった。そこで、図2の如く、位相比較器
(1)、平滑回路(2)及び水平発振回路(3)から成
る水平AFC回路(4)の前段にM・M(単安定マルチ
バイブレータ)(5)を挿入し、水平同期信号のパルス
幅を一旦、一定値に波形整形しているものが考えられ
る。
2. Description of the Related Art A horizontal AFC circuit is known which locks on a horizontal synchronizing signal in a video signal and stably applies a horizontal output pulse to a horizontal deflection coil. In the TV receiver, the pulse width of the horizontal synchronizing signal applied to the horizontal AFC circuit is almost constant. However, in a CRT display device used in a computer or the like, video signals from various sources are applied, and the pulse width of the horizontal synchronizing signal changes variously depending on the sources. For example,
The pulse widths of horizontal sync signals having the same frequency of 30 KHz may differ. When the pulse width is different, there is a problem that the operation time of the phase comparator in the horizontal AFC circuit at the subsequent stage is different and the response sensitivity of the horizontal AFC circuit is changed. Therefore, as shown in FIG. 2, an MM (monostable multivibrator) (5) is provided in front of a horizontal AFC circuit (4) including a phase comparator (1), a smoothing circuit (2) and a horizontal oscillator circuit (3). It is conceivable that the pulse width of the horizontal synchronizing signal is once inserted and the waveform is once shaped into a constant value.

【0003】図2の装置によれば、水平同期信号のパル
ス幅に拘わらず、一定感度で水平同期信号にロックさせ
ることができる。
According to the apparatus of FIG. 2, the horizontal synchronizing signal can be locked with a constant sensitivity regardless of the pulse width of the horizontal synchronizing signal.

【0004】[0004]

【発明が解決しようとする課題】図2の装置において
は、ソースにより水平同期信号の周波数も変化する。そ
の場合には、水平発振回路(3)の中心周波数を端子
(6)からの制御信号により、制御トランジスタ(7)
の電流を変化させ連続的に切換えている。そうすれば、
位相比較器(1)には等しい周波数の2つの信号が印加
され、水平AFC回路(4)は、入力信号にロックでき
る。ところが、図2の装置では水平同期信号の周波数が
変化してもM・M(5)の出力パルスのパルス幅は変わ
らない。該パルス幅は、水平AFC回路(4)の位相比
較器(1)における位相比較動作実行時間を定めてお
り、その時間も変化しないことになる。それに対して、
位相比較器(1)が不動作の期間は、水平同期信号の周
波数に応じて変化するので、入力信号に対する水平AF
C回路(4)の引き込み感度が前記周波数に応じて変化
してしまう、という問題があった。前記引き込み感度を
一定にする為には平滑回路(2)の時定数を調整すれば
良いが、素子数の増加やIC化した場合の外付け部品の
増加が問題となった。又、前記時定数を連続的に変化さ
せることは困難である。
In the device of FIG. 2, the frequency of the horizontal synchronizing signal also changes depending on the source. In that case, the center frequency of the horizontal oscillator circuit (3) is controlled by the control signal from the terminal (6) to control transistor (7).
The current is changed to switch continuously. that way,
Two signals of equal frequency are applied to the phase comparator (1) and the horizontal AFC circuit (4) can lock to the input signal. However, in the apparatus of FIG. 2, the pulse width of the output pulse of M · M (5) does not change even if the frequency of the horizontal synchronizing signal changes. The pulse width defines the phase comparison operation execution time in the phase comparator (1) of the horizontal AFC circuit (4), and that time will not change. On the other hand,
During the period when the phase comparator (1) is not operating, it changes according to the frequency of the horizontal synchronizing signal.
There is a problem that the pull-in sensitivity of the C circuit (4) changes according to the frequency. In order to make the pull-in sensitivity constant, the time constant of the smoothing circuit (2) may be adjusted, but the increase in the number of elements and the increase in external parts when integrated into an IC poses a problem. Further, it is difficult to continuously change the time constant.

【0005】[0005]

【課題を解決するための手段】本発明は上述の点に鑑み
成されたもので、水平同期信号に応じて一定幅のパルス
を発生する波形整形回路と、該波形整形回路の出力パル
スと水平偏向コイルからのフライバックパルスとの位相
比較を行なう位相比較器と、該位相比較器の出力信号を
平滑する平滑回路と、該平滑回路の出力直流信号に応じ
て発振周波数が変化し、その発振出力信号を前記水平偏
向コイルに印加する水平発振回路と、前記水平同期信号
の周波数に応じて前記波形整形回路の出力パルスのパル
ス幅を変える制御回路と、を有する。
The present invention has been made in view of the above points, and a waveform shaping circuit for generating a pulse having a constant width in response to a horizontal synchronizing signal, and an output pulse of the waveform shaping circuit and a horizontal pulse A phase comparator that performs phase comparison with the flyback pulse from the deflection coil, a smoothing circuit that smoothes the output signal of the phase comparator, and an oscillation frequency that changes according to the DC signal output from the smoothing circuit A horizontal oscillation circuit that applies an output signal to the horizontal deflection coil, and a control circuit that changes the pulse width of the output pulse of the waveform shaping circuit according to the frequency of the horizontal synchronization signal.

【0006】[0006]

【作用】本発明に依れば、到来する水平同期信号の周波
数に応じて波形整形回路から発生する出力パルスのパル
ス幅を変化させている。前記周波数が低い時には前記パ
ルス幅を長くし、前記周波数が高い時には前記パルス幅
を短くしている。その為、水平同期信号の一周期当たり
の位相比較期間(パルス幅)の割合が、水平同期信号の
周波数に拘わらず常に一定となり、水平AFC回路の感
度を一定にすることができる。
According to the present invention, the pulse width of the output pulse generated from the waveform shaping circuit is changed according to the frequency of the incoming horizontal synchronizing signal. When the frequency is low, the pulse width is lengthened, and when the frequency is high, the pulse width is shortened. Therefore, the ratio of the phase comparison period (pulse width) per one cycle of the horizontal synchronizing signal is always constant regardless of the frequency of the horizontal synchronizing signal, and the sensitivity of the horizontal AFC circuit can be constant.

【0007】[0007]

【実施例】図1は、本発明の一実施例を示すブロック図
で、(8)は、水平発振回路(3)の中心周波数を制御
する端子(6)からの制御信号に応じてM・M(5)の
出力パルスのパルス幅を変化させる制御トランジスタで
ある。尚、図1において図2と同一の回路ブロックにつ
いては同一の符号を付し説明を省略する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, in which (8) shows M.multidot.M in response to a control signal from a terminal (6) for controlling the center frequency of a horizontal oscillation circuit (3). It is a control transistor that changes the pulse width of the output pulse of M (5). In FIG. 1, the same circuit blocks as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

【0008】図1の端子(6)には所望の水平発振周波
数に対応する直流電圧が印加され、トランジスタ(7)
及び(8)のコレクタには各々直流電流が流れ、水平発
振回路(3)からは周期T1の信号が発生し、M・M
(5)からは周期T1に対応したパルス幅T3の出力パル
スが発生する。図1の線Aには水平偏向コイル(9)か
ら発生する図3(a)の如き周期T1の水平FBP(フ
ライバックパルス)は、平滑回路(10)で平滑され図
3(b)の如き鋸歯状波に変換され、直流阻止コンデン
サ(11)で直流分が除去されて位相比較器(1)に印
加される。
A direct current voltage corresponding to a desired horizontal oscillation frequency is applied to the terminal (6) of FIG.
A direct current flows through the collectors of (8) and (8), respectively, and a signal of period T 1 is generated from the horizontal oscillation circuit (3).
From (5), an output pulse having a pulse width T 3 corresponding to the period T 1 is generated. A horizontal FBP (flyback pulse) generated from the horizontal deflection coil (9) and having a period T 1 as shown in FIG. 3A is smoothed by the smoothing circuit (10) in the line A of FIG. Such a sawtooth wave is converted, the direct current component is removed by the direct current blocking capacitor (11), and the result is applied to the phase comparator (1).

【0009】一方、M・M(5)からは、図3(c)の
如きパルス幅が期間T3の出力パルスが発生し、位相比
較器(1)に印加されている。この状態から、入力端子
(12)に加わる水平同期信号の周波数を1/2に低く
すると、その分、水平発振回路(3)の周波数を下げる
必要があるので、例えば端子(6)により低い電圧を印
加する。すると、図1の線Aに図3(d)の周期T2
パルスが発生し、平滑回路(10)で図3(e)の如く
なり、位相比較器(1)に印加される。
On the other hand, an output pulse having a pulse width of T 3 as shown in FIG. 3C is generated from MM (5) and applied to the phase comparator (1). From this state, if the frequency of the horizontal synchronizing signal applied to the input terminal (12) is reduced to 1/2, the frequency of the horizontal oscillation circuit (3) needs to be reduced by that amount, so that a lower voltage is applied to the terminal (6), for example. Is applied. Then, a pulse having a period T 2 of FIG. 3D is generated on the line A of FIG. 1, and the smoothing circuit (10) produces a pulse as shown in FIG. 3E, which is applied to the phase comparator (1).

【0010】一方、M・M(5)も端子(6)からの制
御信号に応じてその出力パルスの幅を2倍に変化させ、
図3(f)のパルス(パルス幅T4=2T3)を発生す
る。ここで、図3の期間T1:T3と期間T2:T4の比
は、一定であるので水平AFC回路(4)の応答感度
は、元のままである。従って、図1の装置に依れば異な
る周波数の水平同期信号が印加されても、水平AFC回
路は、一定の応答感度で動作する。
On the other hand, MM (5) also doubles the width of its output pulse according to the control signal from the terminal (6),
The pulse shown in FIG. 3 (f) (pulse width T 4 = 2T 3 ) is generated. Here, since the ratio of the period T 1 : T 3 and the period T 2 : T 4 in FIG. 3 is constant, the response sensitivity of the horizontal AFC circuit (4) remains unchanged. Therefore, according to the apparatus of FIG. 1, the horizontal AFC circuit operates with a constant response sensitivity even when horizontal synchronizing signals of different frequencies are applied.

【0011】図4は、図1のM・M(5)の具体回路例
を示すもので、RS−FF(RS型フリップフロップ)
(13)と、第1及び第2トランジスタ(14)及び
(15)と、電流ミラー回路(16)と、充放電コンデ
ンサ(17)と、第1及び第2コンパレータ(18)及
び(19)とからなる。初期状態においては、RS−F
F(13)がリセットされており、第1トランジスタ
(14)がオフ、第2トランジスタ(15)がオンして
いるので、電流ミラー回路(16)が動作し、充放電コ
ンデンサ(17)が放電状態となっている。この為、点
Cの電圧は、電源電圧(+VCC)レベルとなっており、
第1及び第2コンパレータ(18)及び(19)の出力
は共に「L」レベルとなっている。
FIG. 4 shows an example of a concrete circuit of MM (5) of FIG. 1, which is RS-FF (RS type flip-flop).
(13), first and second transistors (14) and (15), current mirror circuit (16), charge and discharge capacitor (17), and first and second comparators (18) and (19) Consists of. In the initial state, RS-F
Since F (13) is reset, the first transistor (14) is off, and the second transistor (15) is on, the current mirror circuit (16) operates and the charge / discharge capacitor (17) discharges. It is in a state. Therefore, the voltage at point C is at the power supply voltage (+ V CC ) level,
The outputs of the first and second comparators (18) and (19) are both at "L" level.

【0012】今、図5(a)の水平同期信号が入力端子
(12)からRS−FF(13)に印加されると、その
Q出力は図5(b)の如くなり、第1トランジスタ(1
4)がオン、第2トランジスタ(15)がオフし、制御
トランジスタ(8)の定電流により、充放電コンデンサ
(17)が充電される。すると、図4の点Cの電圧は、
図5(c)の如く直線的に低下し、それが第1コンパレ
ータ(18)の基準電圧V1より低下すると、第1コン
パレータ(18)の出力は「H」レベルとなり、RS−
FF(13)をリセットし、充放電コンデンサ(17)
を急速放電させるので、急速に電源電圧に向かって上昇
する。その結果、第1コンパレータ(18)の出力は、
図5(d)の如くなり、第2コンパレータ(19)の出
力Voutは、図5(e)の如くなる。図5(e)の出力
パルスの立ち上がりタイミングは、基準電圧V2を一定
とすると、図5(c)の充電カーブにより定められるの
で、制御トランジスタ(8)の端子(6)に加える直流
電圧により出力パルスVou tのパルス幅を定めることが
できる。
Now, when the horizontal synchronizing signal of FIG. 5 (a) is applied to the RS-FF (13) from the input terminal (12), its Q output becomes as shown in FIG. 5 (b), and the first transistor ( 1
4) is turned on, the second transistor (15) is turned off, and the constant current of the control transistor (8) charges the charge / discharge capacitor (17). Then, the voltage at point C in FIG.
When the voltage drops linearly as shown in FIG. 5 (c) and becomes lower than the reference voltage V 1 of the first comparator (18), the output of the first comparator (18) becomes “H” level and RS−
Reset the FF (13) and charge / discharge capacitor (17)
Is rapidly discharged, the voltage rapidly rises toward the power supply voltage. As a result, the output of the first comparator (18) is
As shown in FIG. 5 (d), the output V out of the second comparator (19) becomes as shown in FIG. 5 (e). The rising timing of the output pulse of FIG. 5 (e) is determined by the charging curve of FIG. 5 (c) when the reference voltage V 2 is constant, so that it depends on the DC voltage applied to the terminal (6) of the control transistor (8). it is possible to determine the pulse width of the output pulse V ou t.

【0013】[0013]

【発明の効果】以上述べた如く、本発明に依れば種々の
周波数の水平同期信号が到来しても一定の引き込み感度
を有する水平AFC回路を提供できる。特に本発明に依
れば、波形整形回路により出力パルスのパルス幅を水平
同期信号の周波数に応じて変えているので、素子数の増
加やICの外付け部品の増加を招かずに水平AFC回路
の感度を一定にできる。
As described above, according to the present invention, it is possible to provide a horizontal AFC circuit having a constant pull-in sensitivity even when horizontal synchronizing signals of various frequencies arrive. In particular, according to the present invention, since the pulse width of the output pulse is changed by the waveform shaping circuit according to the frequency of the horizontal synchronizing signal, the horizontal AFC circuit is not brought about without increasing the number of elements and the external parts of the IC. The sensitivity of can be made constant.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の水平AFC回路を示すブロック図であ
る。
FIG. 1 is a block diagram showing a horizontal AFC circuit of the present invention.

【図2】従来の水平AFC回路を示すブロック図であ
る。
FIG. 2 is a block diagram showing a conventional horizontal AFC circuit.

【図3】図1の説明に供する為の波形図である。FIG. 3 is a waveform chart for explaining FIG.

【図4】図1のM・M(5)の具体回路図である。4 is a specific circuit diagram of MM (5) of FIG.

【図5】図4の説明に供する為の波形図である。FIG. 5 is a waveform diagram for explaining FIG.

【符号の説明】[Explanation of symbols]

(1) 位相比較器 (2) 平滑回路 (3) 水平発振回路 (5) M・M (8) 制御トランジスタ (1) Phase comparator (2) Smoothing circuit (3) Horizontal oscillation circuit (5) MM (8) Control transistor

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 複数の周波数の水平同期信号にロックす
る水平AFC回路であって、 前記水平同期信号に応じて一定幅のパルスを発生する波
形整形回路と、 該波形整形回路の出力パルスと水平偏向コイルからのフ
ライバックパルスとの位相比較を行なう位相比較器と、 該位相比較器の出力信号を平滑する平滑回路と、 該平滑回路の出力直流信号に応じて発振周波数が変化
し、その発振出力信号を前記水平偏向コイルに印加する
水平発振回路と、 前記水平同期信号の周波数に応じて前記波形整形回路の
出力パルスのパルス幅を変える制御回路と、を有するこ
とを特徴とする水平AFC回路。
1. A horizontal AFC circuit that locks to a horizontal synchronizing signal of a plurality of frequencies, the waveform shaping circuit generating a pulse of a constant width according to the horizontal synchronizing signal, and an output pulse of the waveform shaping circuit and a horizontal pulse. A phase comparator that performs phase comparison with the flyback pulse from the deflection coil, a smoothing circuit that smoothes the output signal of the phase comparator, and an oscillation frequency that changes according to the DC signal output from the smoothing circuit A horizontal AFC circuit comprising: a horizontal oscillation circuit that applies an output signal to the horizontal deflection coil; and a control circuit that changes the pulse width of the output pulse of the waveform shaping circuit according to the frequency of the horizontal synchronization signal. .
【請求項2】 前記制御回路は、前記水平発振回路の発
振周波数を変化させることを特徴とする請求項1記載の
水平AFC回路。
2. The horizontal AFC circuit according to claim 1, wherein the control circuit changes an oscillation frequency of the horizontal oscillation circuit.
【請求項3】 前記波形整形回路は、単安定マルチバイ
ブレータであることを特徴とする請求項1記載の水平A
FC回路。
3. The horizontal A according to claim 1, wherein the waveform shaping circuit is a monostable multivibrator.
FC circuit.
JP15957693A 1993-06-29 1993-06-29 Horizontal afc circuit Pending JPH0720811A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15957693A JPH0720811A (en) 1993-06-29 1993-06-29 Horizontal afc circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15957693A JPH0720811A (en) 1993-06-29 1993-06-29 Horizontal afc circuit

Publications (1)

Publication Number Publication Date
JPH0720811A true JPH0720811A (en) 1995-01-24

Family

ID=15696736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15957693A Pending JPH0720811A (en) 1993-06-29 1993-06-29 Horizontal afc circuit

Country Status (1)

Country Link
JP (1) JPH0720811A (en)

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