JPH0720715U - PLL circuit for FM stereo demodulation - Google Patents

Abstract

(57) [Summary] [Object] The present invention provides a PLL circuit for FM stereo demodulation which can increase the accuracy of a voltage applied to a voltage controlled oscillator and generate a switching signal for accurate synchronous detection. A first current mirror circuit has the same drive current and mirror current as the first current mirror circuit at an input terminal different from the input terminal of the DC amplifier 12 to which the first current mirror circuit which is an active load circuit of the phase comparator is connected. By connecting the current mirror circuit of No. 2, the offset voltage is prevented from being generated in the DC amplifier 12 in the previous stage of the voltage controlled oscillator.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to an FM stereo demodulation PLL circuit capable of increasing the accuracy of the voltage applied to a voltage controlled oscillator and generating a switching signal for accurate synchronous detection.

[0002]

[Prior art]

 In this type of PLL circuit, as shown in the block diagram of FIG. 3, a phase detector (PC) 10 compares a 19 KHz pilot signal with a 19 KHz signal obtained from a voltage controlled oscillator (VCO) 13 for synchronous detection. Is configured to obtain a switching signal of 38 KHz. Reference numeral 11 is a low-pass filter (LPF) that converts the output of the phase comparator 10 generated when both signals to be compared have a phase difference into DC, and 12 is a DC amplifier (AF) that amplifies the output of the low-pass filter 11. ). Of course, this PLL circuit is configured by an integrated circuit.

The frequency of the output of the voltage controlled oscillator 13 is usually set to 76 KHz, a 19 KHz signal is obtained by the 1/2 frequency dividers (DV) 14 and 15, and 38 KHz from the connection point of both frequency dividers. Is applied to the synchronous detection circuit. This switching signal is required to have an accurate frequency and a rectangular wave, and if there is a shift in frequency or phase, it will adversely affect the degree of separation of the composite signal. An offset voltage generated on the input side of the DC amplifier 12 is a cause of impeding the generation of an accurate switching signal.

FIG. 2 is a circuit diagram of a conventional PLL circuit in a portion surrounded by a dotted line in FIG. 3. The generation of the offset voltage will be described. In FIG. 2, transistors Q1 to Q8 form a double-balanced multiplication circuit, and a first current mirror circuit including transistors Q1 and Q2 is connected as an active load of the multiplication circuit. . A phase comparator is constituted by this multiplication circuit. A 19 KHz signal obtained from the voltage controlled oscillator 13 is applied to the input terminals 3 and 4 of the upper differential pair, and 19 KHz is input to the input terminal 5 of the lower differential pair. The pilot signals of are added and the phases are compared.

The capacitor C1, the series circuit of the resistor R1 and the capacitor C2 constitutes a low-pass filter 11, and is connected to the outside of the integrated circuit by a terminal 6. The resistors R2 and R3 are bias resistors connected to both input terminals of the DC amplifier 12, but the resistor R2 is connected in parallel with the capacitor C1 in terms of AC, and also serves as a circuit element forming a low-pass filter. There is. _{Reference numeral} 1 is a power supply terminal to which a power supply voltage V _CC is applied, 2 is an output terminal of the DC amplifier 12, S 1 is a constant current source, and E1 and E2 are bias voltage sources. The current value of the constant current source S1 is 2I ₂ when the collector current of the transistor Q2 is I ₂ .

In such a circuit, an offset voltage is easily generated due to the connection of the current mirror circuit as the load of the phase comparator. That is, the collector current of the transistor Q1 which is the mirror current of the first current mirror circuit is theoretically slightly smaller than the collector current of the diode-connected transistor Q2 which is the drive current. The multiplier circuit is set so that the same balanced current flows from the current mirror circuit, so the current of the difference flows into the resistor R2, which produces a voltage at one input terminal of the DC amplifier 12 and causes an offset. It becomes a voltage.

When the value of the resistor R2 is small, this offset voltage can be ignored, but when it is large, it cannot be ignored. As described above, the resistor R2 constitutes a part of the low-pass filter 11, and since the cutoff frequency of the filter 11 is very low, such as several Hz, the resistor R2 has a large value of 100 KΩ or more, and the offset The voltage cannot be ignored. Therefore, due to the presence of this offset voltage, an error occurs in the voltage applied from the output terminal 2 of the DC amplifier 12 to the voltage controlled oscillator 13, and the state in which the generation of an accurate switching signal is disturbed is likely to occur.

[0008]

[Problems to be solved by the device]

 An object of the present invention is to provide a PLL circuit for FM stereo demodulation in which an offset voltage is not generated at the input terminal of a DC amplifier even if there is a difference in the current of the first current mirror circuit which is the active load of the multiplication circuit. To provide.

[0009]

[Means for Solving the Problems]

 The PLL circuit for FM stereo demodulation of the present invention is for FM stereo demodulation for obtaining a switching signal for synchronous detection by comparing a pilot signal and a signal of the same frequency as the pilot signal obtained from the output of the voltage controlled oscillator with a phase comparator. In the PLL circuit, the phase comparator is composed of a double-balanced type multiplying circuit to which an active load circuit composed of a first current mirror circuit is connected, and the output terminal of the comparator passes through a loop filter and is connected to a direct-current stage before the voltage-controlled oscillator. A second current mirror circuit which is connected to one input terminal of the amplifier, and which is connected to the other input terminal of the amplifier to generate the same drive current and mirror current as the first current mirror circuit. .

[0010]

【Example】

 An embodiment of the PLL circuit for FM stereo demodulation of the present invention will be described below with reference to FIG. 1, which is a circuit diagram. The same parts as those in FIG. 2 are designated by the same reference numerals. In FIG. 1, Q1 to Q8 are transistors forming a phase comparator, and the phase comparator is formed of a double balanced type multiplication circuit. Q3 to Q6 are transistors forming the upper differential pair of the multiplication circuit, and Q7 and Q8 are transistors forming the lower differential pair.

The transistor Q3 and the transistor Q4, the transistor Q5 and the transistor Q6, and the transistor Q7 and the transistor Q8 form a pair of differential pairs, respectively. Connected to the collector of Q7. Further, the emitters of the commonly connected transistor Q5 and transistor Q6 are connected to the collector of the transistor Q8. The emitters of the commonly connected transistors Q7 and Q8 are connected to the constant current source S1. The bases of the transistors Q7 and Q8 are connected to the bias voltage source E1 via the resistors R5 and R4, and the base of the transistor Q7 is connected to the input terminal 5 of the lower differential pair.

The bases of the transistors Q4 and Q5, and the bases of the transistor Q3 and the transistor Q6 are connected to the input terminals 3 and 4 of the upper differential pair. The collectors of the transistors Q3 and Q5 and the collectors of the transistors Q4 and Q6 are connected to each other, and the connection points are connected to the collectors of the transistors Q1 and Q2. The transistors Q1 and Q2 form a first current mirror circuit which is an active load circuit of the multiplication circuit, and the commonly connected emitters are connected to the power supply terminal 1 to which the power supply voltage V _CC is applied.

The collector of the transistor Q1, which is the output terminal of the phase comparator, is connected to the terminal 6 exposed to the outside of the integrated circuit, and is also connected to the non-inverting input terminal of the DC amplifier 12 via the terminal 6. . This DC amplifier 12 is a differential amplifier. The non-inverting input terminal and the inverting input terminal of the DC amplifier 12 are connected to the bias voltage source E2 via the resistors R2 and R3 having the same resistance value. Between the terminal 6 and the power supply terminal 1, a capacitor C1 forming a low-pass filter and a series circuit including a resistor R1 and a capacitor C2 are connected in parallel.

A second current mirror circuit including a transistor Q9 and a transistor Q10 is connected to the inverting input terminal of the DC amplifier 12, and the collector of the output transistor Q9 is connected to the second current mirror circuit. A power supply voltage V _CC is applied to the emitters of the commonly connected transistors Q9 and Q10, the collector of the transistor Q9 is connected to the constant current source S2, and the collector of the transistor Q10 is connected to the constant current source S3. The current value of the constant current source S1 is 2I ₂ when the collector current of the transistor Q2 is I _2, and the current values of the constant current sources S2 and S3 are I ₂ .

Therefore, the drive current and the mirror current of the first and second current mirror circuits are set so that the same value can be obtained respectively. Further, the circuit part of the second current mirror circuit connected to the inverting input terminal of the DC amplifier 12 is the same as the circuit part of the first current mirror circuit connected to the non-inverting input terminal, and both are mirrors of the current mirror circuit. The collector of the transistor that obtains the current is connected. The second current mirror circuit is set so that the sum of the collector current of the transistor Q9 and the current of the resistor R3, which is the mirror current, becomes equal to the collector current I ₂ of the diode-connected transistor Q10, which is the drive current. Has been done.

Since the general operation of the phase comparator, the low-pass filter, and the DC amplifier 12 which is composed of the double balanced type multiplication circuit in the PLL circuit for FM stereo demodulation configured in this way has already been described, the DC amplifier 12 The offset voltage of will be described. The double-balanced multiplication circuit that forms the phase comparator also draws in the collector current of the diode-connected transistor Q2 that is the drive current and the mirror current of the same value as the collector current from the first current mirror circuit. To try However, since the mirror current, that is, the collector current of the transistor Q1 is slightly smaller than the collector current of the transistor Q2, its shortage flows from the voltage source E2 through the resistor R2 to the multiplication circuit, and the non-inversion of the DC amplifier 12 occurs. Generates a voltage at the input terminal.

However, the collector current of the diode-connected transistor Q10 of the second current mirror circuit is set to the current I ₂ by the current source S3, and the mirror current, that is, the collector current of the transistor Q9 is the first. It is equal to the mirror current of the current mirror circuit. Since the current I ₂ flows through the constant current source S2, the shortage thereof flows from the voltage source E2 through the resistor R3. Therefore, since the same voltage as the non-inverting input terminal is generated at the inverting input terminal of the DC amplifier 12, no offset voltage is generated at the input side of the DC amplifier 12. Since a highly accurate DC voltage having no error is obtained at the output terminal 2 of the direct current amplifier 12 according to the output of the phase comparator, an accurate switching signal can be obtained from the voltage controlled oscillator. Although the first and second current mirror circuits connected to the input terminal of the DC amplifier 12 are collectors of the transistors that obtain the mirror current in the embodiment, they may be the same circuit portion of the current mirror circuit. Alternatively, it may be a collector of a transistor that obtains a driving current.

[0018]

[Effect of device]

 As described above, the PLL circuit for FM stereo demodulation of the present invention has the difference in the driving current and the mirror current of the first current mirror circuit, which is the active load circuit of the phase comparator, even if there is a difference between the current and the mirror current. In the DC amplifier, the offset voltage caused by the difference is prevented. This is because the same voltage as that generated at the input terminal on one side of the DC amplifier according to the difference between the drive current and the mirror current of the first current mirror circuit is generated at the other input terminal by the second current mirror circuit. by. This makes it possible to increase the accuracy of the voltage applied to the voltage controlled oscillator, generate a switching signal for accurate synchronous detection, and accurately separate the composite signal. The entire circuit has only the addition of the second current mirror circuit as compared with the conventional circuit, and has an advantage that it can be constructed extremely simply.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a PLL circuit for FM stereo demodulation of the present invention.

FIG. 2 is a circuit diagram of a conventional PLL circuit for FM stereo demodulation.

FIG. 3 is a circuit diagram for explaining a PLL circuit for FM stereo demodulation.

[Explanation of symbols]

 12 DC amplifier R1, R2 resistance

Claims (2)

[Scope of utility model registration request] 1. A phase comparison in an FM stereo demodulation PLL circuit for obtaining a switching signal for synchronous detection by comparing a pilot signal and a signal of the same frequency as the pilot signal obtained from the output of the voltage controlled oscillator with a phase comparator. The comparator is composed of a double balanced type multiplying circuit to which an active load circuit composed of a first current mirror circuit is connected, and the output terminal of the comparator is passed through a loop filter and an input terminal of one side of a direct current amplifier of the voltage controlled oscillator And a second current mirror circuit that produces the same drive current and mirror current as the first current mirror circuit is connected to the other input terminal of the amplifier.
circuit. 2. A phase comparison in an FM stereo demodulation PLL circuit for obtaining a switching signal for synchronous detection by comparing a pilot signal and a signal of the same frequency as the pilot signal obtained from the output of the voltage controlled oscillator by a phase comparator. Is composed of a double balanced type multiplying circuit to which an active load circuit composed of a first current mirror circuit is connected. One end of the first current mirror circuit, which is the output terminal of the phase comparator, passes through a loop filter and is a voltage controlled oscillator. Connected to one input terminal of the DC amplifier in the preceding stage, and the circuit portion of the second current mirror circuit corresponding to the one end of the first current mirror circuit is connected to the other input terminal of the amplifier. FM stereo demodulation, characterized in that the drive current and the mirror current of the current mirror circuit and the second current mirror circuit are respectively set to be the same. PLL circuit for.