JPS5911285B2 - phase comparison circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a double-balanced differential amplification circuit suitable for application to a phase-locked loop (hereinafter simply referred to as PLL), particularly a multiplex stereo demodulation circuit using this loop. This invention relates to a phase comparator circuit using.

Two examples of conventional phase comparator circuits of this type will be described below with reference to the drawings.

First, one of the conventional phase comparator circuits will be explained with reference to FIG.

11 and 12 are 19K frequency controlled by PLL
Input terminals 13 and 14 are supplied with mutually opposite phase rectangular wave signals of H2, that is, reference signals, and 13 and 14 are one of the composite stereo signals.
This is an input terminal to which 9KHZ pilot signals having mutually opposite phases, that is, sine waves are supplied.

Further, 15 and 16 are output terminals from which output voltages of opposite polarity are obtained according to the phase difference between the above-mentioned reference signal and pilot signal.

This phase comparator circuit consists of a double-balanced differential amplification circuit.
It consists of three pairs of differential amplifier circuits 1γ, 18 and 22.

The differential amplification circuit 17 includes a switching transistor 19
,20,.

the base of transistor 190 is connected to input terminal 11;
Transistor 200 base is connected to input terminal 12 .

Each emitter of transistors 19 and 20 is connected to the collector of transistor 21.

The base of transistor 21 is connected to input terminal 13 .

The emitter of the transistor 21 is connected to a constant current circuit 24 through a resistor 23.

The collector of transistor 19 is connected to output terminal 16.

The collector of the transistor 20 is connected to the output terminal 15 and also to the power supply 1B through a load resistor 25.

On the other hand, the differential amplification circuit 18 includes switching transistors 26 and 27, an amplification transistor 28, and a constant current circuit 24.
It consists of

The base of transistor 260 is connected to input terminal 12;
The base of transistor 27 is connected to input terminal 11 .

The emitters of transistors 26 and 27 are transistor 2
The emitter of the transistor 28 is connected to the constant current circuit 24 through a resistor 29.

The base of transistor 28 is connected to input terminal 14 .

The collector of transistor 26 is connected to power supply +B through resistor 30.

The collector of transistor 27 is connected to output terminal 15 .

The phase comparison circuit shown in FIG. 1 is provided with a load circuit having passive elements as a load of a double-balanced differential amplification circuit.

This phase comparison circuit has the following drawbacks.

■ The gain as an amplifier can be determined by setting the value of the load resistor 25,300 and the value of the emitter resistor 23,29 of the transistor 2L28 that constitutes the differential circuit 22. If these resistance values are selected, the DC potential to be supplied to the next stage amplifier through the output terminals 15 and 16 is automatically determined, and cannot be freely set to a desired value.

■Load resistor 25. Although it is desirable to make the resistance values of the resistors 30 and 30 exactly equal, it is common for manufacturing processes to result in slight differences.

The difference in resistance value appears at terminals 15 and 16 as a DC level difference, that is, an offset voltage, which adversely affects the voltage controlled oscillator connected at the subsequent stage.

Next, another example of the conventional phase comparator circuit of this type will be described with reference to FIG.

In Figure 2, 11, 12. 13 and 14 are input terminals similar to those in FIG.

Further, 15 is an output terminal from which an unbalanced output current can be obtained.

This phase comparator circuit also consists of a double-balanced differential amplification circuit, and the double-balanced differential amplification circuit consists of three pairs of differential amplification circuits 30, 31 and 32.

The differential amplification circuit 31 includes a switching transistor 33,
34, and a width increasing transistor 39.

The base of the transistor 33 is connected to the input terminal 11,
The base of transistor 34 is connected to input terminal 12 .

The emitters of transistors 33 and 34 are connected to the collector of transistor 39.

The base of transistor 390 is connected to input terminal 13.

The emitter of transistor 39 is grounded through resistor 40.

The collector of transistor 33 is connected to power supply +B through load circuit 35.

The load circuit 35 includes transistors 36, 3T and a resistor 38.
The collector of transistor 37 is grounded, the emitter thereof is connected to the base of transistor 36, and the base of transistor 370 is connected to the collector of transistor 36.

The emitter of transistor 36 is connected through resistor 38 to power supply +B.

The differential amplification circuit 32 includes a switching transistor 42,
43, and a width increasing transistor 47.

transistor 420 base is connected to input terminal 12;
Its collector is connected to the collector of transistor 33.

The base of transistor 430 is connected to input terminal 11.

The emitters of transistors 42 and 43 are connected to the collector of transistor 47, the emitter of transistor 47 is grounded through resistor 48, and the emitter of transistor 47 is grounded through resistor 41.
It is connected to the emitter of transistor 39 through.

The base of transistor 47 is connected to input terminal 14 .

The collector of transistor 43 is connected to the collector of transistor 34 and also to output terminal 15 .

The collector of transistor 43 is connected to power supply +B through load circuit 44 .

The load circuit 44 consists of a transistor 45 and a resistor 46.

The collector of transistor 43 is connected to the collector of transistor 45, the base of transistor 450 is connected to the base of transistor 360, and the emitter of transistor 45 is connected to power supply +B through resistor 46.

The phase comparison circuit shown in FIG. 2 uses a load circuit having an active element as a load of a double-balanced differential amplifier circuit.

The phase comparator circuit shown in Figure 2 can obtain a fairly large gain, but since the output is unbalanced, the two to be compared
The disadvantage is that the time constant of the low-pass f-wave filter when removing interference noise components other than signals based on the phase difference between the two signals is significant.

In view of the shortcomings of conventional circuits, the present invention proposes a phase comparison circuit of this type that can set the gain arbitrarily and can give an arbitrary DC level to the output terminal to obtain a balanced output current with good DC balance. This is what I am trying to do.

The present invention will be explained in detail below with reference to its embodiments.

The present invention will be described with reference to a phase comparator circuit suitable for use as a phase comparator circuit in a multiplex stereo demodulation circuit using a phase-opened loop.

The overall configuration of the multiplex stereo demodulation circuit will be explained with reference to FIG.

1 is an input terminal to which a decomposed stereo signal is supplied, 2 is a phase comparison circuit, 3 is a current-to-voltage conversion circuit, 4 is a low-pass F wave generator, 5 is a DC amplification circuit, and 6 is a current control circuit with an oscillation frequency of 76 KHZ. A PLL is constituted by the phase comparator circuit 2, the current-voltage conversion circuit 3, the low-pass r wave generator 4, the DC amplifier circuit 5, the variable oscillator 6, the frequency divider 7, and the frequency divider 8.

The phase comparator circuit 2 receives the 19KH. of the composite stereo signal from the input terminal 1. The pilot signal of Z and the 19 KHZ reference signal obtained from the frequency divider 8 are compared in phase.

Further, the 38 KHz subcarrier signal output from the frequency divider 7 is supplied to the stereo demodulation circuit 9.

Left and right audio signals are obtained from the stereo demodulation circuit 9, respectively.

The present invention is applied to the phase comparator circuit 2 shown in FIG.

An example of the phase comparator circuit according to the present invention will be explained in detail below with reference to FIG.

Reference numerals 11 and 12 are input terminals to which reference signals (rectangular wave signals) of 19 KH and z, which are output from the frequency divider 8 in FIG. 3 and have opposite phases to each other, are supplied.

Reference numerals 13 and 14 are input terminals to which 19 KHZ pilot signals having mutually opposite phases in the composite stereo signal are supplied.

DDA is a pair of differential width circuits 51. 52, to which the above-mentioned reference signal and pilot signal to be phase-compared are supplied.

The differential amplifier circuit 51 includes a switching transistor 53,
54, a width increasing transistor 55, and a constant current transistor 57.

the base of transistor 530 is connected to input terminal 11;
Transistor 540 base is connected to input terminal 12 .

The emitters of transistors 53 and 54 are transistor 5.
The emitter of transistor 55 is connected to the collector of transistor 57 through resistor 56.

The base of transistor 550 is connected to input terminal 13.

The emitter of transistor 57 is connected to power supply 1B.

Reference numeral 59 is a bias power supply input terminal, and the voltage from this terminal is connected to the power supply 1B through a resistor 60 and a diode 58, and is connected to the midpoint between the resistor 60 and the diode 58 or to the base of the transistor 570.

The collector of the transistor 54 is connected to a power supply 1B through a load circuit 61.

This load circuit 61 consists of a series circuit of a diode 63 and a resistor 62 as active elements.

The differential amplification circuit 52 includes a switching transistor 64.
65, a width increasing transistor 66, and a constant current transistor 67.

The base of transistor 640 is connected to input terminal 12;
The base of the transistor 65 is connected to the input terminal 11, and the emitters of the transistors 64 and 65 are connected to the input terminal 11.
The emitter of transistor 66 is connected to the collector of transistor 57 through resistor 67.

The collector of the transistor 64 is connected to the collector of the transistor 53, and is also connected to the power supply 1B through a load circuit 68.

This load circuit 68 consists of a series circuit of a diode 70 and a resistor 69 as active elements.

Further, the collector of the transistor 65 is connected to the transistor 54.
connected to the collector of

The balanced output current of the double-balanced differential amplifier circuit, that is, the sum of the collector currents of transistors 54 and 65 and the sum of the collector currents of transistors 53 and 64 is connected to the first and second current relay circuits (current mirror circuits), respectively. 81 and 82, respectively.

These first and second current relay circuits 81 and 8
The second output current is supplied to third and fourth current relay circuits 83 and 84, respectively.

Also, the first and second current relay circuits 81 . 82 to fourth and third current relay circuits 84 . 83 is applied with current feedback.

Note that the current relay circuit (current mirror circuit) is a circuit in which the collector current of its transistor and the cathode current of its diode are approximately equal.

The first current relay circuit 81 is connected to the diode 6 of the load circuit 61.
3 and transistors 72 and 74.

And transistor 54 . 65 is commonly connected to each base of transistors 72 and 74.

The emitters of transistors 72 and 74 are connected to the power supply +B through resistors 73 and 75, respectively.Resistors 62, 73 and 75 of this first current relay circuit 81 are selected to have equal resistance values.

The second current relay circuit 82 is connected to the diode 7 of the load circuit 68.
0 and transistors 77 and 79.

The collectors of transistors 53 and 64 are commonly connected to the bases of transistors 77 and 79.

Further, the emitters of transistors 77 and 79 are connected to a power supply 1B through resistors 78 and 80, respectively.

The third current relay circuit 83 is composed of a transistor 85 and a diode 87.

The collector of transistor 85 is connected to the collector of transistor 72, and the emitter of transistor 85 is connected to power supply 1B through resistor 86.

The base of transistor 850 is connected to power supply 1B through a series circuit of diode 87 and resistor 88.

The base of transistor 85 is connected to the collector of transistor 77.

The fourth current relay circuit 84 is composed of a transistor 89 and a diode 91.

The emitter of transistor 89 is connected to power supply -B through a resistor 90, and the base of transistor 89 is connected to power supply -B through a series circuit of diode 91 and resistor 92.

The base of transistor 890 is connected to the collector of transistor 74.

Note that resistors 86 and 88 have the same value, and resistor 92
and 90 have the same value.

Then, the positions of the above-mentioned first and second signals are determined from the connection midpoints of the first and third current relay circuits 81 and 83 and the connection midpoints of the second and fourth current relay circuits 82 and 84, respectively. Output terminals 16 and 1 that provide balanced output current based on phase difference
5 is derived.

That is, the output terminal 16 is led out from the connection midpoint between the transistors 72 and 85, and the output terminal 15 is led out from the connection midpoint between the transistors 79 and 89.

Next, another embodiment of the present invention will be described with reference to FIG. 5, but parts corresponding to those of the embodiment of FIG.

In this example, load circuits 61 and 6 of a double-balanced differential amplification circuit are used.
8 is different from that in FIG. 4.

That is, the load circuit 61 includes transistors 95 and 96 and a resistor 97.

The collector of transistor 65 is connected to transistor 9.
6 and the collector of transistor 95.

The collector of transistor 96 is grounded, and the emitter of transistor 96 is connected to the base of transistor 95.

The emitter b' of the transistor 95 is connected to the power supply 1B through the resistor 97.

Then, the base of transistor 950 is connected to transistor 72.
, 740 are commonly connected to each base.

The load circuit 68 also includes transistors 98 . 99 and a resistor 100, the collector of transistor 53 is connected to the base of transistor 990 and the collector of transistor 98.

The collector of transistor 99 is grounded.

The emitter of transistor 99 is connected to the base of transistor 98.

The emitter of transistor 98 is connected to power supply +B through resistor 100.

The base of transistor 9B is the transistor 79.
and 77 bases in common.

Furthermore, in this example, the first to fourth current relay circuits 81, 82
, 83 and 84 are different from their configuration in the case of FIG.

The first current relay circuit 81 is composed of transistors 95 and 96 of the load circuit 61 and transistors 72 and 74.

The emitters of the transistors 72 and 74 are connected to a power source 1B through resistors 73 and 75.

The second current relay circuit 82 also connects transistors 98 . 99 and transistors 77 and 79.

And each emitter of transistors 77 and 79 is connected to resistor 7.
Connected to power supply 10B through 8.80.

The third current relay circuit 83 is composed of transistors 85, 101 and 102.

The collector of transistor 85 is connected to the collector of transistor 72, and the emitter of transistor 85 is connected to resistor 8.
6 to the power supply 1B.

The base of transistor 85 is connected to the base of transistor 102.

The emitter of transistor 102 is connected to power supply -B through resistor 103.

The emitter of transistor 101 is commonly connected to the bases of transistors 85 and 102.

The base of transistor 1010 is connected to the collector of transistor 102.

The collector of transistor 101 is connected to power supply 1B.

Further, the fourth current relay circuit 84 includes transistors 89 and 10.
It consists of 4,105.

The emitter of transistor 89 is connected to power supply 1B through resistor 90.

Transistor 890 base is connected to the base of transistor 105.

The emitter of transistor 105 is connected to power supply 1B through resistor 106.

The base of transistor 104 is connected to the collector of transistor 105.

The collector of transistor 104 is connected to power supply 1B.

Each base of transistors 104 and 101 is connected to each collector of husband transistors 74 and 77.

The input terminal 15 is led out from the connection midpoint between the transistors 79 and 89, and the output terminal 16 is led out from the connection midpoint between the transistors 72 and 85.

The other configurations are the same as those in FIG. 4.

Next, still another embodiment of the present invention will be described with reference to FIG.

In this embodiment, another differential amplifier circuit is provided before the double-balanced differential amplifier circuit, and a 19KHZ reference signal is supplied to the double-balanced differential amplifier circuit through the differential amplifier circuit 110. In this case, the 19KH2 pilot signal is directly supplied to the double-balanced differential amplification circuit.

In FIG. 6 as well, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and redundant explanation will be omitted.

The differential amplification circuit 110 includes amplification transistors 111, 11.
2. Consists of a constant current transistor 115.

The base of transistor 1110 is connected to input terminal 11 and the base of transistor 112 is connected to input terminal 12.

The emitters of transistors 111 and 112 are connected to the collector of transistor 115 through resistors 113 and 114, respectively.

The emitter of transistor 115 is connected to power supply 1B through resistor 116.

59 is a bias DC power input terminal for the transistor 115, and this input terminal 59 is connected to the power supply 1B through a series circuit of a resistor 60 and a diode 58, and the midpoint between the resistor 60 and the diode 58 is connected to the transistor 115. connected to the base of

The collectors of transistors 111 and 112 are connected to a power supply 1B through load circuits 117 and 118, respectively.

Load circuit 117 includes diode 119 and transistor 1
It consists of 21.

The collector of transistor 111 is connected to the emitter of transistor 121 through diode 119, and the collector of transistor 121 is connected to power supply 1B.

Load circuit 118 includes diode 120 and transistor 1
It consists of 21.

The collector of transistor 112 is connected to the emitter of transistor 121 through diode 120 312
2 and 123 are resistors forming a base bias circuit for the transistor 121, and their series circuit is connected between the power supplies 1B and -B.

The collector of transistor 111 is commonly connected to the bases of transistors 53 and 65 of the double-balanced differential amplifier circuit, and the collector of transistor 112 is commonly connected to the bases of transistors 54 and 64.

The rest of the configuration is the same as that shown in FIG. 4, so redundant explanation will be omitted.

No DC potential appears between the output terminals 15 and 16 in the circuits of the embodiments of FIGS. 4, 5 and 6 described above.

Further, since the circuits of each embodiment are driven by two power sources, positive and negative, the output terminals 15 and 16 have almost no DC potential with respect to the ground.

Therefore, as a means for applying a desired DC potential to these output terminals 15 and 16, for example, as shown in the DC amplifier circuits of FIGS. , 157 is effective.

It is also possible to apply a DC potential to the input terminals 158 and 159 using an independent power supply.

According to the above-described phase comparison circuit of the present invention, there is provided a double-balanced differential amplification circuit to which the first and second signals to be phase-compared are supplied, and a double-balanced differential amplification circuit provided in the double-balanced differential amplification circuit. a pair of load circuits including active elements, first and second current mirror circuits to which balanced output currents of the double-balanced differential amplification circuit are respectively supplied, and the first and second current mirrors. It has third and fourth current mirror circuits to which the output current of the circuit is supplied, respectively, current feedback is applied from the first and second current mirror circuits to the fourth and third current mirror circuits, and the above-mentioned A balanced output current according to the phase difference between the first and second signals is obtained from the connection midpoint of the first and third current mirror circuits and the connection midpoint of the second and fourth current mirror circuits. As such, it has the following advantages:

The gain as an amplifier and the DC potential to be applied to the next stage can be set independently, and a balanced output with good DC balance can be obtained.

Furthermore, when the phase comparison circuit according to the present invention is applied to the phase comparator of the multiplex stereo demodulation circuit described above, a balanced output current with good DC balance can be obtained as described above.

Furthermore, when the phase comparator circuit according to the present invention is applied to the phase comparator of the multiplex stereo demodulation circuit described above, a balanced output current of opposite polarity can be obtained, so that a low-pass By inserting the F wave filter, it is possible to easily cancel modulation components other than the 19 KHz pilot signal in the composite stereo signal.

Furthermore, the design of the low-pass wave filter becomes easy.

Furthermore, a signal with good DC balance can be supplied to the DC amplification circuit.

Therefore, the offset and drift of the phase oscillation frequency of the current controlled variable oscillator in FIG. 3 are improved.

In addition, beat interference caused by composite stereo signal components can be reduced, a preamplifier for the PLL can be omitted, and the sensitivity of the PLL can be increased. Although the case of 1 is shown, it goes without saying that a single power supply may also be used.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 and 2 are circuit connection diagrams showing examples of conventional phase comparison circuits, and FIG. 3 is a circuit diagram showing an example of a phase comparison circuit according to the present invention. Block diagrams showing the →ri of the Tux stereo demodulation circuit, Figures 4 and 5
6 and 6 are circuit connection diagrams showing an example of a phase comparator circuit according to the present invention. 61 and 68 are a pair of load circuits including active elements, 8L8
2.83 and 84 are first, second, third and fourth current mirror circuits, respectively.

Claims (1)

[Claims] 1. A pair of load circuits including a double-balanced differential amplification circuit to which first and second signals to be phase-compared are supplied, and an active element provided in the double-balanced differential amplification circuit. and first and second current mirror circuits to which the balanced output currents of the double-balanced differential amplifier circuit are respectively supplied, and output currents of the first and second current mirror circuits are respectively supplied. and third and fourth current mirror circuits, current feedback is applied from the first and second current mirror circuits to the fourth and third current mirror circuits, and the first and third current mirror circuits are provided with current feedback. A balanced output current corresponding to the phase difference between the first and second signals is obtained from the connection midpoint of the mirror circuit and the connection midpoint of the second and fourth current mirror circuits. Phase comparison circuit.