JPH07202872A - Clock recovery device - Google Patents

Abstract

PURPOSE:To realize the clock recovery circuit operated stably with high frequency accuracy even against a reception signal whose transmission speed is high with a complete digital circuit. CONSTITUTION:After a reception signal is converted into a digital signal by an A/D converter 1, a clock phase error detector 2 obtains a clock phase error. An output from a loop filter 3 is divided into high-order bits and low-order bits and the low-order bits not loaded to a down-counter 4 are integrated by an integration device 6. Only when the integration device 6 overflows, an adder 7 adds '1' to the high-order bits being an output of the loop filter and provides an output of a load value to the down-counter 4. The down-counter 4 counts high speed clocks outputted from an oscillator 5 and provides an output of a zero detection signal every time the loaded value reaches zero to set the zero detection signal to be a new load value signal and as a sampling clock for the A/D converter 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock regenerator, and more particularly to a clock regenerator for completely digitizing and reproducing a circuit.

[0002]

2. Description of the Related Art FIG. 2 shows an example in which a conventional clock regenerator is completely composed of digital circuits. The received signal is converted into a digital signal by the A / D converter 1. The sampling of this conversion depends on the recovered clock, which will be explained later. From the sampled data, the clock phase error of the sampling clock is detected by the clock phase error detector 2, filtered by the digital loop filter 3, and then input to the load value input of the down counter 4. When the count value of the down counter 5 becomes zero, a zero detection signal is output, and this zero detection signal is used as a load signal and at the same time is used as the sampling clock.

The counting clock input from the clock oscillator 5 to the down counter 4 is a sufficiently high speed clock 100 times or more as high as the load value receiving clock input from the loop filter 3.

[0004]

However, the frequency accuracy of the sampling clock in this conventional clock regenerator is the resolution of the down counter which can be defined as the ratio of the frequency of the high speed clock and the frequency of the regenerated clock, that is, the number of bits, Will be decided by. This is because even if the resolution of the loop filter is increased, the bits lower than the bit that can be set as the counter load value have to be truncated at the time of setting. Therefore, unless the clock of the received data to be reproduced is sufficiently small, such as about 1/100, compared to the high-speed clock, the frequency accuracy of the sampling clock becomes low, the clock reproduction loop becomes unstable, and the jitter of the reproduced clock becomes large. . Even if the ratio of the received clock to the high speed clock is about 100 to 500, if the noise component on the line is large, sufficient stable operation cannot be obtained.

It is an object of the present invention to provide a clock regenerator which is a completely digital circuit and stably operates with high frequency accuracy even for a received signal having a high transmission rate.

[0006]

To achieve the above object, the clock regenerator of the present invention comprises A / D conversion means for converting an analog reception signal into a digital signal and outputting the digital signal.
A clock phase error detecting means for detecting a clock phase error of the digital signal and outputting the phase error signal; an integrating means for integrating the lower bit signal of the phase error signal and outputting an overflow signal when the integrated value overflows. When an overflow signal is output, an addition unit that adds "1" to the upper bit of the phase error signal and outputs the addition value, an oscillation unit that generates and outputs a clock signal, and a clock with the addition value as a load value And a count means that outputs a zero detection signal when the load value becomes "0" by inputting a signal and counts down. The zero detection signal is used as a load signal for the count means and sampling by the A / D conversion means. It features a clock.

[0007]

Therefore, according to the clock regenerator of the present invention, the signal of the lower bit of the phase error signal converted into the digital signal is integrated, the integrated value is added to the upper bit, and the added value is used as a load value for countdown. Zero detection is performed, and the zero detection signal is the load signal of the counting means,
Moreover, the sampling clock of the A / D conversion means is used. Therefore, the signal of the lower bit is reflected as the sampling signal of the A / D conversion means, and the synchronization between the reproduced clock and the received signal becomes more accurate.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a clock regenerator according to the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, one embodiment of the clock regenerator of the present invention is shown as a block diagram.

The A / D converter 1 converts an analog received signal into a digital signal. The sampling clock for executing this conversion is a signal reproduced from the output signal of the A / D converter 1. The clock phase error detector 2 has A
From the digital data output from the / D converter 1, the clock phase error θ _e is obtained and output, and the loop filter 3
Supply to. The loop filter 3 outputs a loop filter output of frequency w _R based on the input clock phase error θ _e . By setting the output of this loop filter as the sampling frequency of the A / D converter 1, a PLL loop (Phase-Locked Loop) for clock reproduction is constructed.

In this embodiment, the loop filter output is a digital signal composed of an n-bit integer value N _R corresponding to the frequency w _R because all circuits are composed of digital circuits. Of the outputs of the n-bit loop filter 3, only the L-bit (L-bit
≦ n) signal. This value is the integer value N of the upper L bits
_UR (N _UR = N _R / 2 ^nL ) and an integer value N _LR (N _LR = N _R mod 2 ^nL ) of lower [n−L] bits. The lower bit N _LR is input to the [n−L] bit integrator 6.

The integrator 6 holds the overflow value N as an integral value when the value after integration overflows to a value 2 ^{N-L + 1} + N which is 2 ^{N-L + 1} or more, and at the same time, the overflow signal "1". "" Is output, and otherwise "0" is output. The upper bit N _UR is added to the overflow signal of the output of the integrator 6 in the adder 7, and N _UR is input to the load value input of the down counter 4 when the overflow does not occur and N _UR +1 when the overflow occurs. Is output. The down counter 4 inputs the high-speed clock signal of the frequency w _F output from the oscillator 5 to down count, outputs a zero detection signal when the counter value becomes “0”, and outputs the load output from the adder 7. Load the value. Along with this load, the zero detection signal is used as the sampling clock of the A / D converter.

The operation and operating principle of the clock regenerator having the above configuration will be described in detail below. Frequency of received signal w _C
And the oscillation frequency w _F of the oscillator 5, the frequency division ratio R of the down counter 4 which can be synchronized with the sampling clock.
_D becomes R _D = w _F / w _C , but this is not necessarily an integer. Therefore, when R _D is divided into an integer part N _D and a decimal part F _D , the following formula (1) is obtained. R _D = N _D + F _D (1) where; N _D is an integer, 0 ≦ F _D <1

The upper L-bit integer value N _UR and the lower (n−L) -bit integer value N _LR are respectively expressed by equation (2).
And (3). N _UR = N _D (2) N _LR = int (2 ^{N-L + 1} · F _D ) (3) However, int (A) represents the integer part of A.

In the conventional method, since the counter load value is only the integer value N _UR , the reproduced sampling clock frequency has the relationship of the following expression (4). w _F / N _UR = w _F / N _D = w _F / (R _D −F _D ) (w _F / R _D ) · (1 + F _D / R _D ) = w _C (1 + F _D / R _D ) = w _C + Δw (4) Therefore, Δw = w _C · (F _D / R _D ).

Therefore, the clock is deviated from the received clock by Δw, and the stability of the clock recovery loop is lost. In order to prevent this, in the conventional method, there is no choice but to suppress F _D / R _D by increasing the value of the oscillation frequency w _F of the oscillator 5 and reduce the value of Δw, which has a limit. Particularly in a system with a large clock frequency w _C , the sampling frequency w _F must be set higher, which is not practical.

However, in the present embodiment, the value of N _LR is not truncated and integrated and used in the integrator 6, and the counter load value N _D or N _D +1 is set at a ratio according to the value of F _D. According to this procedure, it is possible to equivalently improve the frequency accuracy of the clock to be reproduced. Integrator 6
The probability P _OV of overflowing is as follows. ^{_{P OV = N LR / 2 N}} -L + 1 = F D + ΔF ...... (5) ^{_{where, ΔF = F LD / 2 N}} -L + 1 F LD = 2 N-L + 1 · F D -N LR 0 ≦ F _LD <1

From this, the load average value Nav _L loaded into the down counter 4 is given by the following equation (6). Nav _L = N _D (1-P _OV ) + (N _D +1) P _OV = N _D + P _OV = N _D + F _D + ΔF = R _D + F _LD / 2 ^{N-L + 1} (6)

The load average value Nav _L becomes substantially equal to the ideal frequency division ratio R _D, and the error is F _LD / 2 ^{N-L + 1} . The load average value Nav _L can be reduced without limit by increasing the overflow value N, that is, by increasing the number of bits of the loop filter 3 and the integrator 6. However, the average value Nav _L can be reduced by simply increasing the size of the circuit, which is sufficiently realistic. In this way, the load value to the down counter 4 is F _D
By setting N _D or N _D +1 with a probability corresponding to, it becomes possible to bring the reproduced clock frequency close to a value very close to the reception clock frequency w _C.

During the peak period of the clock of this embodiment, the lower bits of the output of the loop filter which are not loaded in the down counter 4 are integrated by the integrator, and when the integrator overflows, the counter load value is increased by 1 and the loop filter is increased. The effect of the lower bits of 3 is also incorporated in the frequency division of the down counter 4. Therefore, even if the clock recovery circuit is completely composed of a digital circuit, it is possible to obtain a recovered clock extremely matching the frequency of the received signal.

Although the above-described embodiment is a preferred embodiment of the present invention, the present invention is not limited to this, and various modifications can be made without departing from the gist of the present invention. For example, the loop filter is unnecessary in theoretical operation.

[0021]

As is apparent from the above description, in the clock regenerator of the present invention, the signal of the lower bit of the phase error signal is integrated and reflected in the sampling clock of the A / D conversion means. And the synchronization characteristic of the received signal is improved. Therefore, it becomes easy to form a clock recovery circuit that can be stably synchronized with a high-speed received signal with a completely digital circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock regenerator of the present invention.

FIG. 2 is a block diagram showing a circuit configuration example of a conventional completely digital clock regenerator.

[Explanation of symbols]

 1 A / D converter 2 Clock phase error detector 3 Loop filter 4 Down counter 5 High speed oscillator 6 n-L bit integrator 7 Adder

Claims (4)

[Claims] 1. An A / D conversion means for converting an analog reception signal into a digital signal and outputting the digital signal, a clock phase error detection means for detecting a clock phase error of the digital signal and outputting a phase error signal, and the phase. Integrating means for integrating the signal of the lower bit of the error signal and outputting an overflow signal when the integrated value overflows, and "1" for the upper bit of the phase error signal when the overflow signal is output. An adding means for adding and outputting an added value, an oscillating means for generating and outputting a clock signal, and a countdown by inputting the clock signal with the added value as a load value and setting the load value to "0". And a count means for outputting a zero detection signal, wherein the zero detection signal is a load signal for the counting means, and A clock regenerator characterized by using a sampling clock for A / D conversion means. 2. The clock phase error detecting means further has a loop filter for filtering and outputting the phase error signal, and the integrating means integrates the signal filtered by the loop filter. The clock regenerator according to Item 1. 3. The number of high-order bits is less than or equal to the resolution of the counting means.
Alternatively, the clock regenerator according to claim 2. 4. The clock regenerator according to claim 1, wherein the frequency of the clock signal generated by the oscillating means is higher than the frequency of the analog reception signal.