JPH07202077A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07202077A JPH07202077A JP33833493A JP33833493A JPH07202077A JP H07202077 A JPH07202077 A JP H07202077A JP 33833493 A JP33833493 A JP 33833493A JP 33833493 A JP33833493 A JP 33833493A JP H07202077 A JPH07202077 A JP H07202077A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- semiconductor device
- resin
- lead frame
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、エポキシ等の樹脂に
より成形封止される半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device molded and sealed with a resin such as epoxy.
【０００２】[0002]
【従来の技術】半導体集積回路が形成された半導体チッ
プは、通常、パッケージ内に封止された状態で、プリン
ト回路基板上に実装される。この半導体チップのパッケ
ージへの封入方法として、エポキシ等の樹脂により成形
封止する方法がある。この方法によると、リードフレー
ムの中央部分にチップを搭載し、ボンディングした後、
上記樹脂により半導体チップおよびリードフレームを成
形封止する。2. Description of the Related Art A semiconductor chip on which a semiconductor integrated circuit is formed is usually mounted on a printed circuit board in a state of being sealed in a package. As a method of enclosing this semiconductor chip in a package, there is a method of molding and encapsulating with a resin such as epoxy. According to this method, after mounting the chip on the center part of the lead frame and bonding,
The semiconductor chip and the lead frame are molded and sealed with the above resin.
【０００３】[0003]
【発明が解決しようとする課題】ところで、上述したエ
ポキシは、高誘電率の化学樹脂であり、他の物質との摩
擦が起こると内部に静電気の帯電現象が発生する。この
帯電により、エポキシ内の半導体チップに静電誘導が発
生し、電荷が誘起される。図５は、この時のパッケージ
内の状態を示す概念図である。この図において、半導体
チップ１およびリードフレーム２をモールドしたエポキ
シ樹脂３が、他の物体と接触することによって摩擦さ
れ、正に帯電する。それによって、半導体チップ１内部
に静電誘導が発生し、表面近くに負の電荷が誘起され
る。この状態でリード端子４を他の金属に近付けると、
それらが接触する直前に、半導体チップ１内の電荷が金
属ワイヤ５およびリード端子４を介して放電する。この
現象により、半導体チップ１は、内部で電力が消費され
破壊する。By the way, the above-mentioned epoxy is a chemical resin having a high dielectric constant, and when friction with another substance occurs, an electrostatic charging phenomenon occurs inside. Due to this charging, electrostatic induction is generated in the semiconductor chip inside the epoxy, and charges are induced. FIG. 5 is a conceptual diagram showing a state inside the package at this time. In this figure, the epoxy resin 3 in which the semiconductor chip 1 and the lead frame 2 are molded is rubbed and positively charged by coming into contact with another object. As a result, electrostatic induction occurs inside the semiconductor chip 1, and negative charges are induced near the surface. If the lead terminal 4 is brought close to another metal in this state,
Immediately before they contact each other, the electric charge in the semiconductor chip 1 is discharged through the metal wire 5 and the lead terminal 4. Due to this phenomenon, the semiconductor chip 1 consumes power internally and is destroyed.
【０００４】上述したような問題を解決するために、パ
ッケージの摩擦による帯電を軽減する半導体装置が考え
られている。その１つとして、図６に示す半導体装置で
は、摩擦が起こる面積を減少させるために、エポキシ樹
脂３の表面に凹凸が設けられている。あるいは、半導体
チップ内部の電荷が放電するときに発生する電力を効率
的に消費することにより、半導体チップの破壊を防ぐよ
うに、保護回路が設けられた半導体装置も考えられてい
る。しかしながら、これらの半導体装置は、半導体チッ
プの破壊を軽減することはできるが、防止することはで
きないという問題があった。In order to solve the above-mentioned problems, a semiconductor device has been considered which reduces electrification due to friction of the package. As one of them, in the semiconductor device shown in FIG. 6, unevenness is provided on the surface of the epoxy resin 3 in order to reduce the area where friction occurs. Alternatively, a semiconductor device in which a protection circuit is provided so as to prevent destruction of the semiconductor chip by efficiently consuming electric power generated when electric charges inside the semiconductor chip are discharged has been considered. However, these semiconductor devices have a problem that they cannot prevent the damage of the semiconductor chip, although they can reduce the damage.
【０００５】この発明は、このような背景の下になされ
たもので、パッケージの摩擦による帯電から生じる静電
破壊を防止することができる半導体装置を提供すること
を目的とする。The present invention has been made under such a background, and an object thereof is to provide a semiconductor device capable of preventing electrostatic breakdown caused by charging due to friction of a package.
【０００６】[0006]
【課題を解決するための手段】この発明による半導体装
置は、集積回路が形成された半導体チップが導電性のリ
ードフレームの搭載部に搭載され、前記半導体チップお
よび前記リードフレームが樹脂によって成形封止されて
なる半導体装置において、前記集積回路の上部全面に亙
って導電性の層が設けられ、前記導電性の層と前記リー
ドフレームの搭載部とを電気的に接続したことを特徴と
している。In the semiconductor device according to the present invention, a semiconductor chip on which an integrated circuit is formed is mounted on a mounting portion of a conductive lead frame, and the semiconductor chip and the lead frame are molded and sealed with resin. In the semiconductor device thus obtained, a conductive layer is provided over the entire upper surface of the integrated circuit, and the conductive layer and the mounting portion of the lead frame are electrically connected.
【０００７】[0007]
【作用】上記構成によれば、樹脂が摩擦により帯電する
と、導電性の層とリードフレームとの内部に静電誘導が
発生し、電荷が誘起される。この時、半導体チップの集
積回路は、電気的に接続された導電性の層とリードフレ
ームの搭載部とに挟まれているため、樹脂の帯電の影響
を受けることなく、電荷は誘起されない。According to the above structure, when the resin is charged by friction, electrostatic induction is generated inside the conductive layer and the lead frame, and the electric charge is induced. At this time, the integrated circuit of the semiconductor chip is sandwiched between the electrically conductive layer and the mounting portion of the lead frame, so that the charge is not induced without being affected by the charging of the resin.
【０００８】[0008]
【実施例】以下、図面を参照して、この発明の一実施例
について説明する。図１はこの発明の一実施例による半
導体装置の構成を示す図である。この図に示すように、
半導体装置２０には、半導体集積回路の機能を有する部
分である機能部３０、すなわち、基板６、拡散層７、素
子分離絶縁膜８、層間絶縁膜９、配線金属１０、および
保護膜１１が形成されており、その保護膜１１の全面に
金属層１２が形成されている。そして、その金属層１２
の全面に、電気的に絶縁するためのガラス層１３が形成
されている。なお、金属層１２の代わりに導電性ポリイ
ミド等を導電層として用いてもよい。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing the configuration of a semiconductor device according to an embodiment of the present invention. As shown in this figure,
In the semiconductor device 20, a functional portion 30 having a function of a semiconductor integrated circuit, that is, a substrate 6, a diffusion layer 7, an element isolation insulating film 8, an interlayer insulating film 9, a wiring metal 10, and a protective film 11 are formed. The metal layer 12 is formed on the entire surface of the protective film 11. And the metal layer 12
A glass layer 13 for electrical insulation is formed on the entire surface of the. Instead of the metal layer 12, conductive polyimide or the like may be used as the conductive layer.
【０００９】図２は、図１に示す半導体チップ２０をパ
ッケージＰに搭載した様子を示す平面図である。この図
に示すパッケージＰにおいては、半導体チップ２０と、
半導体チップ２０が搭載されるリードフレームの金属ス
テージ１４と、この金属ステージ１４を支持するために
該金属ステージ１４の一部を伸長したサポートバー１
５，１５とが、エポキシ樹脂３によってモールドされて
いる。また、このパッケージＰの両側面には、各々複数
個のリード端子４，４，…が形成されており、半導体チ
ップ２０の上面に形成されている複数個のパッド１６
ａ，１６ａ，…の各々と、金属ワイヤ５によって接続さ
れている。以上のような構成は、従来の半導体装置の製
造方法によって、形成される。更に、半導体チップ２０
の上面には、２個のパッド１６ｂ，１６ｂが形成されて
おり、このパッド１６ｂ，１６ｂとサポートバー１５，
１５とが、金属ワイヤ５によって接続されている。FIG. 2 is a plan view showing a state where the semiconductor chip 20 shown in FIG. 1 is mounted on the package P. In the package P shown in this figure, the semiconductor chip 20 and
A metal stage 14 of a lead frame on which the semiconductor chip 20 is mounted, and a support bar 1 in which a part of the metal stage 14 is extended to support the metal stage 14.
5 and 15 are molded by the epoxy resin 3. A plurality of lead terminals 4, 4, ... Are formed on both side surfaces of the package P, and a plurality of pads 16 formed on the upper surface of the semiconductor chip 20.
, 16a, ... Are connected by a metal wire 5. The above structure is formed by the conventional method of manufacturing a semiconductor device. Furthermore, the semiconductor chip 20
Two pads 16b, 16b are formed on the upper surface of the pad 16b, 16b and the support bar 15,
And 15 are connected by a metal wire 5.
【００１０】図３（ａ）は、図２におけるＡ−Ａ’線断
面図であり、図３（ｂ）は、Ｂ−Ｂ’線断面図である。
図３（ａ）に示すように、半導体チップ２０は、パッド
１６ｂ，１６ｂの部分に対応するガラス層１３が除去さ
れ、金属層１２が露出している。そして、金属ワイヤ５
の一端が上記露出した金属層１２に接続され、他端がサ
ポートバー１５，１５に接続されることにより、金属層
１２とサポートバー１５，１５とが電気的に接続されて
いる。一方、図３（ｂ）に示すように、パッド１６ａ，
１６ａの部分に対応するガラス層１３、金属層１２、お
よび保護膜１１が除去され、金属ワイヤ５，５の一端が
接続されることにより、電極が取り出されるようになっ
ている。FIG. 3 (a) is a sectional view taken along the line AA 'in FIG. 2, and FIG. 3 (b) is a sectional view taken along the line BB'.
As shown in FIG. 3A, in the semiconductor chip 20, the glass layer 13 corresponding to the pads 16b and 16b is removed and the metal layer 12 is exposed. And the metal wire 5
One end of is connected to the exposed metal layer 12 and the other end is connected to the support bars 15 and 15, so that the metal layer 12 and the support bars 15 and 15 are electrically connected. On the other hand, as shown in FIG. 3B, the pads 16a,
The electrode is taken out by removing the glass layer 13, the metal layer 12, and the protective film 11 corresponding to the portion 16a and connecting one end of the metal wires 5 and 5.
【００１１】図４は、上述した半導体チップ２０がモー
ルドされたパッケージＰの電気的な状態を示す概念図で
ある。この図に示すように、他の物質との摩擦により、
エポキシ樹脂３が正に帯電すると、金属層１２および金
属ステージ１４に静電誘導が発生する。そして、金属層
１２の上面、および金属ステージ１４の下面に、負の電
荷が誘起される。ここで、金属層１２と金属ステージ１
４とは金属ワイヤ５によって電気的に接続されているた
め、それらの内側に配置された半導体チップ２０の機能
部３０は、その外側の電界の影響を受けない。従って、
エポキシ樹脂３が帯電しても、機能部３０に電荷は誘起
されず、リード端子４を他の金属に近づけても機能部３
０内には放電電流は流れない。FIG. 4 is a conceptual diagram showing an electrical state of the package P in which the above-mentioned semiconductor chip 20 is molded. As shown in this figure, due to friction with other substances,
When the epoxy resin 3 is positively charged, electrostatic induction is generated in the metal layer 12 and the metal stage 14. Then, negative charges are induced on the upper surface of the metal layer 12 and the lower surface of the metal stage 14. Here, the metal layer 12 and the metal stage 1
Since the metal wires 4 and 4 are electrically connected to each other, the functional portion 30 of the semiconductor chip 20 arranged inside thereof is not affected by the electric field outside thereof. Therefore,
Even if the epoxy resin 3 is charged, the electric charge is not induced in the functional portion 30, and even if the lead terminal 4 is brought close to another metal, the functional portion 3
No discharge current flows in 0.
【００１２】[0012]
【発明の効果】以上説明したように、この発明によれ
ば、集積回路が形成された半導体チップが導電性のリー
ドフレームの搭載部に搭載され、前記半導体チップおよ
び前記リードフレームが樹脂によって成形封止されてな
る半導体装置において、前記集積回路の上部全面に亙っ
て導電性の層が設けられ、前記導電性の層と前記リード
フレームの搭載部とを電気的に接続したので、樹脂が摩
擦により帯電しても、半導体チップの集積回路は、電気
的に接続された導電性の膜と支持手段とに挟まれている
ため、樹脂の帯電の影響を受けることなく、電荷は誘起
されない。そのため、この電荷が放電されることにより
半導体チップ内で電力が消費され、半導体チップが破壊
される、といった静電破壊の発生を防止することができ
るという効果がある。As described above, according to the present invention, the semiconductor chip on which the integrated circuit is formed is mounted on the mounting portion of the conductive lead frame, and the semiconductor chip and the lead frame are molded and sealed with resin. In the semiconductor device thus stopped, a conductive layer is provided over the entire upper surface of the integrated circuit, and the conductive layer and the mounting portion of the lead frame are electrically connected to each other. Even when electrically charged by, the integrated circuit of the semiconductor chip is sandwiched between the electrically conductive film and the supporting means that are electrically connected, so that the electric charge is not induced by the influence of the electrification of the resin. Therefore, there is an effect that it is possible to prevent the occurrence of electrostatic breakdown such that the electric power is consumed in the semiconductor chip due to the discharge of the electric charge and the semiconductor chip is destroyed.
【図１】 この発明の一実施例による半導体装置におけ
る半導体チップ２０の構成を示す断面図である。FIG. 1 is a sectional view showing a configuration of a semiconductor chip 20 in a semiconductor device according to an embodiment of the present invention.
【図２】 同実施例による半導体装置の平面図である。FIG. 2 is a plan view of a semiconductor device according to the same example.
【図３】 同実施例による半導体装置の断面図である。FIG. 3 is a cross-sectional view of the semiconductor device according to the same example.
【図４】 同実施例による半導体装置のパッケージＰ内
部の電気的な状態を示す概念図である。FIG. 4 is a conceptual diagram showing an electrical state inside a package P of the semiconductor device according to the embodiment.
【図５】 従来の半導体装置のパッケージＰ内部の電気
的な状態を示す概念図である。FIG. 5 is a conceptual diagram showing an electrical state inside a package P of a conventional semiconductor device.
【図６】 従来の半導体装置のエポキシ樹脂３の一例を
示す概略図である。FIG. 6 is a schematic view showing an example of an epoxy resin 3 of a conventional semiconductor device.
３……エポキシ樹脂、４……リード端子、５……金属ワ
イヤ、１２……金属層、 １３……ガラス層、１４……
金属ステージ、１５……サポートバー、１６ａ，１６ｂ
……パッド3 ... Epoxy resin, 4 ... Lead terminal, 5 ... Metal wire, 12 ... Metal layer, 13 ... Glass layer, 14 ...
Metal stage, 15 ... Support bar, 16a, 16b
……pad
Claims (1)
電性のリードフレームの搭載部に搭載され、前記半導体
チップおよび前記リードフレームが樹脂によって成形封
止されてなる半導体装置において、 前記集積回路の上部全面に亙って導電性の層が設けら
れ、前記導電性の層と前記リードフレームの搭載部とを
電気的に接続したことを特徴とする半導体装置。1. A semiconductor device in which a semiconductor chip on which an integrated circuit is formed is mounted on a mounting portion of a conductive lead frame, and the semiconductor chip and the lead frame are molded and sealed with a resin. A semiconductor device, wherein a conductive layer is provided over the entire upper surface, and the conductive layer and the mounting portion of the lead frame are electrically connected.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5338334A JP2755148B2 (en) | 1993-12-28 | 1993-12-28 | Semiconductor device |
| TW83111810A TW248611B (en) | 1993-12-28 | 1994-12-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5338334A JP2755148B2 (en) | 1993-12-28 | 1993-12-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07202077A true JPH07202077A (en) | 1995-08-04 |
| JP2755148B2 JP2755148B2 (en) | 1998-05-20 |
Family
ID=18317178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5338334A Expired - Fee Related JP2755148B2 (en) | 1993-12-28 | 1993-12-28 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2755148B2 (en) |
| TW (1) | TW248611B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6248657B1 (en) | 1998-03-13 | 2001-06-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57210646A (en) * | 1981-06-19 | 1982-12-24 | Seiko Epson Corp | Resin-sealed semiconductor device |
-
1993
- 1993-12-28 JP JP5338334A patent/JP2755148B2/en not_active Expired - Fee Related
-
1994
- 1994-12-17 TW TW83111810A patent/TW248611B/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57210646A (en) * | 1981-06-19 | 1982-12-24 | Seiko Epson Corp | Resin-sealed semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6248657B1 (en) | 1998-03-13 | 2001-06-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method for manufacturing the same |
| KR100306858B1 (en) * | 1998-03-13 | 2001-11-17 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2755148B2 (en) | 1998-05-20 |
| TW248611B (en) | 1995-06-01 |
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