JPH0590333A - Film mount type semiconductor device - Google Patents
Film mount type semiconductor deviceInfo
- Publication number
- JPH0590333A JPH0590333A JP24585291A JP24585291A JPH0590333A JP H0590333 A JPH0590333 A JP H0590333A JP 24585291 A JP24585291 A JP 24585291A JP 24585291 A JP24585291 A JP 24585291A JP H0590333 A JPH0590333 A JP H0590333A
- Authority
- JP
- Japan
- Prior art keywords
- film
- lead
- semiconductor device
- conductive pattern
- static electricity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体チップを、TA
B(Tape Automated Bonding)
方式によってフィルム上に搭載した半導体装置に於ける
リード配線部の構造及び電気的特性検査方法に関する。The present invention relates to a semiconductor chip, TA
B (Tape Automated Bonding)
The present invention relates to a structure of a lead wiring portion in a semiconductor device mounted on a film by a method and an electric characteristic inspection method.
【0002】[0002]
【従来の技術】従来、TAB方式によって半導体チップ
をフィルム上に搭載し、このフィルムを適宣カットして
フィルム上にあらかじめ形成されたリード配線を介して
外部回路などに接続する方法がある。2. Description of the Related Art Conventionally, there is a method in which a semiconductor chip is mounted on a film by the TAB method, the film is appropriately cut, and the film is connected to an external circuit or the like through lead wiring formed in advance on the film.
【0003】このフィルム型半導体装置の平坦構造を図
3に示す。The flat structure of this film type semiconductor device is shown in FIG.
【0004】ポリィミド製のフィルムで形成されたテー
プキャリア201上には、半導体チップ202を収容す
るためのデバイスホール204と、テープ搬送用のスプ
ロケットホール205が形成されており、テープキャリ
ア201の表面上には、予め半導体チップ202上に形
成されたバンプ電極に対応した数のリード配線203が
印刷形成されている。A device hole 204 for accommodating a semiconductor chip 202 and a sprocket hole 205 for carrying a tape are formed on a tape carrier 201 formed of a polyimide film. The lead wires 203 corresponding to the bump electrodes previously formed on the semiconductor chip 202 are printed and formed on the.
【0005】このフィルム実装型半導体装置に於ては、
半導体チップ202上に形成されたバンプ電極に接続さ
れたリード配線203は、個々に独立し、かつ、電位的
にもオープン状態となっていた。In this film mounting type semiconductor device,
The lead wirings 203 connected to the bump electrodes formed on the semiconductor chip 202 were individually independent and were in an open state in terms of potential.
【0006】[0006]
【発明が解決しようとする課題】しかしながら、上記フ
ィルム実装型半導体装置に於ては、リード配線203が
オープン状態で電気的に不安定であることより、テープ
キャリア201自体が静電気により帯電し易く、静電気
が任意のリード配線203に印可された場合、テープキ
ャリアに実装された半導体チップの集積回路素子が、破
壊されてしまうという問題点を有していた。However, in the above film mounting type semiconductor device, since the lead wire 203 is electrically unstable in the open state, the tape carrier 201 itself is easily charged by static electricity, When static electricity is applied to an arbitrary lead wire 203, the integrated circuit element of the semiconductor chip mounted on the tape carrier is destroyed.
【0007】したがって、フィルム実装型半導体装置の
製造に於ては、人体アース、製造設備のアース、イオン
アナライザーによる除電等の静電対策が必要であり、ま
た半導体装置の静電気破壊による信頼性低下をまねいて
いた。Therefore, in the manufacture of the film-mounted semiconductor device, it is necessary to take measures against static electricity such as earthing of the human body, earthing of the manufacturing equipment, static elimination by an ion analyzer, and deterioration of reliability due to electrostatic breakdown of the semiconductor device. I was imitating.
【0008】そこで、本発明は上記問題を解決するもの
であり、その課題は、リード配線203を電気的に安定
させることによって、静電気が印可された時の電荷を逃
がす経路を持ったフィルム実装型半導体装置を提供する
ことにある。Therefore, the present invention is to solve the above-mentioned problem, and its problem is to electrically stabilize the lead wiring 203 to provide a film mounting type having a path for discharging charges when static electricity is applied. It is to provide a semiconductor device.
【0009】[0009]
【課題を解決するための手段】上記課題を解決するため
に、フィルム上に半導体チップを搭載し、半導体チップ
に接続された複数の配線からなるリードパターンが形成
されたフィルム実装型半導体装置に於て、本発明が講じ
た手段は、テープキャリア周辺部に導電性パターン部を
配置し、搬送用スプロケットを介して接地電位を与え、
更にそれぞれのリードパターンをこの導電性パターンに
接続するものである。In order to solve the above problems, in a film mounting type semiconductor device, a semiconductor chip is mounted on a film and a lead pattern consisting of a plurality of wirings connected to the semiconductor chip is formed. Then, the means taken by the present invention is to arrange a conductive pattern portion in the peripheral portion of the tape carrier, and to apply a ground potential via a sprocket for conveyance,
Further, each lead pattern is connected to this conductive pattern.
【0010】[0010]
【実施例】次に、添付図面を参照して本発明の実施例を
説明する。Embodiments of the present invention will now be described with reference to the accompanying drawings.
【0011】(実施例1)図1は、フィルム実装型半導
体装置の実施例を示す平面図である。テープキャリア1
01のほぼ中央部にはデバイスホール104、上下端部
にはスプロケットホール102が打ち抜き形成されてい
る。半導体のバンプ電極と接続されたリード配線103
は、テープ周辺に配置され、搬送用スプロケットを介し
て接地電位を与えられる導電性パターン105に接続用
導電性パターン106を介して接続される。従って、こ
のリード配線103は電位的に接地され、静電気が製造
工程中に印可されても接地側に逃がす電気的経路を持つ
ことになる。(Embodiment 1) FIG. 1 is a plan view showing an embodiment of a film mounting type semiconductor device. Tape carrier 1
A device hole 104 is punched out at substantially the center of 01, and a sprocket hole 102 is punched at the upper and lower ends. Lead wiring 103 connected to semiconductor bump electrodes
Is arranged around the tape and is connected to the conductive pattern 105 to which a ground potential is applied via the transport sprocket via the conductive pattern for connection 106. Therefore, the lead wire 103 is electrically grounded and has an electric path through which the static electricity is released to the ground side even if static electricity is applied during the manufacturing process.
【0012】一方、最終電気的特性検査工程では、検査
前に各々のリード配線103間及びテープ周辺に配置さ
れた導電性パターン105に接続している接続用導電性
パターン106を打ち抜くことにより、各リード配線を
電気的に絶縁させ、独立した電極として電気的特性検査
を行なうことができる。On the other hand, in the final electrical characteristic inspection step, the conductive patterns for connection 106 connected to the conductive patterns 105 arranged between the lead wirings 103 and around the tape are punched out before the inspection. It is possible to electrically insulate the lead wiring and perform electrical characteristic inspection as an independent electrode.
【0013】(実施例2)次に、図2を参照して本発明
によるフィルム実装型半導体装置の実施例2を説明す
る。(Second Embodiment) Next, a second embodiment of the film mounting type semiconductor device according to the present invention will be described with reference to FIG.
【0014】この実施例に於ては、接続用導電性パター
ン106以外は図1に示す実施例1と同一であり、説明
は省略する。This embodiment is the same as the first embodiment shown in FIG. 1 except for the conductive pattern 106 for connection, and the description thereof will be omitted.
【0015】図2に於て、接続用導電パターン106
は、リード配線外端部より各配線パターンを一括して、
接地導電パターン105に接続し、各配線パターンを電
位的に接地する。また、四方にリード配線が配置されて
いる場合、両側に配置された接地用導電パターンを結ぶ
新たな接地用導電パターンを設ける。In FIG. 2, the conductive pattern 106 for connection is used.
Is a batch of each wiring pattern from the outer end of the lead wiring,
It is connected to the ground conductive pattern 105 and each wiring pattern is electrically grounded. When the lead wirings are arranged on all sides, new grounding conductive patterns connecting the grounding conductive patterns arranged on both sides are provided.
【0016】最終電気的特性検査時には、検査前に接地
用導電パターン一括でを抜き、各リード配線を電気的に
独立させる。この場合、一括した接地電源パターン10
5を打ち抜くため、実施例1に要求されるほどの高い打
ち抜き精度は必要としない。At the time of the final electrical characteristic inspection, the grounding conductive patterns are collectively removed before the inspection so that the lead wirings are electrically independent. In this case, the ground power supply pattern 10
Since 5 is punched out, the punching precision as high as that required in the first embodiment is not required.
【0017】[0017]
【発明の効果】以上述べたように、本発明によれば、テ
ープキャリアに実装された半導体ペレットの集積回路素
子に静電気による過大電流が加わらないため、集積回路
素子の静電気破壊を確実に防止できる。As described above, according to the present invention, since an excessive current due to static electricity is not applied to the integrated circuit element of the semiconductor pellet mounted on the tape carrier, electrostatic breakdown of the integrated circuit element can be surely prevented. ..
【図1】本発明によるフィルム型半導体装置の実施例1
を示す平面図である。FIG. 1 is a first embodiment of a film type semiconductor device according to the present invention.
FIG.
【図2】本発明によるフィルム型半導体装置の実施例2
を示す平面図である。FIG. 2 is a second example of the film type semiconductor device according to the present invention.
FIG.
【図3】従来のフィルム型半導体装置の平坦構造を示す
平面図である。FIG. 3 is a plan view showing a flat structure of a conventional film type semiconductor device.
101 テープキャリア 102 スプロケットホール 103 リード配線 104 デバイスホール 105 導電性パターン 106 接地用導電性パタ−ン 201 テープキャリア 202 半導体チップ 203 リード配線 204 デバイスホール 205 スプロケットホール 101 tape carrier 102 sprocket hole 103 lead wiring 104 device hole 105 conductive pattern 106 conductive pattern for ground 201 tape carrier 202 semiconductor chip 203 lead wiring 204 device hole 205 sprocket hole
Claims (2)
導体チップに接続された複数の配線からなるリ−ドパタ
−ンが形成されているフィルム実装型半導体装置に於
て、前記リードパターンをフィルム周辺部に設けた導電
性パターンに接続することを特徴とするフィルム実装型
半導体装置。1. A film mounting type semiconductor device in which a semiconductor chip is mounted on a film, and a lead pattern comprising a plurality of wirings connected to the semiconductor chip is formed. A film-mounted semiconductor device, which is connected to a conductive pattern provided in a peripheral portion.
に於て、リードパタ−ンとフィルム周辺部に設けた導電
性パターンとの接続部を、電気的特性検査時にパンチで
抜き、電気的特性検査を行なうことを特徴とするフィル
ム実装型半導体装置。2. The film mounting type semiconductor device according to claim 1, wherein the connecting portion between the lead pattern and the conductive pattern provided on the peripheral portion of the film is punched out at the time of the electric characteristic inspection, and the electric characteristic is obtained. A film-mounted semiconductor device characterized by being inspected.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24585291A JPH0590333A (en) | 1991-09-25 | 1991-09-25 | Film mount type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24585291A JPH0590333A (en) | 1991-09-25 | 1991-09-25 | Film mount type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0590333A true JPH0590333A (en) | 1993-04-09 |
Family
ID=17139803
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24585291A Pending JPH0590333A (en) | 1991-09-25 | 1991-09-25 | Film mount type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0590333A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09283572A (en) * | 1996-04-17 | 1997-10-31 | Nec Corp | Film carrier semiconductor device |
KR20010018949A (en) * | 1999-08-24 | 2001-03-15 | 마이클 디. 오브라이언 | Circuit board for semiconductor package |
KR100381844B1 (en) * | 1998-08-31 | 2003-07-10 | 앰코 테크놀로지 코리아 주식회사 | Circuit Tape for Semiconductor Package |
JP2009252964A (en) * | 2008-04-04 | 2009-10-29 | Oki Semiconductor Co Ltd | Tape carrier, semiconductor device, and position shift determining method |
-
1991
- 1991-09-25 JP JP24585291A patent/JPH0590333A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09283572A (en) * | 1996-04-17 | 1997-10-31 | Nec Corp | Film carrier semiconductor device |
KR100381844B1 (en) * | 1998-08-31 | 2003-07-10 | 앰코 테크놀로지 코리아 주식회사 | Circuit Tape for Semiconductor Package |
KR20010018949A (en) * | 1999-08-24 | 2001-03-15 | 마이클 디. 오브라이언 | Circuit board for semiconductor package |
JP2009252964A (en) * | 2008-04-04 | 2009-10-29 | Oki Semiconductor Co Ltd | Tape carrier, semiconductor device, and position shift determining method |
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