JPH07201911A - Tape carrier package - Google Patents

Tape carrier package

Info

Publication number
JPH07201911A
JPH07201911A JP5337601A JP33760193A JPH07201911A JP H07201911 A JPH07201911 A JP H07201911A JP 5337601 A JP5337601 A JP 5337601A JP 33760193 A JP33760193 A JP 33760193A JP H07201911 A JPH07201911 A JP H07201911A
Authority
JP
Japan
Prior art keywords
carrier tape
tape
beam leads
supported
linear conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5337601A
Other languages
Japanese (ja)
Inventor
Atsuhiro Horii
篤宏 堀井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Original Assignee
Fujikura Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd filed Critical Fujikura Ltd
Priority to JP5337601A priority Critical patent/JPH07201911A/en
Publication of JPH07201911A publication Critical patent/JPH07201911A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

PURPOSE:To facilitate a bump bonding operation by arranging and fixing a linear conductor in a bridge state in which the end of each linear conductor passes through a hole and is supported by a carrier tape. CONSTITUTION:A plurality of beam leads (linear conductor 13) provided in a bridge state that beam leads cross a long hole 11 to interconnect a chip mounting part 12 and a carrier tape 10 on the outside thereof are arranged and fixed in parallel to each other. Thereby, since the tip of the end 13a of the beam leads is supported on both sides of the long hole II, the positional accuracy of the smoothing quality, the pitch and the like of the beam leads 13 is kept and advantageous for bump connection. The tip of the end 13a of the beam leads 13 is supported in the carrier tape 10 and sealed with a resist ink layer 16 to prevent the concentration of a current density into the end 13a of the beam leads 13, so that the unusual precipitation may be prevented. Therefore, the bump connection with an electrode is easy and at the same time the separation and the like in the bump connection part are prevented to increase reliability.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は導体の支持構造の改善を
図ったテープキャリアパッケージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tape carrier package having an improved conductor support structure.

【0002】[0002]

【従来の技術】近年、大型コンピュータ等に使用される
半導体として、実装技術の改善を図ったテープキャリア
パッケージが多用されている。このテープキャリアパッ
ケージは、例えば、図5および図6に示すように構成さ
れたものである。図中符号1は、キャリアテープであ
り、このキャリアテープ1には、所定間隔おきにデバイ
スホール2・2…が形成されている。キャリアテープ1
上には、その先端を前記デバイスホール2に突出させた
状態に複数のビームリード(線状導体)が並列状態に配
置・固定されている。前記ビームリード3には、前記デ
バイスホール2に位置させたベアチップIC(ICチッ
プ)4の電極がバンプ5を介して接続されている。前記
ビームリード3の端部3aを除く部分には、レジストイ
ンク(絶縁層)6が形成されている。ベアチップIC4
とキャリアテープ1との間には、前記ベアチップIC4
の電極とビームリード3との接続部を覆うように、かつ
前記デバイスホール2の領域全体を埋設するように封止
樹脂7が固着されている。
2. Description of the Related Art In recent years, tape carrier packages with improved packaging technology have been widely used as semiconductors used in large computers and the like. This tape carrier package is configured as shown in FIGS. 5 and 6, for example. In the figure, reference numeral 1 is a carrier tape, and the carrier tape 1 has device holes 2.2 formed at predetermined intervals. Carrier tape 1
A plurality of beam leads (linear conductors) are arranged and fixed on the upper side in a state where the tip ends thereof are projected into the device hole 2. An electrode of a bare chip IC (IC chip) 4 located in the device hole 2 is connected to the beam lead 3 via a bump 5. A resist ink (insulating layer) 6 is formed on a portion of the beam lead 3 excluding the end portion 3a. Bare chip IC4
Between the carrier tape 1 and the carrier tape 1
A sealing resin 7 is fixed so as to cover the connection between the electrode and the beam lead 3 and to bury the entire area of the device hole 2.

【0003】このテープキャリアパッケージは、前記デ
バイスホール2を有するキャリアテープ1にビームリー
ド3を形成し、その後このビームリード3にレジストイ
ンク層(絶縁層)6を形成するとともに、ビームリード
3の端部3aにベアチップIC5をバンプ5を介して接
続し、最後に封止樹脂7を固着させて製造されるもので
ある。
In this tape carrier package, a beam lead 3 is formed on a carrier tape 1 having the device hole 2, a resist ink layer (insulating layer) 6 is formed on the beam lead 3, and the end of the beam lead 3 is formed. It is manufactured by connecting the bare chip IC 5 to the portion 3a via the bump 5 and finally fixing the sealing resin 7.

【0004】[0004]

【発明が解決しようとする課題】ところで、前記テープ
キャリアパッケージにおいては、ビームリード3にはフ
ァイン回路を形成するために通常非常に薄い銅箔が用い
られているから、ビームリード3のデバイスホール2よ
りオーバーハングした部分の強度は非常に弱く簡単な力
で変形してしまうために、ビームリード3の端部3aの
平滑性やピッチの位置精度の保持が難しくバンプボンデ
ィング作業が困難になるケースが生じていた。また、ビ
ームリード3の端部3aにはボンディングのために鍍金
処理を施すが、この鍍金処理においてビームリード3の
端部3aに電流密度の集中によって鍍金層の異常析出が
起きやすく、パターンの混線や、各ビームリード3のバ
ンプ5に対する相対位置がばらついたりして、バンプ接
続の難易度上昇の原因となっていた。
In the tape carrier package, since the beam lead 3 is usually made of a very thin copper foil to form a fine circuit, the device hole 2 of the beam lead 3 is used. Since the strength of the overhanged portion is very weak and is deformed by a simple force, it is difficult to maintain the smoothness of the end portion 3a of the beam lead 3 and the positional accuracy of the pitch, which makes it difficult to perform the bump bonding work. It was happening. Further, the end portion 3a of the beam lead 3 is subjected to a plating treatment for bonding. In this plating treatment, the concentration of the current density at the end portion 3a of the beam lead 3 tends to cause abnormal deposition of the plating layer, and thus the pattern mixing Or, the relative position of each beam lead 3 with respect to the bump 5 is varied, which causes the increase in difficulty of bump connection.

【0005】本発明は、前述の課題に鑑みてなされたも
ので、バンプボンディング作業が容易なテープキャリア
パッケージを提供することを目的とするものである。
The present invention has been made in view of the above problems, and an object of the present invention is to provide a tape carrier package in which bump bonding work is easy.

【0006】[0006]

【課題を解決するための手段】請求項1記載のテープキ
ャリアパッケージでは、キャリアテープ上に複数の線状
導体が並列に配置・固定され、該複数の線状導体の端部
にICチップの電極がバンプを介して接続され、前記複
数の線状導体に絶縁層が被覆され、前記ICチップと前
記キャリアテープとの間に前記電極と線状導体との接続
部を覆って樹脂が固着されたテープキャリアパッケージ
において、前記キャリアテープに前記複数の線状導体の
端部を横切る方向に孔が形成され、該複数の線状導体の
端部が該孔を通って先端が該キャリアテープに支持され
る架橋状態に配置・固定されていることを前記課題の解
決手段とした。
According to a first aspect of the tape carrier package of the present invention, a plurality of linear conductors are arranged and fixed in parallel on a carrier tape, and an electrode of an IC chip is provided at an end of the plurality of linear conductors. Are connected via bumps, the plurality of linear conductors are covered with an insulating layer, and a resin is fixed between the IC chip and the carrier tape so as to cover the connection portion between the electrodes and the linear conductors. In the tape carrier package, holes are formed in the carrier tape in a direction crossing the ends of the plurality of linear conductors, the ends of the plurality of linear conductors pass through the holes, and the tips are supported by the carrier tape. It was arranged and fixed in a cross-linked state as the means for solving the above problems.

【0007】[0007]

【作用】本発明のテープキャリアパッケージによれば、
各線状導体の端部が孔を通って先端が該キャリアテープ
に支持される架橋状態に配置・固定されているので、両
端支持梁のように応力を発揮して変形耐力を発揮する。
また、線状導体の両端がキャリアテープに接して電気的
絶縁されているので、鍍金の際に線状導体先端の電流密
度集中が抑さえられる。
According to the tape carrier package of the present invention,
Since the ends of the respective linear conductors are arranged and fixed in a bridged state in which the ends pass through the holes and the ends are supported by the carrier tape, stress is exerted like a beam supporting both ends to exert deformation resistance.
Further, since both ends of the linear conductor are in contact with the carrier tape and electrically insulated, current density concentration at the tip of the linear conductor can be suppressed during plating.

【0008】[0008]

【実施例】以下本発明の一実施例を、図1ないし図4を
参照して説明する。図1・図2中において、符号10は
キャリアテープであり、このキャリアテープ10には、
該キャリアテープ10において4個の長孔11により画
成されてなる概略正方形状のチップ取り付け部12が所
定間隔おきに形成されている。このチップ取り付け部1
2は、正方形の各辺部分のそれぞれに前記長孔11が位
置し、これら長孔11によってチップ取り付け部12の
外側のキャリアテープ10と仕切られているとともに、
正方形の各角部分が隣接する二つの長孔11・11が不
連続になっている部分において、チップ取り付け部12
の外側のキャリアテープ10と連続している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. In FIGS. 1 and 2, reference numeral 10 is a carrier tape, and the carrier tape 10 includes:
In the carrier tape 10, chip mounting portions 12 each having a substantially square shape defined by four elongated holes 11 are formed at predetermined intervals. This tip mounting part 1
In No. 2, the long holes 11 are located at the respective side portions of the square, and the long holes 11 separate the carrier tape 10 on the outside of the chip mounting portion 12, and
In the part where the two long holes 11 and 11 where each corner part of the square is adjacent are discontinuous, the chip mounting part 12
Is continuous with the outer carrier tape 10.

【0009】前記キャリアテープ10上には、前記長孔
11を横断して前記チップ取り付け部12とその外側の
キャリアテープ10との間を接続する架橋状態に設けら
れたビームリード(線状導体)13が複数並列状態に配
置・固定されている。前記ビームリード13の端部13
aは、前記チップ取り付け部12に位置させたベアチッ
プIC(ICチップ)14の電極がバンプ15を介して
接続されている。前記ビームリード13の前記長孔11
に臨む領域を除く部分は、レジストインク層(絶縁層)
16の層によって覆われている。ベアチップIC14と
キャリアテープ10との間には、前記ベアチップIC1
4の電極とビームリード13との接続部を覆いかつ前記
長孔11の領域全体を埋設するように封止樹脂17が固
着されている。
Beam leads (linear conductors) provided on the carrier tape 10 in a bridging state for connecting the chip mounting portion 12 and the carrier tape 10 on the outside thereof across the elongated hole 11. A plurality of 13 are arranged and fixed in parallel. The end 13 of the beam lead 13
In a, the electrodes of the bare chip IC (IC chip) 14 located in the chip mounting portion 12 are connected via bumps 15. The elongated hole 11 of the beam lead 13
The area other than the area facing the resist ink layer (insulating layer)
It is covered by 16 layers. The bare chip IC 1 is provided between the bare chip IC 14 and the carrier tape 10.
A sealing resin 17 is fixed so as to cover the connecting portion between the electrode 4 and the beam lead 13 and to fill the entire area of the elongated hole 11.

【0010】このテープキャリアパッケージの製造方法
としては、前記長孔11を有するキャリアテープ10に
ビームリード13を形成し、このビームリード13の端
部13aの長孔11に臨む領域以外の部分にレジストイ
ンク層16層を形成すると共に、該ビームリード13の
端部13aにバンプ15を介してベアチップIC14を
接続し、最後に封止樹脂17を固着させてバンプ接続部
分全体を封止する。なお、この製造方法において、前記
ビームリード13の端部13aには、金鍍金等の鍍金を
施す。
As a method of manufacturing this tape carrier package, a beam lead 13 is formed on the carrier tape 10 having the elongated hole 11 and a resist is applied to a portion other than a region of the end portion 13a of the beam lead 13 facing the elongated hole 11. The ink layer 16 is formed, and the bare chip IC 14 is connected to the end 13a of the beam lead 13 via the bump 15. Finally, the sealing resin 17 is fixed to seal the entire bump connecting portion. In this manufacturing method, the end portion 13a of the beam lead 13 is plated with gold or the like.

【0011】以下、本実施例の作用および効果を説明す
る。前記テープキャリアパッケージによれば、ビームリ
ード13の端部13aの先端が長孔11の両側において
支持されているので、ビームリード13の平滑性、ピッ
チ等の位置精度が保持され、バンプ接続に有利である。
また、ビームリード13に鍍金処理を施す場合には、ビ
ームリード13の端部13aの先端がキャリアテープ1
0に支持され、しかもレジストインク層16で封止され
て、ビームリード13の端部13aへの電流密度の集中
を防止して鍍金層の異常析出が防がれるので、ビームリ
ード13の鍍金による厚みおよび強度のばらつきが少な
くビームリード13とベアチップIC14の電極とのバ
ンプ接続が容易であるとともに、各ビームリード13か
らベアチップIC14の電極に加えられる押圧力の強度
のばらつきも少なくなり、バンプ接続部分の剥離等が防
止されて信頼性が向上する。加えて、図2に示すよう
に、ベアチップIC14がチップ取り付け部12に支持
されて少量の封止樹脂17によって安定に固定されるの
で、封止樹脂17の封止高が抑制されてパッケージの小
型化に有利である上、従来のデバイスホール2の様に開
口部が大きくないので、ビームリード13とベアチップ
IC14の電極との接続部を封止する際に封止樹脂の染
みだしを抑さえることができる。
The operation and effect of this embodiment will be described below. According to the tape carrier package, since the ends of the end portions 13a of the beam leads 13 are supported on both sides of the elongated hole 11, the smoothness of the beam leads 13 and positional accuracy such as pitch are maintained, which is advantageous for bump connection. Is.
When the beam lead 13 is plated, the tip of the end portion 13 a of the beam lead 13 is the carrier tape 1.
It is supported by 0 and is sealed with the resist ink layer 16 to prevent current density from concentrating on the end portion 13a of the beam lead 13 and prevent abnormal deposition of the plating layer. The variation in thickness and strength is small, and the bump connection between the beam lead 13 and the electrode of the bare chip IC 14 is easy, and the variation in the strength of the pressing force applied from each beam lead 13 to the electrode of the bare chip IC 14 is small, and the bump connection portion The peeling is prevented and the reliability is improved. In addition, as shown in FIG. 2, the bare chip IC 14 is supported by the chip mounting portion 12 and is stably fixed by a small amount of the sealing resin 17, so that the sealing height of the sealing resin 17 is suppressed and the package size is reduced. Moreover, since the opening is not large like the conventional device hole 2, the exudation of the sealing resin is suppressed when the connection between the beam lead 13 and the electrode of the bare chip IC 14 is sealed. You can

【0012】なお、前記長孔11の形状は、図1および
図2に示す以外の形状であってもよい。
The elongated hole 11 may have a shape other than that shown in FIGS.

【0013】図3および図4は、本発明の別の実施例を
示す図である。これらの図に示す実施例は、キャリアテ
ープ10のチップ取り付け部13上にベタパターン18
を形成し、このベタパターン18をGNDレベルの複数
のームリード19に接続した例である。ベタパターン1
8の上面側にはレジストインク層16が形成されてい
る。このテープキャリアパッケージによれば、ベタパタ
ーン18からなるグランドプレーンの存在により、電気
的特性の安定な高品質の製品を提供することが可能であ
る。ベタパターン18は、VDD等の電源パターンとし
て用いることも出来る。
3 and 4 are views showing another embodiment of the present invention. In the embodiment shown in these figures, the solid pattern 18 is formed on the chip mounting portion 13 of the carrier tape 10.
Is formed and the solid pattern 18 is connected to a plurality of ground leads 19 of GND level. Solid pattern 1
A resist ink layer 16 is formed on the upper surface side of 8. According to this tape carrier package, it is possible to provide a high-quality product with stable electric characteristics due to the presence of the ground plane formed of the solid pattern 18. The solid pattern 18 can also be used as a power supply pattern such as VDD.

【0014】[0014]

【発明の効果】以上説明したように、請求項1記載のテ
ープキャリアパッケージによれば、線状導体の端部がキ
ャリアテープに支持されているので、線状導体の平滑
性、ピッチ等の位置精度が保持され、バンプ接続に有利
であるほか、線状導体とICチップの電極との接続部を
封止する際に、従来のデバイスホールの様にキャリアテ
ープの開口部が大きくないので、ICチップの封止高が
抑制されてパッケージの小型化に有利である上、封止樹
脂の染みだしも抑さえられるといった優れた効果を得る
ことができる。また、線状導体の先端がキャリアテープ
に支持されているので、線状導体に鍍金処理を施す際に
線状導体の先端の電流密度の集中を防止して鍍金層の異
常析出が抑さえられるので、線状導体の先端形状のばら
つきが少なく線状導体とICチップの電極とのバンプ接
続に有利であるとともに、各線状導体のICチップの電
極への押圧力の強度のばらつきも少なくなり、バンプ接
続部分信頼性が向上する。
As described above, according to the tape carrier package of the first aspect, since the ends of the linear conductors are supported by the carrier tape, the smoothness of the linear conductors, the position of pitch, etc. The accuracy is maintained, it is advantageous for bump connection, and when sealing the connection between the linear conductor and the electrode of the IC chip, the opening of the carrier tape is not large like the conventional device hole, so the IC It is possible to obtain an excellent effect that the sealing height of the chip is suppressed, which is advantageous for downsizing of the package, and the leakage of the sealing resin is suppressed. Further, since the tip of the linear conductor is supported by the carrier tape, the concentration of the current density at the tip of the linear conductor is prevented when the linear conductor is plated, and abnormal deposition of the plated layer is suppressed. Therefore, there is little variation in the tip shape of the linear conductor, which is advantageous for bump connection between the linear conductor and the electrode of the IC chip, and variation in the strength of the pressing force of each linear conductor to the electrode of the IC chip is reduced. Bump connection area reliability is improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のテープキャリアパッケージの一実施例
を示す平面図である。
FIG. 1 is a plan view showing an embodiment of a tape carrier package of the present invention.

【図2】前記テープキャリアパッケージを示す側断面図
である。
FIG. 2 is a side sectional view showing the tape carrier package.

【図3】前記テープキャリアパッケージにベタパターン
を設けた実施例を示す底面図である。
FIG. 3 is a bottom view showing an embodiment in which a solid pattern is provided on the tape carrier package.

【図4】前記テープキャリアパッケージにベタパターン
を設けた実施例を示す側断面図である。
FIG. 4 is a side sectional view showing an embodiment in which a solid pattern is provided on the tape carrier package.

【図5】従来のテープキャリアパッケージを示す平面図
である。
FIG. 5 is a plan view showing a conventional tape carrier package.

【図6】従来のテープキャリアパッケージを示す側断面
図である。
FIG. 6 is a side sectional view showing a conventional tape carrier package.

【符号の説明】[Explanation of symbols]

10 キャリアテープ 11 長孔(孔) 13 ビームリード(線状導体) 14 ベアチップIC(ICチップ) 15 バンプ 16 レジストインク(絶縁層) 17 封止樹脂 19 ビームリード(線状導体) 10 Carrier Tape 11 Long Hole (Hole) 13 Beam Lead (Linear Conductor) 14 Bare Chip IC (IC Chip) 15 Bump 16 Resist Ink (Insulating Layer) 17 Sealing Resin 19 Beam Lead (Linear Conductor)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 キャリアテープ上に複数の線状導体が並
列に配置・固定され、該複数の線状導体の端部にICチ
ップの電極がバンプを介して接続され、前記複数の線状
導体に絶縁層が被覆され、前記ICチップと前記キャリ
アテープとの間に前記電極と線状導体との接続部を覆っ
て樹脂が固着されたテープキャリアパッケージにおい
て、前記キャリアテープに前記複数の線状導体の端部を
横切る方向に孔が形成され、該複数の線状導体の端部が
該孔を通って先端が該キャリアテープに支持される架橋
状態に配置・固定されていることを特徴とするテープキ
ャリアパッケージ。
1. A plurality of linear conductors are arranged and fixed in parallel on a carrier tape, and electrodes of an IC chip are connected to end portions of the plurality of linear conductors via bumps. A tape carrier package in which an insulating layer is covered with a resin, and a resin is fixed between the IC chip and the carrier tape so as to cover a connecting portion between the electrodes and the linear conductors. A hole is formed in a direction crossing the end of the conductor, and the ends of the plurality of linear conductors are arranged and fixed in a bridged state in which the ends pass through the holes and the tips are supported by the carrier tape. Tape carrier package.
JP5337601A 1993-12-28 1993-12-28 Tape carrier package Pending JPH07201911A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5337601A JPH07201911A (en) 1993-12-28 1993-12-28 Tape carrier package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5337601A JPH07201911A (en) 1993-12-28 1993-12-28 Tape carrier package

Publications (1)

Publication Number Publication Date
JPH07201911A true JPH07201911A (en) 1995-08-04

Family

ID=18310186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5337601A Pending JPH07201911A (en) 1993-12-28 1993-12-28 Tape carrier package

Country Status (1)

Country Link
JP (1) JPH07201911A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6744122B1 (en) 1999-10-04 2004-06-01 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6744122B1 (en) 1999-10-04 2004-06-01 Seiko Epson Corporation Semiconductor device, method of manufacture thereof, circuit board, and electronic device

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