JPH07200539A - Two-dimensional dct arithmetic unit - Google Patents

Abstract

PURPOSE:To calculate the two-dimensional DCT/IDCT in a circuit constitution of a smaller scale than the conventional one. CONSTITUTION:This arithmetic unit consists of a one-dimensional DCT unit of the first stage, an intermediate buffer and a one-dimensional DCT unit of the second stage which operate via a pipeline. An (8X8)-pixel block matrix is externally read in order of O-th, 7th, 1st, 6th, 2nd, 5th, 3rd and 4th rows and in order of O-th, 7th, 1st, 6th, 2nd, 5th, 5rd and 4th columns respectively. These orders are changed by the simple address conversion when a DCT coefficient is written. The one-dimensional DCT unit applying conventionally a distribution arithmetic method consists of a constant multiplier and a totalizer. In such a constitution, the intermediate buffer can be reduced down to a quarter and the constitution of a computing element is simplified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a two-dimensional discrete cosine transform (DCT) in a signal processing device.
Abbreviated) and inverse discrete cosine transform (IDCT (Inverse Discrete Co
sine Transform) and either).

[0002]

2. Description of the Related Art High-speed DCT calculation is required in many signal processing fields such as compression / expansion of images and sounds. DCT
Requires a large circuit scale in order to process this in real time because the amount of processing calculation is enormous. Conventional two-dimensional DC
The T arithmetic unit is, for example, Japanese Patent Publication No. Hei 5-26229, US Pat. No. 4,791,598 (December 13, 1988) and MT Sun, L. Wu, a
nd ML Liou, "A Concurrent Architecture for VLSI I
mplementation of Discrete Cosine Transform, "IEEET
rans.on Circuits and Systems, Vol. CAS-34, No.8, pp.
992-994, Aug. 1987, and MT Sun, TC Chen, A. Gottl
ieb, L. Wu, and ML Liou, "A 16x16 Discrete Cosine T
ransform Chip, "Visual Commun. and Image Process.
II, SPIE, Vol.845, pp.13-18, Oct.1987, and MT Su
n, TC Chen, and AM Gottlieb, "VLSI Implementatio
n of a 16 × 16 Discrete Cosine Transform, "IEEE Tra
ns. Circuits and Systems, Vol. CAS-36, pp. 610-617, A
pr.1989, and TC Chen, MT Sun, and AM Gottlie
b, "VLSI Implementation of a 16x16 DCT," ICASSP 88,
Intl. Conf. Acoust., Speech, and Signal Process., P
p. 1973-1976, Apr. 1988.

(FIG. 10), (FIG. 11) and (FIG. 12) are block diagrams of a conventional example. The conventional example describes an N × N two-dimensional DCT, but here, for simplicity, it is limited to the case of 8 × 8. In addition, the pixel data, internal numerical representation, and DCT coefficient are 1
It is assumed that it is a fixed point number of 6 to 8 bits.
In FIG. 10, 203 is the first column N × 1 DCT processor. 205 is an N × N conversion memory. 207 is a second row N × 1 DCT processor. 209 is a timing and control signal generator. 211 and 212 are timing and control signals. Reference numeral 216 is a read / write address and control circuit. Reference numeral 214 is a read / write address and control signal. In FIG. 11, 3
Reference numeral 13 is an input register. Reference numeral 315 is a holding register. Reference numerals 381 and 383 denote N / 2 serial adders and serial subtractors, respectively. 317 is RAC (ROM and accu
mulator). Reference numeral 319 is an output register. 38
5,387 are N / 2 bit buses. 445, 447 is 1
It is a 6-word ROM. Reference numeral 449 is an adder. Reference numeral 451 is an adder / subtractor. Reference numeral 453 is a shift register.

In the conventional example, 4 bits of 8 × 8 DCT are used.
Although RAC is used, in order to process 16-bit pixel data, serial adder 381, serial subtractor 383, RA
The C317 and the like must operate at double the frequency of other parts such as the shift register (details are given in the above paper). If the same frequency is supplied to all, 8-bit RAC shown in (FIG. 12) is required.

[0005]

However, the above-mentioned two-dimensional DCT arithmetic unit of the prior art requires two one-dimensional DCT arithmetic units and a conversion memory for row-column transposition of N × N words. There was a problem that the number of elements consumed by the wear, the circuit area, and the power consumption were large. In addition, the above-mentioned conventional two-dimensional DCT computing device is
There is a problem that a large number of internal buffers and shift registers are required to perform DCT operation in serial bit using the ributed arithmetic method.

In view of the above problems, it is an object of the present invention to provide a novel two-dimensional DCT arithmetic device which has performance equivalent to that of a conventional two-dimensional DCT arithmetic device and which is configured with less hardware. .

[0007]

In order to solve the above-mentioned problems, a two-dimensional DCT operation device of the present invention is provided with a two-stage one-dimensional DCT operation means for a data matrix having N × N elements. A two-dimensional DCT arithmetic device that calculates a two-dimensional discrete cosine transform and writes each component of the matrix of the conversion result to an external memory,
For the data matrix to be subjected to the two-dimensional DCT, the first stage for the reading means for reading out the components corresponding to the reading number order shown in (Equation 1) one by one and the two components read by the reading means The first one-dimensional DCT calculation means for performing one-dimensional DCT and generating the conversion result for each column, and the two-column components generated by the first one-dimensional DCT calculation means are two components in row order. A second read-out means for reading out one by one, and a second one-dimensional DCT operation for performing a second-stage one-dimensional DCT on the two components read out by the second read-out means to generate a matrix of the conversion result. Means and
And a writing unit that writes the matrix of the conversion result generated by the second one-dimensional DCT calculation unit to the external memory one by one.

Further, the first one-dimensional DCT means has a first addition / subtraction means, a first constant multiplication means, and a first accumulation means, and the first addition / subtraction means is a reading means. Performs addition and subtraction of the two components read by, the first constant multiplication means, in the product sum calculation of one row × one column in the one-dimensional DCT of the first stage, the addition result by the first addition and subtraction means All partial products with the subtraction result as a multiplier are obtained, and the first accumulating means obtains the accumulated value of the partial products of the first constant multiplying means for one column of the addition / subtraction result, and the obtained accumulated value is the second value. Output to the reading means, the second one-dimensional DCT means has a second addition and subtraction means, a second constant multiplication means, and a second accumulation means, the second addition and subtraction means, Addition and subtraction of the two components read by the second reading means are performed, and second constant multiplication means , In the one-row × one-column product-sum calculation in the second-stage one-dimensional DCT, all the partial products using the addition result and the subtraction result by the second addition and subtraction means as multipliers are obtained, and the second accumulation means performs addition and subtraction. As a result, the accumulated value of the partial products of the first constant multiplication means for one row may be obtained, and the obtained accumulated value may be output to the writing means.

The first addition / subtraction means has a two-stage shift register, a first input buffer, a second input buffer, and a first adder / subtractor, and the two-stage shift register is , The two components of the input signal sequence read by the reading means are held by shifting by one component, and the first input buffer holds one component held by the preceding stage every time the two-stage shift register shifts twice. The second input buffer receives a component held in the second stage each time the two-stage shift register shifts twice, and the first adder / subtractor operates in the first input buffer and the second input buffer. The two constant components are alternately added and subtracted, and the first constant multiplication means has N / 2 first constant multipliers connected to the first adder-subtractor, Is a constant multiplier in the first-stage one-dimensional DCT. In the product-sum calculation of one row ×,
The addition result and the subtraction result by the first adder-subtractor is a multiplier, and a partial product in which one component of a predetermined matrix is a multiplicand is obtained, and the first accumulating unit is the N / 2 constant multiplier. N / 2 first adders connected corresponding to each, and N / 2 two-stage shift registers connected corresponding to each of the N / 2 first adders And each first adder has a product output by the first constant multiplier,
The components output from the subsequent stages of the two-stage shift register are added, and each of the two-stage shift registers holds the two components while shifting the components output by the first adder, and stores the two retained components into one. The output of the latter stage may be fed back to the first adder by shifting the components one by one, and after shifting N × 2 times, the two components in the one column may be output to the second reading means at once.

Further, the second reading means has a one-column buffer, a first N-stage parallel / serial conversion shift register, and a second N-stage parallel / serial conversion shift register. The one-column buffer receives the components of one column sequentially generated by the first one-dimensional DCT calculation means and holds them every other column, and the component of the column next to the held component is the first one-dimensional buffer. When output from the DCT calculation means, the one-column component held until then is output to the first N-stage parallel / serial conversion shift register at once, and the first N-stage parallel / serial conversion is performed. The shift register for use holds one-column components output from the one-column buffer, shifts the held one-column components one component at a time, and performs one-column components one component at a time on the second one-dimensional DCT operation. Output to a means for parallel / serial conversion of the second N stages. The register registers the one-column components output by the first one-dimensional DCT calculation means, which are not received by the one-column buffer, shift the held one-column components one by one, and May be output to the second one-dimensional DCT calculation means one by one.

The second addition / subtraction means alternately performs addition and subtraction of the two components output by the second reading means, and the second constant multiplication means is connected to the second addition / subtraction means. N / 2 number of second constant multipliers, each second constant multiplier is a second addition / subtraction means in the one-row × one-column product-sum calculation in the second-stage one-dimensional DCT. The addition result and the subtraction result by the as a multiplier, the partial product in which one component in one row of a predetermined matrix is the multiplicand, the second accumulation means, the N / 2 second constant multiplier N / 2 second adders connected to each of the N
/ N / 2 N × 2 connected corresponding to 2 second adders
And a second stage adder, each second adder having
The product output from the second constant multiplier and the component output from the final stage of the N × 2 stage shift register are added, and each N
The × 2 stage shift register holds the components output by the second adder for two columns while shifting them, and shifts the retained components one component at a time to feed back the output of the final stage to the second adder. Then, after shifting N × N times, the components for the two columns may be output to the writing unit one by one.

Further, the accumulating means further comprises N / 2 N × 2
Of the shift registers of the stages, N / 2-1 output buffers connected to the final stage of N / 2-1 excluding a predetermined one, and an output selector, N / 2-1 The output buffer of is composed of N × 2 stages of shift registers, holds the components for two columns output from the connected shift register one component at a time while shifting, and sequentially holds the held components one component at a time. The output may be output to the output selector, and the output selector may select and output the output of each N × 2 stage shift register and N / 2-1 output buffers.

Further, the constant multiplier may have a ROM in which a multiple of a component of a predetermined matrix is stored in advance.
In addition, the constant multiplier converts the components of the constant matrix used for the one-dimensional DCT of the first and second stages and / or the inverse discrete cosine transform of the first and second stages as a predetermined matrix. The components of the constant matrix used may be stored in advance.

The read means comprises a read column generation means, a read row generation means, and a read address generation means, and the read column generation means is a column in the data matrix having N × N components of the component to be read. The read row generation means specifies the row number of the component to be read in the column specified by the read column generation means,
The read address generation means may generate an address in the external memory of the component to be read, from the column number generated by the read column generation means and the row number generated by the read row generation means.

The writing means has a write column generating means, a write row generating means, and a write address generating means, and the write column generating means is the column number of the element of the matrix of the operation result to be written. And the writing row generating means generates the row number of the component to be written in the column of the column number generated by the writing column generating means,
The write address generation means may generate an address in the external memory for writing each component of the operation matrix from the row number generated by the write row generation means and the column number generated by the write column generation means.

[0016]

With the above-described means, in the two-dimensional DCT arithmetic device of the present invention, the data matrix to be subjected to the two-dimensional DCT is read by the reading means one by one in the order of the read numbers shown in (Equation 1). The first one-dimensional DCT calculation means is operated for each two components read by the reading means, the first-stage one-dimensional DCT is performed, and the conversion result is generated for each column. Each of the two columns of components generated by the first one-dimensional DCT calculation means is read by the second reading means, two components in row order. The two components read by the second reading means, second one-dimensional DCT is performed by the second one-dimensional DCT operation means,
A matrix of conversion results is generated. The matrix of the conversion result generated by the second one-dimensional DCT calculation means is written into the external memory by the writing means one component at a time.

According to the above-mentioned means, the first one-dimensional DCT means of the present invention has the first adding / subtracting means, the first constant multiplying means, and the first accumulating means, and is read by the reading means. The addition and subtraction of the output two components are performed by the first addition / subtraction means, and the addition result and the subtraction result by the first addition / subtraction means in the product sum calculation of one row × one column in the first-stage one-dimensional DCT are calculated. The partial products that are multipliers are all obtained by the first constant multiplication means. The cumulative value of the partial product of the first constant multiplying means for one column of the addition / subtraction result is obtained by the first accumulating means, and the obtained accumulated value is output to the second reading means.

According to the above means, the second one-dimensional DCT means of the present invention has the second adding / subtracting means, the second constant multiplying means, and the second accumulating means. Addition and subtraction of the two components read by the means is performed by the second addition and subtraction means, the addition result by the second addition and subtraction means in the product sum calculation of one row × one column in the one-dimensional DCT of the second stage and The partial product with the subtraction result as a multiplier is all obtained by the second constant multiplying means, and the cumulative value of the partial product of the first constant multiplying means for one line of the addition / subtraction result is obtained by the second accumulating means. The accumulated value thus obtained is output to the writing means.

The first addition / subtraction means has a two-stage shift register, a first input buffer, a second input buffer, and a first adder / subtractor. By shifting one component at a time, the two components of the input signal sequence read by the reading means are held. Each time the two-stage shift register shifts twice, one component held by the previous stage is received by the first input buffer. Each time the two-stage shift register shifts twice, one component held in the latter stage is received by the second input buffer, and addition and subtraction of the two components in the first input buffer and the second input buffer are performed. , The first adder / subtractor alternates.

According to the above means, the first constant multiplication means of the present invention has N / 2 first constant multipliers connected to the first adder / subtractor, and The partial product in the one-row × one-column product-sum calculation in the first-stage one-dimensional DCT whose addition result and subtraction result are multipliers and one component of a predetermined matrix is the multiplicand is obtained by each first constant multiplier .

According to the above means, the first accumulating means of the present invention comprises N / 2 first adders connected corresponding to the N / 2 constant multipliers, respectively. And N / 2 two-stage shift registers connected corresponding to each of the N / 2 first adders, and the product output from the first constant multiplier and the two-stage shift Addition with the component output from the latter stage of the register is performed by each first adder. The components output from the first adder are held in two components while being shifted by each two-stage shift register, and the held two components are shifted by one component, so that the output of the subsequent stage is transferred to the first adder. After being fed back and shifted by N × 2 times, the two components in the one row are output to the second reading means at once.

According to the above-mentioned means, the second reading means of the present invention comprises a one-column buffer, a first N-stage parallel / serial conversion shift register, and a second N-stage parallel / serial conversion. And a shift register, and the one-column buffer receives and holds the components of one column sequentially generated by the first one-dimensional DCT operation means, every other column, and stores the components of the column next to the held component. When it is output from the first one-dimensional DCT calculation means, the one-column component held until then is
It is output to the N-stage parallel / serial conversion shift register at once, and the first N-stage parallel / serial conversion shift register holds the one-column component output from the one-column buffer, and the one-column stored Shift the minute component one by one,
The components for one column are output one by one to the second one-dimensional DCT operation means, and the second N-stage shift register for parallel / serial conversion is output by the first one-dimensional DCT operation means. The one-column component that is not received by the one-column buffer is held, the held one-column component is shifted one component at a time, and the one-column component is one component by the second one-dimensional DCT.
Is output to the calculation means, and by the second addition and subtraction means,
The addition and subtraction of the two components output by the second reading unit are alternately performed.

According to the above means, the second constant multiplication means of the present invention has N / 2 second constant multipliers connected to the second addition / subtraction means, and each second constant The partial product in the one-row × one-column product sum calculation in the second-stage one-dimensional DCT in which the addition result and the subtraction result by the second addition and subtraction means are set as multipliers by the multiplier, and one component in one row of a predetermined matrix is set as the multiplicand Is required.

Further, the second accumulating means of the present invention by the above means is the N / 2 second adders connected corresponding to each of the N / 2 second constant multipliers. And N / 2 N × 2 stages of shift registers connected corresponding to the N / 2 second adders, and the product output from the second constant multiplier, N The component output from the final stage of the × 2 stage shift register is added by each second adder, and the component output by the second adder is divided into two columns by each N × 2 stage shift register. The held component is shifted by one component and the output of the final stage is fed back to the second adder. After shifting N × N times, the components of the two columns are output to the writing unit one by one.

Further, by the above means, the accumulating means of the present invention is further connected to N / 2-1 final stages except a predetermined one of N / 2 N × 2 stages of shift registers. It has N / 2-1 output buffers and an output selector, and the components for two columns output from the connected shift register one component at a time are N / 2-1.
It is held while shifting by 2-1 output buffers, and the held components are sequentially output to the output selector one by one.

[0026]

EXAMPLE A detailed description of DCT will be given below. IDC
The processing for T can be performed in the same manner and can be calculated by an equivalent arithmetic unit, so the description of IDCT is omitted. In the following explanation, the input signal sequence is f _ij or f (i, j)
And the one-dimensional DCT of f _{ij is} the two-dimensional DCT of h _ij in h _mn or h (m, n)
DCT is represented by g _uv or g (u, v). The present invention is an N × N two-dimensional DC
Regarding T, the case of 8 × 8 will be described below.
In addition, pixel data, internal numerical expressions, and DCT coefficients are fixed-point numbers of 16 bits or less.

Although some definition formulas are given to the DCT, here, reference is made to the definition formulas typically stipulated in the image coding international standard such as MPEG and JPEG. That is, the 8 × 8 two-dimensional DCT is defined by the following equation.

[0028]

[Equation 2]

[0029]

[Equation 3]

[0030]

[Equation 4]

[0031]

[Equation 5]

[0032]

[Equation 6]

[0033]

[Equation 7]

[0034]

[Equation 8]

[0035]

[Equation 9]

[0036]

[Equation 10]

[0037]

[Equation 11]

[0038]

[Equation 12]

[0039]

[Equation 13] (FIG. 1) is a diagram showing a configuration of a two-dimensional DCT computation device in an embodiment of the present invention configured to perform the above computation. The two-dimensional DCT calculation device is the first DCT calculation unit 100.
, Intermediate buffer 110, and second DCT operation unit 120
And an address generator 130.

The address generator 130 includes a linear read address generator 131 and a linear write address generator 1.
And 35. Linear read address generation unit 13
1 is for calculating the linear address of the N × N matrix component data (N = 8 in this embodiment) in the external linear memory based on the column read address and the row read address, and calculating the linear address component Each component is read out to the first DCT calculation unit 100.

FIG. 2 is a diagram showing the configuration of the linear read address generator 131. The linear read address generation unit 131 includes a log ₂ N × 2 bit counter 132, a row read address generation unit 133, and a column read address generation unit 134. log ₂ N × 2 bit counter 1
32 is an input terminal for inputting a clock pulse and log ₂ N
× 2 output terminals are provided, and counts N × N times each time a clock pulse is input. In this embodiment, N =
Therefore, the log ₂ N × 2 bit counter 132 has r0 to r
It is equipped with 5 output terminals, and the numbers 0 to 63 are generated at the output terminals r0 to r5.

The row read address generation unit 133 uses log ₂
The lower 3 bits of the numerical value generated by the N × 2 bit counter 132 are input, and a row read address is generated each time a clock pulse is input to the log ₂ N × 2 bit counter 132. When the lower 3 bits of the numerical value generated by the log ₂ N × 2 bit counter 132 increase in the order of 0, 1, 2, 3, 4, 5, 6, 7, the row read address generation unit 133 determines that 0,7,1,6,
Generates read addresses for reading 2,5,3,4 rows.

The column read address generator 134 uses log ₂
The upper 3 bits of the numerical value generated by the N × 2 bit counter 132 are input, and a column read address is generated each time the upper 3 bits are counted up. The upper 3 bits of the output terminal of the log ₂ N × 2 bit counter 132 are 0,1,2,3,4,5,6,7.
Is counted, the column read address generation unit 134
Generates a read address for reading columns 0,7,1,6,2,5,3,4.

When the row read address generation unit 133 and the column read address generation unit 134 generate read addresses in this way, the reading order is 0, 7, 1, 1 in column units.
The order is 6,2,5,3,4 columns, and the order is the 0,7,1,6,2,5,3,4 rows in the columns, that is, as shown in the table below. 1 17 33 49 57 41 25 9 3 19 35 51 59 43 27 11 5 21 37 53 61 45 29 13 7 23 39 55 63 47 31 15 8 24 40 56 64 48 32 16 6 22 38 54 62 46 30 14 4 20 36 52 60 44 28 12 2 18 34 50 58 42 26 10 The first DCT operation unit 100 performs the first stage one-dimensional DCT operation shown in (Equation 12) in 64 cycles. The order in which the first DCT calculation unit 100 calculates each component of the matrix H is shown in FIG. "1 + 3 + 5 + 7" written under h _{00 in} the figure means h
₀₀ means that the multiplication is performed in the first cycle, and the multiplication and accumulation are performed in the third, fifth, and seventh cycles. h
"57 + 59 + 61 + 63" written under ₆₇ means that h ₆₇ is calculated by multiplying at the 57th cycle, and multiplying and accumulating at the 59,61,63th cycle. Means that. The first DCT calculation unit 100 is configured so that calculations can be performed in this order.

The first DCT calculator 100 includes an input shift register 101, an input buffer 102, a first adder / subtractor 1
03, the first constant multiplier 104, the first accumulator 105,
And a cumulative shift register 106. The input shift register 101 is composed of a two-stage shift register that stores two-component data while shifting it. Specifically, the input shift register 101 causes the first-stage register to hold the one-component data read from the external linear memory by the linear read address generation unit 131.
When the next component is read by the linear read address generation unit 131, the contents held until then are shifted to the register of the next stage. As a result, the input shift register 1
01 is filled with two components in two cycles. At the same time as the filling, the input shift register 101 stores the data of the two components held until then in the input buffer 102 at once.
Transfer to.

The input buffer 102 holds the two-component data transferred by the input shift register 101 until the next two-component data is read to the input shift register 101 (this holding is performed for two cycles. ). When the next two-component data is read to the input shift register 101, the input buffer 102 transfers the two-component data held up to that point to the first adder / subtractor 103.

The first adder / subtractor 103 calculates each component (f _0j + f _{7 j} , f _0j −f _7j , f _1j + f) of the matrix of the first term on the right side of ( _Equation 12).
_6j , _{f1j- f6j} , _f2j + _f5j , _{f2j- f5j} , _f3j + _f4j , _f3j- f
_4j j = 0, ..., 7) is calculated. Specifically, the first adder / subtractor 103 receives the data of the two components transferred by the input buffer 102, adds the data of these two components in one cycle at the time of reception, and outputs the addition result as the first It outputs to the constant multiplier of each stage of the constant multiplier 104. After the output, the first adder / subtractor 103 subtracts the data of two components in one cycle, and outputs the subtraction result to each constant multiplier of the first constant multiplier 104. In this way, the first adder / subtractor 103 alternately repeats addition and subtraction for each two-component data. Operations on the j-column data are f _0j + f _7j , f _0j –f _7j , f _{1j in} cycle order.
+ _F6j , _{f1j- f6j} , _f2j + _f5j , _{f2j- f5j} , _f3j + _f4j , _f3j
−f _4j and this is repeated for the 0th, 7th, 1st, 6th, 2nd, 5th, 3rd, and 4th columns in order.

The first constant multiplier 104 is composed of N / 2 (four) ROMs. These ROMs contain (Equation 1
The multiplication value of the matrix component of the second term on the right side of 2) and the matrix component of the first term on the right side of (Equation 12) is stored in advance. The N / 2 ROMs forming the constant multiplier 104 are the first adder / subtractor 1
The result of addition and subtraction output from 03 is received, and the stored multiplication value that has the matrix component of the second term on the right side of (Equation 12) output from the first adder-subtractor 103 as the multiplicand is extracted. And outputs it to each of the N / 2 adders of the first accumulator 105.

The first accumulator 105 is composed of N / 2 adders. The first accumulator 105 calculates the product of N / 2 output from the first constant multiplier 104 and the accumulation shift register 1
And the intermediate value during accumulation of N / 2 that is fed back via 06 is added. The cumulative shift register 106 is composed of N / 2 two-stage shift registers.

The cumulative shift register 106 holds the intermediate values of the components of the matrix H and corresponds to the odd and even rows in one column.
The shift operation is performed so that N / 2 accumulations are alternately performed every cycle, and the intermediate value in the middle of accumulation is calculated by the first accumulator 10
Give feedback to 5. By repeating this shift operation for N cycles, the cumulative shift register 106 is filled with the components for one column of the matrix H, and at the time of filling, the cumulative shift register 106 stores all the components for one column in the intermediate buffer 110. Transfer sequentially. The numbers written in the cells in the figure indicate which row in one column the component filled in each register is.

The intermediate buffer 110 is the single column buffer 11
1 and a two-row shift register 112. The one-column buffer 111 receives N components for one column, which are sequentially transferred by the cumulative shift register 106, every other column, until one component for the next column of the matrix H is calculated in the cumulative shift register 106. The buffer 111 holds the received component for one column. When the component for the next one column for the held one column is calculated in the cumulative shift register 106, the one-column buffer 111 transfers the held component for one column to the two-column shift register 112 at once.

The two-row shift register 112 is constructed by arranging two stages of N-stage shift registers for parallel / serial conversion. The two-column shift registers forming the two-column shift register 112 receive the two-column values transferred from the accumulation shift register 106 and the one-column buffer 111.
Next, the shift register for the above two columns shifts every cycle, and transfers these two components to the second DCT operation unit 120 two by two. When all the components for two columns have been transferred to the second DCT operation unit 120 in eight cycles, the two-column shift register 112 receives the components for the next two columns from the accumulation shift register 106 and the one-column buffer 111. .

The second DCT calculation section 120 performs the second stage one-dimensional DCT calculation shown in (Equation 13) in 64 cycles. The order in which the second DCT calculation unit 100 calculates each component of the matrix G is shown in FIG. "1+" written under g _{00 in} the figure
17 + 33 + 49 "means g ₀₀ multiplies in the first cycle,
It means that it is calculated by performing multiplication and accumulation at the 33rd and 49th cycles. written under g ₆₇ "14 + 30 + 46 + 6
2 "means that g ₆₇ multiplies in the 14th cycle to get 30,46,62
It means that it is calculated by performing multiplication and accumulation at the cycle. The second DCT calculator 120 is configured so that the calculation can be performed in this order.

The second DCT calculator 120 includes a second adder / subtractor 121, a second constant multiplier 122, and a second accumulator 12.
3, two-row shift registers 124a, 124b, 124
c, 124d, two-column output buffers 125b, 125c,
It is composed of 125d. The second adder / subtractor 121 calculates each component h _{m, 0} + h _{m, 7} , h _{m, 0} − of the matrix of the first term on the right side of (Equation 13).
h _{m, 7} , h _{m, 1} + h _{m, 6} , h _{m, 1} −h _{m, 6} , h _{m, 2} + h _{m, 5} , h _{m, 2} −h
Calculate _{m, 5} , h _{m, 3} + h _{m, 4} , h _{m, 3} −h _{m, 4} (m = 0, ..., 7). Specifically, the second adder / subtractor 121 receives the two components transferred by the two-column shift register 112, adds these two components in one cycle at the time of reception, and outputs the addition result to the first second Output to the constant multiplier 122. After the output, the second adder / subtractor 121 performs the subtraction of the two components in one cycle, and outputs the subtraction result to each constant multiplier of the second constant multiplier 122.

The second constant multiplier 122 is composed of N / 2 (four) ROMs. These ROMs are (Equation 13)
The multiplication value of the matrix component of the second term on the right side of the above and the matrix component of the first term on the right side of (Equation 13) is stored in advance. The N / 2 ROMs constituting the second constant multiplier 122 are the second adder / subtractor 12
Among the stored multiplication values that receive the addition and subtraction results output from 1 and all of which have the matrix component of the second term on the right side of (Equation 13) output from the second adder / subtractor 121 as the multiplicand, It is taken out and output to each of the N / 2 adders of the second accumulator 123.

The second accumulator 123 is composed of N / 2 adders. The second accumulator 123 has a product of N / 2 output from the second constant multiplier 122 and the two-column shift register 1
24a, 124b, 124c, and 124d are fed back, and the intermediate value of N / 2 being accumulated is added. The two-row shift register 124a is composed of N × 2 stages of shift registers. The two-column shift register 124a holds the intermediate values of the components of the matrix G, and the accumulation for obtaining the components of two columns is g _0v , g _{0, v + 1} , g _1v , g _{1, v + 1.} , G _2v , g _{2, v + 1} , g _3v ,
g _{3, v + 1} , g _4v , g _{4, v + 1} , g _5v , g _{5, v + 1} , g _6v , g _{6, v + 1} ,
The shift operation is performed so that g _7v , g _{7, v + 1} (v = 0,2,4,6) are alternately performed in order, and the intermediate value in the middle of accumulation is set to the second accumulator 1
Give feedback to 23. By repeating this shift operation for 64 cycles, the two-column shift register 124a is filled with components for two columns of the matrix G. The two-row shift register 124a performs a shift operation at the time of filling, and outputs the two-row components one by one in each cycle of the output selector 126.
And outputs all the components for two columns to the output selector 126 in N × 2 cycles. It should be noted that the numbers written in the cells in the figure indicate which components in one column the components filled in each register are. The two-row shift register 124b, 124c, 124d performs the same operation as the two-row shift register 124a. The difference is that the two-row shift registers 124b, 124c, and 124d output to the two-row output buffers 125b, 125c, and 125d. It should be noted that the numbers written in the cells in the figure indicate which components in one column the components filled in each register are.

Two-column output buffers 125b, 125c, 1
25d is a two-row shift register 124b, 124c, 1
The components for two columns output from 24d are received one by one, and while shifting, all these components are stored in N × 2 cycles. After the two-row shift register 124a outputs all the components for two rows to the output selector 126 by taking N × 2 cycles, the two-row output buffers 125b, 125c,
The 125d takes N × 2 cycles and sequentially outputs the components of two columns to the output selector 126. It should be noted that the numbers written in the cells in the figure indicate which components in one column the components filled in each register are.

The output selector 126 includes a two-column shift register 124a, two-column output buffers 125b, 125c, 12
Each element of the matrix G output from 5d is selectively output to the external linear memory. Linear write address generator 135
Generates a row write address and a column write address for writing each element of the matrix G output from the output selector 126 into the external linear memory. FIG. 5 shows the configuration of the linear write address generation unit 135. The linear write address generation unit 135 includes a log ₂ N × 2 bit counter 136, and the log ₂ N × 2 bit counter 13
The order of the output terminals of No. 6 is exchanged and output to the outside.

The log ₂ N × 2 bit counter 136 has a log ₂ N
It is provided with × 2 output terminals and counts N × N times each time each element of the matrix G is received from the output selector 126. Since N = 8 in this embodiment, the log ₂ N × 2 bit counter 136 generates the numerical values of 0 to 63 at the output terminals u0 to u5. Each time the log ₂ N × 2 bit counter 136 counts an even value, the row write address is incremented and lo
The column write address is incremented each time the g ₂ N × 2 bit counter 136 counts an odd value. By generating the address as the row write address and the column write address, the components of the matrix G are written in the external linear memory in the following order. 1 2 17 18 33 34 49 50 3 4 19 20 35 36 51 52 5 6 21 22 37 38 53 54 7 8 23 24 39 40 55 56 9 10 25 26 41 42 57 58 11 12 27 28 43 44 59 60 13 14 29 30 45 46 61 62 15 16 31 32 47 48 63 64 (FIG. 6) is the first constant multiplier 104, the second constant multiplier 122, the first accumulator 105, and the first accumulator 105 (FIG. 1). FIG. 3 is a detailed diagram of each constant multiplier and adder that form the second accumulator 123. Below, the constant multiplier 104 and the first constant accumulator 1
Details of the configuration of 05 will be described.

In the figure, the ROM 501 is composed of four 8 × 16 word constant ROMs, and the constant multipliers 104, 1 of FIG. 1 are used.
Equivalent to 22. The value of the product of the multiplicand bi and the constant is precalculated and stored in the ROM 501. More specifically, the 16-bit multiplicand is divided into four every four bits, and the product of these four bits and a constant, that is, the constant 0 to 15
Is stored in the constant ROM (the capacity of the ROM 501 becomes smaller by storing in this way). Also, as can be seen from (Equation 12), half the components of the constant matrix are 0 (zero), and the multiplicand bi is multiplied by four constants in one multiplication, so these four constants are common. These four constants are retrieved when stored in the address and the multiplicand bi is input. The product of 4 bits for each division and 16 bits of constant is 20 bits long, and since the above 4 constants are stored in the same address, 20 × 4 = 8
The 0 bit length is the bit length of one word. Further, since half of the components of the constant matrix stored in the ROM are 0, the ROM 501 stores 8 × 2 ⁴ = 128 words. First adder / subtractor 103
By using each element of the matrix of the first term on the right-hand side of (Equation 12) output from
Six 20-bit long partial products are retrieved simultaneously.

The first accumulator 105 includes N / 2 carry save adders (hereinafter abbreviated as CSA (carry save adder)) for adding five inputs to two partial sums without carry propagation, and N. / 2
Carry carry adders (hereinafter CPA (carry propagate adde
abbreviated as r)). CSA502 in the figure is a carry save adder that adds five inputs to two partial sums without carry propagation. As shown in FIG. 7, the CSA 502 is composed of three stages of CSA. 20 × output from ROM 501
Assuming that 20 bits of each of the products of 4 bits are m0, m1, m2, and m3 in order from the lower one, CSA in the first stage adds m0 and the accumulated value. The CSA in the second stage adds the addition result of the CSA in the first stage and m1 shifted up by 4 bits. The third and fourth stage CSAs add the addition results of the second and third stage CSAs, with m2 and m3 shifted by 8 bits and 12 bits higher. It should be noted that the additions performed by the CSA 502 are performed with the carry retained.

The CPA 503 in the figure adds the addition output (S) output from the CSA 502 and the carry output (C).
The addition result is rounded to an appropriate bit width and output to the accumulation shift register 106. (FIG. 8) is a two-row shift register 124a and a two-row output buffer 125 (of FIG. 1).
It is a figure showing the timing of the shift control signal of b, 125c, 125d. In the figure, the number of execution cycles, that is, time is shown in the right direction. The vertical axis represents the logical value of the shift control signal of 0 or 1. The two-column output buffers 125b, 125c, and 125d hold components while the shift control signal is 0, and the two-column shift register 1 while the shift control signal is 1.
24a and two-column output buffers 125b, 125c, 12
5d performs the shift operation, and the output selector 126
Output to.

Two-dimensional of the present embodiment constructed as described above
The operation of the DCT arithmetic unit will be described below. The two-dimensional DCT operation device of the present embodiment reads an external linear memory, receives an input signal sequence f _ij consisting of 8 × 8 matrix blocks generated by the read, and receives a DCT for the received input signal sequence. Multi-stage pipeline processing is performed, and the resulting DCT coefficient sequence is output to the external linear memory. (1) The row read address generation unit 133 generates a row read address. The designation of the read column by the column read address generation unit 133 is 0, 7,
Change in the order of 1,6,2,5,3,4 lines and repeat this. (2) If the column read address generation unit 133 generates all the row numbers in one column, the column read address generation unit 134 generates the column read address. The designation of the read column by the column read address changes in the order of the 0th, 7th, 1st, 6th, 2nd, 5th, 3rd, and 4th columns each time one data is read, and this is repeated. (3) The linear address of the matrix component data in the external linear memory is calculated based on the column read address and the row read address. (4) The linear read address generation unit 131 reads out the 8 × 8 matrix for each component for each cycle, and generates the input signal sequence for each component. The input shift register 101 reads this input signal sequence while shifting it. The reading order is column by column, in the order of 0,7,1,6,2,5,3,4, and in the column the order of 0,7,1,6,2,5,3,4. Is. 1 17 33 49 57 41 25 9 3 19 35 51 59 43 27 11 5 21 37 53 61 45 29 13 7 23 39 55 63 47 31 15 8 24 40 56 64 48 32 16 6 22 38 54 62 46 30 14 4 20 36 52 60 44 28 12 2 18 34 50 58 42 26 10 (5) The input shift register 101 transfers the read two-component data to the input buffer 102 at a time. The input buffer 102 holds this data for two cycles. (6) The first adder / subtractor 103 first adds and then subtracts. After that, addition and subtraction are repeated alternately. Operations on j-th column data are f _0j + f _7j , f _0j −f _7j , f _{1j in the} order of cycle.
＋ f _6j , f _1j −f _6j , f _2j ＋ f _5j , f _2j −f _5j , f _3j ＋ f _4j , f _3j −f _4j
And this is repeated for the 0th, 7th, 1st, 6th, 2nd, 5th, 3rd, and 4th columns in order. (7) The first constant multiplier 104 outputs the product of each matrix element based on (Equation 12). The output products are sequentially accumulated and added by the first accumulator 105. The intermediate value being accumulated is held in the accumulation shift register 106. (8) The cumulative shift register 106 shifts and feeds back the held intermediate value to the first accumulator 105. If the steps of product and accumulation are repeated four times, an intermediate value for one column can be obtained. This intermediate value is a one-dimensional DCT coefficient. Accumulation for the 0th, 2nd, 4th, 6th rows and the 1st, 3rd, 5th, 7th rows are alternately repeated in one column. 64 such shifts
By repeating the cycle, the product of 8 × 8 matrices is calculated. (9) When the intermediate values for two components are stored in the cumulative shift register 106, these are transferred to the one-column buffer 111 as intermediate values for one column. (10) Accumulation shift register 106 and single column buffer 111
If two columns of intermediate values are stored in and, the contents of two columns are transferred to the two-column shift register 112 at once. (11) The two-column shift register 112 shifts the row numbers 0 to 7 in this order, and outputs the two-component data to the second adder / subtractor 12
Output to 1. The second adder / subtractor 121 calculates their sum or difference. The second adder / subtractor 121 first performs addition and then subtraction. After that, addition and subtraction are repeated alternately. The operation on the m-row data is h for each cycle.
_{m, 0} + h _{m, 7} , h _{m, 0-} h _{m, 7} , h _{m, 1} + h _{m, 6} , h _{m, 1} -h _{m, 6} , h
_{m, 2} + h _{m, 5} , h _{m, 2} −h _{m, 5} , h _{m, 3} + h _{m, 4} , h _{m, 3} −h _{m, 4} (m = 0,
・ ・ ・ ・, 7) is calculated. (12) The second constant multiplier 122 obtains the product of each matrix element based on (Equation 13), and sequentially adds the obtained value to the intermediate sum during accumulation. (13) The result of addition by the second accumulator 123 is output to the two-column shift register 124. Two-row shift register 124
Holds the addition result while sequentially shifting it. In the first cycle, four two-row shift registers 124a, 124
b, 124c, and 124d hold the intermediate value of the 0th row of the 0th, 2nd, 4th, and 6th columns, and the intermediate value of the 0th row of the 1st, 3rd, 5th, and 7th columns in the next cycle. This is repeated alternately and the line number is incremented. The relationship between each matrix element and the order of calculation in the first 16 cycles is shown in the table below. Components with the same number are calculated simultaneously. 1 2 1 2 1 2 1 2 3 4 3 4 3 4 3 4 5 6 5 6 5 6 5 6 7 8 7 8 7 8 7 8 9 10 9 10 9 10 9 10 11 12 11 12 11 12 11 12 13 14 13 14 13 14 13 14 15 16 15 16 15 16 15 16 If the above 16 cycles are repeated four times, the two-dimensional DCT operation is completed. Accumulation is performed four times for each component position. (14) Three two-column output buffers 125b, 125c, 1
25d, three two-row shift registers 124b,
124c and 124d output while holding the component that is being held. The two-row shift register 124a outputs the two components to the output selector 126 without going through the above output buffer. (15) The linear write address generator 136 generates a row write address and a column write address. The row write address is 0,0,1,1,2,
Change in the order of 2,3,3,4,4,5,5,6,6,7,7 lines, and repeat the specification for these two columns four times. The column write address increases in the order of the 0th and 1st columns every time two pieces of data are written. 2nd and 3rd in the next two rows
Repeat the columns, and then specify the 4th, 5th, and 6th and 7th columns every two columns. (16) Based on the column write address and the row write address, the linear write address generator 136 calculates the linear address of the matrix component data in the external linear memory. As shown in (17) (FIG. 8), the output selector 126 is
The calculated two-dimensional DCT coefficient is selectively output to the two-row shift register 124a in 16 cycles, and the contents of the three two-row shift registers 124b, 124c, and 124d are output to the three two-row output buffers 125b, 125c, and 125d during this period. Transferred while shifting. Thereafter, the contents of the three two-column output buffers 125b, 125c, 125d are sequentially selected and output by the output selector 126. The order of writing in the two-dimensional DCT coefficient matrix is as shown in the table below, as controlled by the write address. 1 2 17 18 33 34 49 50 3 4 19 20 35 36 51 52 5 6 21 22 37 38 53 54 7 8 23 24 39 40 55 56 9 10 25 26 41 42 57 58 11 12 27 28 43 44 59 60 13 14 29 30 45 46 61 62 15 16 31 32 47 48 63 64 The timing chart of the above pipeline processing is shown in (Fig. 9). The 1st DCT in the figure is the first-stage one-dimensional DCT.
2nd DCT means the second-stage one-dimensional DCT. It can be considered that the above multi-stage pipeline processing is roughly divided into the following three processing units. 1st stage: 1st dimensional DCT operation part of 1st stage: In the above explanation
Equivalent to (1) to (8) Second stage ... Intermediate buffer ... Equivalent to (9) to (10) in the above explanation Third stage ... One-dimensional DCT operation part of the second stage ... Above In explanation
Corresponding to (11) to (18) Although the 8 × 8 DCT is described in this embodiment, it can be easily expanded to 16 × 16 using the same arithmetic method. In addition to 16-bit bit width and number representation, it can be applied to 32-bit floating point numbers as well as fixed point numbers. Further, in the present embodiment, for convenience of description, the reading is performed in the column direction, but it is needless to say that a configuration in which the description regarding the rows and the columns is exchanged can be realized by transposing the constant matrix C.

[0064]

As described above, according to the two-dimensional DCT arithmetic device of the present invention, the data input / output order is optimally changed in the N × N pixel block, so that the same performance can be obtained with a smaller circuit scale. Can be demonstrated. Changing the input / output order of the component data in pixel block units can be easily realized in terms of system configuration. Moreover, since the internal shift register and the intermediate buffer are reduced, the latency of the DCT operation is reduced. Further, the conventional two-dimensional DCT arithmetic device is realized at a lower cost, and the latency time from inputting data to obtaining an arithmetic result is shortened, so that its practical effect is great.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a two-dimensional DCT calculation device of the present invention.

FIG. 2 is a configuration diagram of a linear write address generation unit 131.

FIG. 3 is a diagram showing an order of accumulation and multiplication performed by a first DCT calculation unit 100.

FIG. 4 is a diagram showing an order of accumulation and multiplication performed by a second DCT operation unit 120.

5 is a diagram showing the configuration of a linear write address generation unit 134. FIG.

FIG. 6 is a detailed diagram of constant multipliers 104 and 122 and accumulators 105 and 123 of FIG. 1;

FIG. 7 is a diagram showing a configuration of a CSA 502 (FIG. 6).

FIG. 8 is a dual column output buffer 125b, 125 of FIG. 1;
It is a figure which shows the timing of the shift control signal of c and 125d.

FIG. 9 is a timing chart of pipeline processing.

FIG. 10 is a block diagram of a conventional two-dimensional DCT arithmetic device.

11 is a circuit diagram of N × 1 (in particular, 8 × 1) DCT processors 203 and 207 in FIG. 10;

FIG. 12 is a block diagram of the RAC 317 of (FIG. 11).

[Explanation of symbols]

101 Input Shift Register 102 Input Buffer 103,121 Adder / Subtractor 104,122 Constant Multiplier 105,123 Accumulator 106 Accumulation Shift Register 111 One-row Buffer 112 Two-row Shift Register 124 Two-row Shift Register 125 Two-row Output Buffer 126 Output Selector 131 linear read address generation unit 132, 136 log ₂ N × 2 bit counter 133 row read address generation unit 134 column write address generation unit 135 linear write address generation unit

Claims (10)

[Claims] 1. A two-dimensional one-dimensional DCT calculation means, N × N
A two-dimensional DCT arithmetic device that performs a two-dimensional discrete cosine transform (abbreviated as DCT (Discrete Cosine Transform)) on a data matrix having a number of elements and writes each element of the transformation result matrix to an external memory, A reading means for reading the components corresponding to the order of the reading numbers shown in (Equation 1) one by one from the data matrix to be subjected to the two-dimensional DCT; A first one-dimensional DCT calculating means for performing a first-stage one-dimensional DCT on each of the two components read by the reading means, and generating a conversion result for each column; Second reading means for reading the two components of each of the two columns generated by the computing means in row order by two components, and the two components read by the second reading means for the second dimensional one-dimensional A second one-dimensional DCT operation means for performing a DCT to generate a matrix of the conversion result, and a writing means for writing the conversion result matrix generated by the second one-dimensional DCT operation means into the external memory one component at a time. A two-dimensional DCT calculation device characterized by being provided. 2. The first one-dimensional DCT means includes a first addition / subtraction means, a first constant multiplication means, and a first accumulation means, and the first addition / subtraction means is a reading means. The addition and subtraction of the two components read by the first constant multiplication means is the addition result by the first addition and subtraction means in the product sum calculation of one row × one column in the first-stage one-dimensional DCT. All partial products with the subtraction result as a multiplier are obtained, and the first accumulating means obtains the accumulated value of the partial products of the first constant multiplying means for one column of the addition / subtraction result, and the obtained accumulated value is the second value. The second one-dimensional DCT means has a second addition and subtraction means, a second constant multiplication means, and a second accumulation means, the second addition and subtraction means, The addition and subtraction of the two components read by the second reading means are performed, and the second constant multiplication means is In the one-row x one-column product-sum calculation in the second-stage one-dimensional DCT, all the partial products with the addition result and the subtraction result by the second addition and subtraction means as multipliers are obtained, and the second accumulation means is the addition and subtraction result. 2. The two-dimensional DCT arithmetic unit according to claim 1, wherein an accumulated value of partial products of the first constant multiplication means for one row is obtained, and the obtained accumulated value is output to the writing means. 3. The first addition / subtraction means has a two-stage shift register, a first input buffer, a second input buffer, and a first adder / subtractor, and the two-stage shift register is , The two components of the input signal sequence read out by the reading means are held by shifting by one component, and the first input buffer holds one component held by the preceding stage every time the two-stage shift register shifts twice. The second input buffer receives one component held by the second stage each time the two-stage shift register shifts twice, and the first adder / subtractor receives the components in the first input buffer and the second input buffer. The two constant components are alternately added and subtracted, and the first constant multiplication means has N / 2 first constant multipliers connected to the first adder / subtractor, Is a constant multiplier in the first-stage one-dimensional DCT. In the row-by-column product-sum calculation, the addition result and the subtraction result by the first adder-subtractor are used as multipliers, and a partial product in which one component of a predetermined matrix is used as a multiplicand is obtained, and the first accumulation means is N / 2 first adders connected to each of the N / 2 constant multipliers and N connected to each of the N / 2 first adders. / 2 two-stage shift register, and each first adder adds the product output from the first constant multiplier and the component output from the latter stage of the two-stage shift register. Then, each two-stage shift register holds the two components while shifting the components output by the first adder, and shifts the retained two components by one component to output the output of the subsequent stage to the first adder. To the second read-out means at once after feeding back to the second reading means after shifting N × 2 times Two-dimensional DCT operation device according to claim 2, wherein Rukoto. 4. The second reading means includes a one-column buffer, a first N-stage parallel / serial conversion shift register, and a second N-stage parallel / serial conversion shift register. The one-column buffer receives the components of one column sequentially generated by the first one-dimensional DCT calculation unit and holds them every other column, and the component of the column next to the held component is the first one-dimensional buffer.
When output from the DCT calculation means, the one-column component held until then is output to the first N-stage parallel / serial conversion shift register at once, and the first N-stage parallel / serial conversion is performed. The shift register for use holds one-column components output from the one-column buffer, shifts the held one-column components one component at a time, and performs one-column components one component at a time on the second one-dimensional DCT operation. The second N-stage shift register for parallel / serial conversion holds the one-column component output from the first one-dimensional DCT operation unit that was not received by the one-column buffer. 4. The two-dimensional DCT according to claim 3, wherein the held one-row components are shifted one by one, and the one-row components are output one by one to the second one-dimensional DCT calculation means. Arithmetic unit. 5. The second addition / subtraction means alternately performs addition and subtraction of the two components output by the second reading means, and the second constant multiplication means is connected to the second addition / subtraction means. N / 2 number of second constant multipliers, each of the second constant multipliers is the second addition / subtraction means in the 1-row × 1-column product-sum calculation in the second-stage one-dimensional DCT. The addition result and the subtraction result by, to obtain a partial product with one component in one row of a predetermined matrix as the multiplicand, the second accumulation means, the N / 2 second constant multiplier Of N / 2 second adders connected corresponding to each of, and N / 2 N × 2 shifts connected corresponding to the N / 2 second adders Each of the second adders has a product output from the second constant multiplier and a component output from the final stage of the N × 2 stage shift register. Each N × 2 stage shift register holds the two columns while shifting the component output from the second adder, and shifts the retained component one component at a time to output the final stage output. 5. The two-dimensional DCT calculation device according to claim 4, wherein the components of the two columns are output to the writing unit one by one after being fed back to the second adder and being shifted N × N times. 6. The accumulating means is further connected to N / 2-1 final stages other than a predetermined one of N / 2 N × 2 stages of shift registers, N / 2-1. It has N output buffers and an output selector, and N / 2-1 output buffers are composed of N × 2 stages of shift registers, and two columns for each component are output from the connected shift registers. Hold the components while shifting, and sequentially output the held components one by one to the output selector.The output selectors are each N × 2 stage shift register and
6. The two-dimensional DCT operation device according to claim 5, wherein the outputs of N / 2-1 output buffers are selected and output. 7. The two-dimensional DCT arithmetic device according to claim 3, wherein the constant multiplier has a ROM in which multiples of components of a predetermined matrix are stored in advance. . 8. The constant multiplier is a component of a constant matrix used for the one-dimensional DCT of the first and second stages as a predetermined matrix and / or discrete cosine of the first and second stages. Inverse transform (IDCT (Inverse Discrete Cosine
The two-dimensional structure according to claim 7, wherein components of a constant matrix used for (Transform) are stored in advance.
DCT arithmetic unit. 9. The read means comprises a read column generation means, a read row generation means, and a read address generation means, and the read column generation means has a data matrix having N × N components of components to be read. The read row generation means specifies the row number of the component to be read in the column designated by the read column generation means, and the read address generation means reads the column number generated by the read column generation means and the read number. A two-dimensional DCT arithmetic device, which generates an address in an external memory of a component to be read, from the line number generated by the line generation means. 10. The writing unit includes a write column generating unit, a write row generating unit, and a write address generating unit, and the write column generating unit is one of the elements of the matrix of the operation result.
The column number of the one to be written is generated, the write row generation means generates the row number of the component to be written in the column of the column number generated by the write column generation means, and the write address generation means is the write row generation means. 10. The address in the external memory for writing each component of the operation matrix is generated from the row number generated by the above and the column number generated by the write column generating means. 2D DCT computing device.