JP2901896B2 - Orthogonal transform processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an orthogonal transform processor suitably used for image information processing.

[0002]

2. Description of the Related Art In recent years, as an important part of a high-efficiency compression encoding method for two-dimensional image data, a small-scale circuit for realizing orthogonal transformation has been required. In the encoder, a forward orthogonal transform, for example, a discrete cosine transform (discrete cosine tr
ansform: DCT for short, discrete sine transform (discrete
sine transform: DST) is used.
In the decoder, an orthogonal transform in the reverse direction, for example, an inverse discrete cosine transform (I.sub.
DCT), inverse discretesine t
ransform: IDST for short) is used.

US Pat. No. 4,791,598 discloses a two-dimensional DCT processor comprising two one-dimensional DCT processors and a transposed memory interposed therebetween. Each of the two one-dimensional DCT processors is a distributed arithmetic (distributed arithmet) for obtaining a vector inner product using a ROM (read only memory) without using a multiplier.
ic: Abbreviated DA) circuit. The DA circuit has a plurality of ROM / accumulators.
(RAC for short). Each RAC includes a ROM in which a partial sum of a vector inner product based on a discrete cosine matrix is stored in the form of a look-up table, and a partial sum sequentially indexed from the ROM using a bit slice word as an address by digit-aligning and adding to an input vector. And an accumulator for obtaining a corresponding vector dot product. Such a configuration of the two-dimensional DCT processor can be applied to a two-dimensional IDCT processor.

The input data consisting of 8 × 8 elements has a two-dimensional I
DCT processing is performed. The input data is an element y _ij
It is represented by a matrix Y of 8 rows and 8 columns having (i = 0 to 7, j = 0 to 7). Also, consider an 8 × 8 inverse discrete cosine matrix D. Each element d _ij of the matrix D is represented by d _i0 = 1 / (2 · 2 ^0.5 ), i = 0 to 7 d _ij = (1/2) cos {(2i + 1) jπ / 16}, i = 0 to 7, j = 1 to 7 (1) 2D IDCT matrix Y is DYD ^T. Here, ^DT is the transposed matrix of the matrix D. One-dimensional IDCT for matrix Y, that is, one-dimensional I for calculating matrix product DY
By using the DCT processor and the transposing means, the intermediate matrix X = (DY) ^T can be easily obtained. The final result DYD ^T
Is similarly obtained. This is because, DYD ^T = (D
This is because (DY) ^T ) ^T = (DX) ^T. That is, the one-dimensional IDCT processor for calculating the matrix product DY plays an important role in realizing the two-dimensional IDCT.

[0005] The result of the one-dimensional IDCT on the j-th column of the matrix Y is represented by the j-th column of the matrix W having 8 rows and 8 columns. Here, each element w _ij of the matrix W is as follows: w _ij = Σ _{k =} ⁷ d _ik y _kj , i = 0 to 7, j = 0 to 7 (2) The element w _ij is an inner product of the i-th row of the matrix D and the j-th column of the matrix Y, and is a sum of eight products. This element w _ij
Is called an 8-point IDCT process.

[0006] A 1 comprising eight multipliers and eight accumulators
According to dimension IDCT processor, eight inner products w _0j constituting the j-th column of the matrix _{W, w 1j, w 2j,} w 3j, w 4j,
w _5j , w _6j , w _7j can be calculated in parallel. _{Here, w 0j = Σ k = 0} 7 d 0k y kj w 1j = Σ k = 0 7 d 1k y kj w 2j = Σ k = 0 7 d 2k y kj w 3j = Σ k = 0 7 d 3k y _kj w _4j = Σ _{k = 0} ⁷ d _{4ky kj} w _5j = Σ _{k = 0} ⁷ d _5k y _kj w _6j = Σ _{k = 0} ⁷ d _6k y _kj w _7j = Σ _{k = 0} ⁷ d _7k y _kj ... (3)

[0007]

The one-dimensional IDCT processor having the above-mentioned eight multipliers is a VLSI (very lar
There is a problem in that the multiplier occupies a large area on the chip when mounting on (ge scale integration).

Further, when the parallel calculation of the eight inner products represented by the equation (3) is realized by the above-mentioned conventional DA circuit, there is a problem that a large ROM size is required.

An object of the present invention is to reduce the circuit scale of an orthogonal transform processor such as a one-dimensional IDCT processor.

[0010]

In order to achieve the above-mentioned object, a first orthogonal transform processor according to the present invention comprises a number of multipliers in consideration of the regularity of an element of an inverse discrete cosine matrix or an inverse discrete sine matrix. And the result of each multiplier is distributed to a plurality of accumulators.

A second orthogonal transformation processor according to the present invention divides each of a plurality of inner product calculations into two constant multiplications and one partial inner product calculation, and performs constant multiplication of the two constant multiplications. This is to be executed by a circuit. In addition, the calculation of a plurality of partial inner products is performed in parallel by the DA circuit.

[0012]

According to the first orthogonal transform processor of the present invention, for example, in the case of 8-point IDCT processing, eight multipliers are conventionally required, but the number of multipliers is reduced to four or three.

According to the second orthogonal transform processor of the present invention, only two or one multiplier in the constant multiplication circuit is required. Further, since part of the inner product calculation is performed by the constant multiplication circuit, the ROM size of the DA circuit is reduced.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a one-dimensional IDCT processor according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) First, t _n (n = 0 to 7)
Is defined as t ₀ = 1 / (2 · 2 ^0.5 ) t _n = (１ ／) cos (nπ / 16), n = 1 to 7 (4) Then, the calculation of the eight inner products represented by the above equation (3) is expressed as shown in FIG. 1 using the symmetry of the cosine function.

In the matrix operation shown in FIG. 1, when the sign (±) is ignored, the coefficients to be _applied to y _0j are t ₀ , and the coefficients to be _applied to y _1j are t ₁ , t ₃ , t ₅ and t ₇ . , Y _2j are coefficients t ₂ , t ₆ , coefficients y _3j are t ₃ , t ₇ , t ₁ , t ₅ , coefficients y _4j are t ₄ , y _The coefficients to be multiplied by _5j are t ₅ and t
₁ , t ₇ and t ₃ , and the coefficients to be multiplied by y _6j are t ₆ ,
t ₂ , and the coefficients to be multiplied by y _7j are t ₇ , t ₅ ,
t ₃ and t ₁ . Accordingly, as shown in FIG. 2, when eight elements y _ij (i = 0 to 7) of the input data are sequentially supplied, a maximum of four multiplications may be performed in one cycle. FIG. 3 shows a coefficient matrix E used in the procedure of FIG.
The coefficient matrix E is a 4-row, 8-column matrix in which the absolute values of the elements from the 0th row to the 3rd row of the 8-row, 8-column inverse discrete cosine matrix in FIG. 1 are constituent elements.

One-dimensional IDC according to a first embodiment of the present invention
FIG. 4 shows the configuration of the T processor. This configuration employs the coefficient matrix E shown in FIG. In FIG. 4, 10
1 to 104 are first to fourth coefficient memories, 105 to 108
Denotes first to fourth multipliers, 109 to 116 denote first to eighth accumulators, and 117 denotes an eight-input selector. The first coefficient memory 101 has eight elements in the zeroth row of the matrix E, and the second coefficient memory 102 has eight elements in the first row of the matrix E.
The third coefficient memory 103 stores eight elements of the second row of the matrix E, and the fourth coefficient memory 104 stores eight elements of the third row of the matrix E.
Elements are stored respectively. From the input terminal, 2
Binary data y _ij (i = 0 to 7, j = 0 to 0)
_{7), y 00 ~y 70, y 01} ~y 71, ..., it is supplied to a multiplier 105 to 108 sequence in the first to fourth y ₀₇ ~y _77.
The first multiplier 105 multiplies y _{ij by} the output of the first coefficient memory 101, the second multiplier 106 multiplies y _{ij by} the output of the second coefficient memory 102, and the third multiplication Container 107
Is for multiplying y _{ij by} the output of the third coefficient memory 103, and the fourth multiplier 108 is for multiplying y _{ij by} the output of the fourth coefficient memory 104. 1st to 8th
Are stored in the first to fourth multipliers 105.
Eight of the inner product w _0j using the results of ~108, w _1j, w _2j,
Accumulation for _obtaining w _3j , w _4j , w _5j , w _6j , w _7j is performed in parallel. The eight-input selector 117 sequentially selects the results of the first to eighth accumulators 109 to 116 and converts the data w _ij (i = 0 to 7, j = 0 to 7) into w ₀₀ to
The output is performed in the order of w ₇₀ , w _{01 to} w ₇₁ ,..., w _{07 to} w ₇₇ .

An accumulator 110 for _obtaining w _1j in FIG.
Is shown in FIG. In FIG. 5, 201 is a 4-input selector, 202 is a two's complementer, 203 is an adder,
04 is an accumulation register and 205 is a buffer register. The four-input selector 201 includes the first to fourth multipliers 10
One of the results 5 to 108 is selected.
The two's complementer 202 passes the output of the four-input selector 201 as it is or outputs the two's complement of the output of the four-input selector 201 according to the value of i.
Specifically, the first of the inverse discrete cosine matrices in FIG.
Rows (t ₀ , t ₃ , t ₆ , -t ₇ , -t ₄ , -t ₁ , -t
₂ , −t ₅ ) and the input data vector (y _0j , y _1j ,
In response to the calculation of the inner product w _1j with y _2j , y _3j , y _4j , y _5j , y _6j , y _7j ), the output of the 4-input selector 201 is passed as it is in the cycle of i = 0, 1, and 2. , I = 3
In the cycles of 4, 5, 6, and 7, the output of the 4-input selector 201 is controlled to output the 2's complement. Data x
Complements all bits of x, plus 1
Is calculated by adding The adder 203
The sum of the result of the two's complementer 202 and the output held by the accumulation register 204 is obtained. The content held in the accumulation register 204 is initialized to 0 in advance, and is rewritten with the result of the adder 203. The buffer register 205 holds the output of the accumulation register 204 so as to guarantee the pipeline operation of the one-dimensional IDCT processor. The internal configuration of the other accumulators in FIG. 4 is the same as that in FIG.

The operation of the one-dimensional IDCT processor according to the first embodiment of the present invention will be described below with reference to FIGS.

[0020] In the first cycle, the data y ₀₀ is supplied from the input terminal. On the other hand, t ₀ , t ₀ , t ₀ , and t ₀ are read from the coefficient memories 101 to 104, respectively, and the four products t ₀ y ₀₀ , t ₀ y ₀₀ ,
t ₀ y ₀₀ and t ₀ y ₀₀ are calculated in parallel. Next, one of the results of the four multipliers 105 to 108 is selected by the four-input selector 201 of the accumulators 109 to 116, respectively. In this case, since the results of the four multipliers 105 to 108 are all the same, any one may be selected. Each of the two's complementers 202 of the accumulators 109 to 116 passes the output of the four-input selector 201 as it is. The adder 203 of the accumulators 109 to 116 calculates the sum of the result of the two's complementer 202 and the output of the accumulation register 204 which has been initialized to 0 in advance, and outputs the addition result to the accumulation register 204
Write to each. As a result, the accumulators 109 to 116
The same product t ₀ y ₀₀ is stored in all the accumulation registers 204.

[0021] In the second cycle, the data y ₁₀ is supplied from the input terminal. On the other hand, t ₁ , t ₃ , t ₅ , and t ₇ are read from the coefficient memories 101 to 104, respectively, and the four products t ₁ y ₁₀ , t ₃ y ₁₀ ,
_{t 5 y 10, t 7 y} 10 are calculated in parallel. Next, one of the results of the four multipliers 105 to 108 is selected by the four-input selector 201 of the accumulators 109 to 116, respectively. In this case, the result t ₁ y ₁₀ of the first accumulator 109 first multiplier 105, the result t ₃ y ₁₀ of the second accumulator 110 and the second multiplier 106, a third Accumulator 1
11, the result t ₅ y ₁₀ of the third multiplier 107 is output, and the fourth accumulator 112 is the result t ₇ y of the fourth multiplier 108.
₁₀ , the fifth accumulator 113 outputs the result t ₇ y ₁₀ of the fourth multiplier 108, and the sixth accumulator 114 outputs the third multiplier 1
Result t ₅ y ₁₀ 07, the result t ₃ y ₁₀ of the seventh accumulator 115 second multiplier 106, eighth the accumulator 116 of the first multiplier 105 result t ₁ y ₁₀ are selected respectively. The two's complementers 202 of the first to fourth accumulators 109 to 112 pass the output of the four-input selector 201 as they are. The two's complement units 202 of the fifth to eighth accumulators 113 to 116 each output the two's complement of the output of the four-input selector 201. The adders 203 of the accumulators 109 to 116 calculate the sum of the result of the two's complementer 202 and the output of the accumulation register 204, and write the addition result to the accumulation register 204. As a result, in the first accumulator 109, t ₀ y ₀₀ + t ₁ y ₁₀ is changed to the second accumulator 11
0 In _{t 0 y 00 + t 3 y} 10 is, in the third accumulator _{111 t 0 y 00 + t 5} y 10 is, t ₀ In the fourth accumulator 112 y
₀₀ + t ₇ y ₁₀ is equal to t ₀ y ₀₀ −t in the fifth accumulator 113.
₇ y ₁₀ is, t ₀ the accumulator 114 of the 6 y ₀₀ -t ₅ y ₁₀
But seventh accumulator 115 at t ₀ y ₀₀ -t ₃ y ₁₀ of, first _{8 t 0 y 00 -t 1 y} 10 In accumulator 116 is stored in the accumulator register 204, respectively.

[0022] In the third from the eighth cycle, the data _{y 20, y 30, y 40} , y 50, y 60, y 70 is sequentially supplied from the input terminal. Thus, at the end of the eighth cycle, the accumulator to the accumulator register 204 of 109 to 116, eight inner products _{w 00, w 10, w 20} , w 30, w 40, w 50, w 60, w 70 Is stored.

[0023] In the ninth cycle, from the input terminal is supplied with the data y ₀₁ together with the processing similar to the above first cycle is executed, the accumulation register 204 of the accumulator 109 to 116 holding contents w ₀₀ , W ₁₀ , w ₂₀ , w ₃₀ , w ₄₀ , w
₅₀ , w ₆₀ and w ₇₀ are transferred to the buffer register 205, respectively. The 8-input selector 117 selectively outputs the output w ₀₀ of the first accumulator 109.

In the tenth cycle, data y ₁₁ is supplied from the input terminal, and the same processing as in the second cycle is executed. 8-input selector 117 selectively outputs the output w ₁₀ of the second accumulator 110.

Thereafter, by repeating the same processing, the input data y _{00 to} y ₇₀ , y _{01 to} y ₇₁ , which are continuously supplied,
..., output data w _{00 to} w ₇₀ , w ₀₁ corresponding to y _{07 to} y _{77
~w 71, ..., w 07 ~w} 77 can be obtained continuously.

FIG. 6 shows a modification of the accumulator 110 shown in FIG. In the example of FIG. 6, a one's complementer 212 is used in place of the two's complementer 202. The one's complementer 212 passes the output of the four-input selector 201 as it is or outputs the one's complement of the output of the four-input selector 201 according to the value of i. Specifically, the first row (t ₀ , t ₃ ,
t ₆ , −t ₇ , −t ₄ , −t ₁ , −t ₂ , −t ₅ ) and input data vectors (y _0j , y _1j , y _2j , y _3j , y _4j , y
_5j, y _6j, in response to the calculation of the inner product w _1j of the y _7j), i =
In the cycles of 0, 1, and 2, the output of the 4-input selector 201 is passed as it is, and in the cycle of i = 3, 4, 5, 6, and 7, the output of the 4-input selector 201 is controlled to output the one's complement. You. The one's complement of data x is determined by inverting all bits of x. The initial value of the accumulation register 204 is set to the number of negative elements out of the eight elements constituting the first row of the inverse discrete cosine matrix, that is, five.

As described above, according to the first embodiment, a one-dimensional IDCT processor in which the number of multipliers is reduced to four can be realized. Note that the 4-input selector 201 (FIGS. 5 and 6) of the accumulators 109 to 116 may be omitted and fixed wiring may be employed. In this case, the first and eighth accumulators 109,
116, the result of the first multiplier 105 only, the second and seventh accumulators 110, 115 only the result of the second multiplier 106, the third and sixth accumulators 111, Only the result of the third multiplier 107 is supplied to 114, and only the result of the fourth multiplier 108 is supplied to the fourth and fifth accumulators 112 and 113, respectively.

(Embodiment 2) In order to perform the matrix operation of FIG. 1, it is necessary to execute 22 multiplications in eight cycles as shown in FIG. The average number of multiplications in one cycle is 2.75. Therefore, in the second embodiment, as shown in FIG. 7, eight elements y _ij (i = 0 to 7) of the input data
Are sequentially supplied, a maximum of three multiplications are performed in one cycle. Therefore, a register for holding the input element is provided so that the input element of the previous cycle can be used in addition to the input element of a certain cycle. That is, in a certain cycle, the coefficients t ₁ and t ₀ of the first group and the element y
_1j , y _0j is multiplied by the coefficient t of the second group in the next cycle.
_3, the multiplication of the t _5, t ₇ and element y _1j is coefficient t ₃ of the third group in the next cycle, t _2, t ₆ and element y _3j, multiplies the y _2j, in the next cycle the Four groups of coefficients t ₇ , t ₁ , t
₅ multiplies the and elements y _3j, coefficients t ₅ of the fifth group in the next cycle, t ₄ and element y _5j, multiplies the y _4j, coefficients t ₁ of the sixth group in the next cycle, t ₇ , T ₃ and the element y _5j are multiplied by the coefficients t ₇ , t ₆ , t ₂ of the seventh group in the next cycle.
And the elements y _7j , y _6j, and in the next cycle, the multiplication of the eighth group of coefficients t ₅ , t ₃ , t ₁ and the element y _7j are executed. The coefficient matrix G used in the procedure of FIG.
Shown in The coefficient matrix G has a 0-th column having three coefficients t ₁ , t ₀ , and t ₀ including the coefficients of the first group, and a first column having the coefficients t ₃ , t ₅ , and t ₇ of the second group. A second column having the third group of coefficients t ₃ , t ₂ , t _6, and a fourth group of coefficients t
_7, t _1, t and a third column with _5, the fourth column with three coefficients t _5, t _4, t ₄ containing the coefficients of the fifth group, the coefficient t ₁ of the sixth group, The fifth column having t ₇ and t ₃ and the seventh column
A third column composed of a sixth column having group coefficients t ₇ , t ₆ and t ₂ and a seventh column having coefficients t ₅ , t ₃ and t ₁ of the eighth group.
It is a matrix of 8 rows.

One-dimensional IDC according to a second embodiment of the present invention
FIG. 9 shows the configuration of the T processor. This configuration employs the coefficient matrix G shown in FIG. In FIG. 9, 30
1 is an input register, 302 to 304 are first to third coefficient memories, 305 is a two-input selector, 306 to 308 are first to third multipliers, 309 is a temporary register, 310 to 310
Reference numeral 17 denotes a first to eighth accumulators, and 318 denotes an 8-input selector. The first coefficient memory 302 stores 8 in the 0th row of the matrix G.
Elements are stored in the second coefficient memory 303 in the first coefficient of the matrix G.
The eight elements in the row are stored in the third coefficient memory 304 in the matrix G
Of the second row are stored. From the input terminal, binary number data y _ij (i = 0 to 2's complement notation)
7, j = 0~7) _{is, y 00 ~y 70, y 01} ~y 71, ..., y
In the order of ₀₇ ~y _77, it is supplied to the input register 301 and the 2-input selector 305. The two-input selector 305 determines whether the data supplied directly from the input terminal and the input register 301
Of the output data. First
Multiplier 306 multiplies the output of the two-input selector 305 by the output of the first coefficient memory 302,
7 is the output of the input register 301 and the second coefficient memory 30
The third multiplier 308 executes multiplication of the output of the input register 301 and the output of the second coefficient memory 304, respectively. Temporary register 309
Is to temporarily hold the output of the first multiplier 306. The first to eighth accumulators 310 to 317 store output data of the temporary register 309 and first to third multipliers 306 to 306.
08 and the eight inner products w _0j , w _1j , w _2j , w
Accumulation for _{obtaining 3j} , _w4j , _w5j , _w6j , _w7j is performed in parallel, and the internal configuration of each is as shown in FIG. 5 or FIG. The 8-input selector 318 sequentially selects the results of the first to eighth accumulators 310 to 317 and converts the data w _ij (i = 0 to 7, j = 0 to 7) into w ₀₀ to w ₇₀ , w
₀₁ ~w _71, ..., and outputs in the order of w ₀₇ ~w _77.

The operation of the one-dimensional IDCT processor according to the second embodiment of the present invention will be described below with reference to FIGS.

[0031] In the first cycle, the data y ₀₀ is supplied from the input terminal. Further, at the end of the first cycle,
The data y ₀₀ is written to the input register 301.

[0032] In the second cycle, the data y ₁₀ is supplied from the input terminal, the data y ₁₀ is the two-input selector 305
Is selected by On the other hand, t ₁ , t ₀ , and t ₀ are read from the coefficient memories 302 to 304, respectively, and
6 to 308, the three products t ₁ y ₁₀ , t ₀ y ₀₀ , t ₀ y
₀₀ are calculated in parallel. Next, the second and third multipliers 3 are input by the four-input selector 201 of the accumulators 310 to 317.
One of the results of 07, 308 is selected, respectively. In this case, the results of the second and third multipliers 307 and 308 are the same, and either may be selected. Each of the two's complementers 202 of the accumulators 310 to 317 passes the output of the four-input selector 201 as it is. The adder 203 of the accumulators 310 to 317 calculates the sum of the result of the two's complementer 202 and the output of the accumulation register 204 which has been initialized to 0 in advance, and outputs the addition result to the accumulation register 204.
Write to each. As a result, the accumulators 310 to 317
, The same product t ₀ y ₀₀ is stored in all the accumulation registers 204. Further, at the end of the second cycle, the data y ₁₀
Is written to the input register 301, and the result t ₁ y ₁₀ of the first multiplier 306 is written to the temporary register 309.

[0033] In the third cycle, the data y ₂₀ is supplied from the input terminal. 2-input selector 305 selects the output data y ₁₀ of the input register 301. On the other hand, t ₃ , t ₅ , and t ₇ are read from the coefficient memories 302 to 304, respectively, and the _three products t ₃ y are calculated by the multipliers 306 to 308.
_{10, t 5 y 10, t} 7 y 10 are calculated in parallel. Next, the output data of the temporary register 309 and the three multipliers 306 to 306 are output by the four-input selector 201 of the accumulators 310 to 317.
One of each of the results of 308 is selected. In this case, the first accumulator 310 outputs the output data t ₁ y _{10 of the} temporary register 309, the second accumulator 311 outputs the result t ₃ y ₁₀ of the first multiplier 306, and outputs the third accumulation results t ₅ y ₁₀ of the vessel 312 a second multiplier 307, the result t ₇ y ₁₀ of the fourth accumulator 313 the third multiplier 308, a fifth
In the accumulator 314, the result t ₇ y _{10 of} the third multiplier 308
But sixth result t ₅ y ₁₀ of the accumulator 315 the second multiplier 307 of the seventh multiplier 30 accumulator in 316 first of
Results t ₃ y ₁₀ of 6, the output data t ₁ y ₁₀ of the eighth accumulators in 317 temporary register 309 is selected. Two's complementer 2 of first to fourth accumulators 310 to 313
02 passes the output of the 4-input selector 201 as it is. Fifth to eighth accumulators 314 to 317-2
Output the two's complement of the output of the four-input selector 201, respectively. The adder 203 of the accumulators 310 to 317 stores the result of the two's complementer 202 and the accumulation register 2
The sum of the sum of the output and the sum of the outputs is calculated, and the sum is written to the accumulation register 204. As a result, in the first accumulator 310, t ₀ y ₀₀ + t ₁ y ₁₀ is converted into the second accumulator 311.
In the third accumulator 312, t ₀ y ₀₀ + t ₃ y _10
0 y ₀₀ + t ₅ y ₁₀ is output to the fourth accumulator 313 by t ₀ y ₀₀
+ T ₇ y ₁₀ is equal to t ₀ y ₀₀ −t _{7 in} the fifth accumulator 314.
y ₁₀ is equal to t ₀ y ₀₀ −t ₅ y in the sixth accumulator 315.
₁₀ in the seventh accumulator 316, t ₀ y ₀₀ −t ₃ y ₁₀
T ₀ y ₀₀ -t ₁ y ₁₀ In accumulator 317 eighth is stored in the accumulator register 204, respectively. Further, at the end of the third cycle, the data y ₂₀ is written to the input register 301 and the result t ₃ y ₁₀ of the first multiplier 306 is written to the temporary register 309.

[0034] In the fourth cycle, the data y ₃₀ is supplied from the input terminal, the data y ₃₀ is the two-input selector 305
Is selected by On the other hand, t ₃ , t ₂ , and t ₆ are read from the coefficient memories 302 to 304, respectively, and
6-308 by three product _{t 3 y 30, t 2 y} 20, t 6 y
₂₀ are calculated in parallel. Next, the second and third multipliers 3 are input by the four-input selector 201 of the accumulators 310 to 317.
One of the results of 07, 308 is selected, respectively. In this case, the first, fourth, fifth and eighth accumulators 31
At 0, 313, 314, and 317, the result t ₂ y ₂₀ of the second multiplier 307 is stored in the second, third, sixth, and seventh accumulators 3
In 11, 312, 315 and 316, the third multiplier 308
As a result, t ₆ y ₂₀ is selected. The two's complementers 202 of the first, second, seventh, and eighth accumulators 310, 311, 316, and 317 each pass the output of the four-input selector 201 as it is. Third to sixth accumulators 312
The two's complement units 202 to 315 output the two's complement of the output of the four-input selector 201, respectively. Accumulator 310
The adder 203 at 317 calculates the sum of the result of the two's complementer 202 and the output of the accumulation register 204, and writes the addition result to the accumulation register 204. As a result,
In the first accumulator _{310 t 0 y 00 + t 1} y 10 + t 2 y 20
However, in the second accumulator 311, t ₀ y ₀₀ + t ₃ y ₁₀ + t ₆
In the third accumulator 312, y ₂₀ is equal to t ₀ y ₀₀ + t ₅ y ₁₀ −
t ₆ y ₂₀ is equal to t ₀ y ₀₀ + t ₇ y in the fourth accumulator 313.
₁₀ −t ₂ y ₂₀ is calculated by the fifth accumulator 314 as t ₀ y ₀₀ −t.
₇ y ₁₀ −t ₂ y ₂₀ is calculated by the sixth accumulator 315 as t ₀ y ₀₀
−t ₅ y ₁₀ −t ₆ y ₂₀ is equal to t _{0 in} the seventh accumulator 316.
_{y 00 -t 3 y 10 + t} 6 y 20 is the eighth accumulator 317 at _{t 0 y 00 -t 1 y 10} + t 2 y 20 of is stored in the accumulator register 204, respectively. Further, at the end of the fourth cycle, the data y ₃₀ is written to the input register 301, and the result t ₃ y _{30 of} the first multiplier 306 is stored in the temporary register 309.
Is written to.

In the fifth cycle, data y ₄₀ is supplied from the input terminal. 2-input selector 305 selects the output data y ₃₀ of the input register 301. On the other hand, t ₇ , t ₁ , and t ₅ are read from the coefficient memories 302 to 304, respectively, and the three products t ₇ y are calculated by the multipliers 306 to 308.
₃₀ , t ₁ y ₃₀ and t ₅ y ₃₀ are calculated in parallel. Next, the output data of the temporary register 309 and the three multipliers 306 to 306 are output by the four-input selector 201 of the accumulators 310 to 317.
One of each of the results of 308 is selected. In this case, the first accumulator 310 outputs the output data t ₃ y _{30 of the} temporary register 309, the second accumulator 311 outputs the result t ₇ y ₃₀ of the first multiplier 306, and outputs the third accumulation The result t ₁ y ₃₀ of the second multiplier 307 is output by the multiplier 312, and the result t ₅ y _{30 of} the third multiplier 308 is output by the fourth accumulator 313.
In the accumulator 314, the result t ₅ y _{30 of} the third multiplier 308
However, the result t ₁ y ₃₀ of the second multiplier 307 in the sixth accumulator 315 and the first multiplier ₃₀ in the seventh accumulator 316
Results t ₇ y ₃₀ of 6, the output data t ₃ y ₃₀ of the eighth accumulators in 317 temporary register 309 is selected. First, fifth, sixth and seventh accumulators 310, 31
The four's complementer 202 of 4,315,316 is 4
The output of the input selector 201 is passed as it is. Second, third, fourth and eighth accumulators 311, 312, 31
3,317 two's complement units 202 each output the two's complement of the output of the four-input selector 201. Accumulator 310
The adders 203 to 317 calculate the sum of the result of the two's complementer 202 and the output of the accumulation register 204, and write the addition result to the accumulation register 204. As a result, in the first accumulator _{310 t 0 y 00 + t 1} y 10 + t 2
y ₂₀ + t ₃ y ₃₀ is calculated by the second accumulator 311 as t ₀ y ₀₀ +
_{t 3 y 10 + t 6 y} 20 -t 7 y 30 is a third accumulator 312
In _{t 0 y 00 + t 5 y} 10 -t 6 y 20 -t 1 y 30 is a fourth
In the accumulator 313, t ₀ y ₀₀ + t ₇ y ₁₀ −t ₂ y ₂₀ −t
₅ y ₃₀ is equal to t ₀ y ₀₀ −t ₇ y _{10 in} the fifth accumulator 314.
−t ₂ y ₂₀ + t ₅ y ₃₀ is equal to t _{0 in} the sixth accumulator 315.
_{y 00 -t 5 y 10 -t 6} y 20 + t 1 y 30 is the 7 t ₀ the accumulator 316 _{y 00 -t 3 y 10 + t} 6 y 20 + t 7 y
_In the eighth accumulator 317, t ₀ y ₀₀ −t ₁ y ₁₀ + t
₂ y ₂₀ -t ₃ y ₃₀ is stored in the accumulator register 204, respectively. Further, at the end of the fifth cycle, the data y ₄₀
Is written to the input register 301, and the result t ₇ y ₃₀ of the first multiplier 306 is written to the temporary register 309.

In the sixth to ninth cycles, data y ₅₀ , y ₆₀ , y ₇₀ and y ₀₁ are sequentially supplied from the input terminals. Therefore, at the end of the ninth cycle, the accumulators 310 to 3
In the 17 accumulation registers 204, eight inner products w ₀₀ , w ₁₀ ,
_{w 20, w 30, w 40} , w 50, w 60, w 70 are stored. Further, at the end of the ninth cycle, the data y ₀₁ is written to the input register 301 and the result t ₅ y ₇₀ of the first multiplier 306 is written to the temporary register 309.

In the tenth cycle, data y ₁₁ is supplied from the input terminal, the same processing as in the second cycle is executed, and the contents w ₀₀ of the accumulation register 204 of the accumulators 310 to 317 are held. , W ₁₀ , w ₂₀ , w ₃₀ , w ₄₀ ,
w ₅₀ , w ₆₀ , and w ₇₀ are transferred to the buffer register 205, respectively. The 8-input selector 318 selectively outputs the output w ₀₀ of the first accumulator 310.

Thereafter, by repeating the same processing, the input data y _{00 to} y ₇₀ , y _{01 to} y ₇₁ , which are continuously supplied,
..., output data w _{00 to} w ₇₀ , w ₀₁ corresponding to y _{07 to} y _{77
~w 71, ..., w 07 ~w} 77 can be obtained continuously.

As described above, according to the second embodiment, a one-dimensional IDCT processor in which the number of multipliers is reduced to three can be realized.

(Embodiment 3) From equation (4), it can be immediately understood that t ₀ = t ₄ . Using this relationship, equation (2) _{is, w ij = d i0 y 0j} + Σ k = 1 3 d ik y kj + d i4 y 4j + Σ k = 5 7 d ik y kj = t 0 y 0j + Σ k = 1 ^{_{3 d ik y kj ± t 0}} y 4j + Σ k = 5 7 d ik y kj = t 0 y 0j ± t 0 y 4j + Σ k = 1 3 d ik y kj + Σ k = 5 7 d ik y kj = t 0 y _0j ± t ₀ y _4j + ω _ij (5) Here, “±” in equation (5) is
"+" when i = 0,3,4,7, i = 1,2,2
In the case of 5, 6, it means "-", respectively (see FIG. 1). Further, omega _ij in equation (5) is a partial inner product is a ^{_{ω ij = Σ k = 1 3}} d ik y kj + Σ k = 5 7 d ik y kj ... (6). According to equation (6), the size of the matrix operation in FIG. 1 is reduced as shown in FIG.

One-dimensional IDC according to a third embodiment of the present invention
FIG. 11 shows the configuration of the T processor. This configuration executes the calculation of the equation (5). In FIG.
Reference numeral 10 denotes an input buffer, 11 denotes a constant multiplication circuit, 12 denotes a distribution operation (DA) circuit, and 13 denotes a synthesis operation (RA) circuit. From the input terminal, binary data y _ij (i = 0 to 7, j = 0 to 7) represented by 2's complement with a 16-bit length are input to y _{00 to} y
_{70, y 01 ~y 71, ...} , is supplied to the input buffer 10 in the order of y ₀₇ ~y _77. The input buffer 10 stores data y _0j ,
y _4j is _supplied to the constant multiplication circuit 11 and data y _1j , y _2j , y _3j ,
y _5j , y _6j , and y _7j are supplied to the DA circuit 12, respectively.
The constant multiplication circuit 11 performs two constant multiplications t ₀ y _0j and t ₀ y
_4j . The DA circuit 12 obtains the partial inner product ω _ij by executing the matrix operation shown in FIG. The RA circuit 13 _calculates t ₀ y _0j , t ₀ y _4j and ω _{ij
Is used} to determine the inner product w _ij according to equation (5).

FIG. 12 shows the internal configuration of the input buffer 10. The input buffer 10 stores data y _0j , y _1j ,
y _2j, composed of _{y 3j, y 4j, y 5j} , y 6j, 8 pieces of registers 400 to 407 for holding the y _7j.

FIG. 13 shows the internal configuration of the constant multiplication circuit 11. The constant multiplication circuit 11 has an input register 410 for holding data y _0j , an input register 411 for holding data y _4j, and a two-input selector for sequentially selecting two data y _0j and y _4j. 412 and a multiplier 413 for sequentially executing two constant multiplications t ₀ y _0j and t ₀ y _4j.
And a temporary register 414 for holding the product t ₀ y _0j
And a temporary register 415 for holding the product t ₀ y _4j
And two buffer registers 416 and 41 for holding the outputs of both temporary registers 414 and 415 so as to guarantee the pipeline operation of the one-dimensional IDCT processor.
7 is comprised.

FIG. 14 shows the internal configuration of the DA circuit 12.
The DA circuit 12 includes six shift registers 420 to 425.
, Eight 6-bit input RACs 426 to 433, eight buffer registers 434 to 441, and an eight-input selector 442. Shift registers 420 to 425
Holds data y _1j , y _2j , y _3j , y _5j , y _6j , and y _7j , and shifts out the least significant two bits one after another. The least significant bit of each of shift registers 420 to 425 is a first bit slice word q ₀ , and the bit one digit higher than the least significant bit is a second bit slice word q ₁ , each having a 6-bit input RAC 426 to 433. Supplied to 6-bit input RA
C426, as shown in FIG.
, A second ROM 72, a three-input adder / subtractor 73, a shifter 74, and an accumulation register 75. First R
The OM 71 receives the first bit slice word q ₀ as an address and calculates the partial sum of the corresponding vector dot product by 3
It is supplied to the input adder / subtractor 73 as a first input. The second ROM 72 receives the second bit slice word q ₁ as an address, and supplies the partial sum of the corresponding vector inner product to the three-input adder / subtractor 73 as a second input. The output held by the accumulation register 75 is supplied to the three-input adder / subtractor 73 as a third input. However, the second input has a weight one bit higher than the first and third inputs. The content held in the accumulation register 75 is initialized to 0 in advance. The three-input adder / subtractor 73 includes first to third
Is performed. However, the partial sum of the last bit slice word q _1, executes the subtraction. The shifter 74 is a left shifter for shifting the digit of the result of the three-input adder / subtracter 73. The content held in the accumulation register 75 is rewritten to the output of the shifter 74. Finally, the partial inner product ω _0j is output from the accumulation register 75. The internal configuration of another 6-bit input RAC in FIG. 14 is the same as that in FIG. Therefore, eight 6-bit inputs R
In AC 426 to 433, eight partial inner products ω _0j , ω _1j ,
ω _2j , ω _3j , ω _4j , ω _5j , ω _6j , ω _7j are obtained in parallel. The buffer registers 434 to 441 store the one-dimensional I
The outputs of the 6-bit input RACs 426 to 433 are held so as to guarantee the pipeline operation of the DCT processor. The 8-input selector 442 sequentially selects the data held in the buffer registers 434 to 441, and converts the partial inner product ω _ij (i = 0 to 7, j = 0 to 7) into ω _0j , ω _1j ,
ω _2j , ω _3j , ω _4j , ω _5j , ω _6j , and ω _7j are output in this order.

FIG. 16 shows the internal configuration of the RA circuit 13.
The RA circuit 13 performs addition and subtraction of the two products t ₀ y _0j and t ₀ y _4j supplied from the constant multiplication circuit 11 and the partial inner product ω _ij supplied from the DA circuit 12 to obtain an inner product w _ij . It comprises a three-input adder / subtractor 450 for obtaining. However, for the product t ₀ y _4j , addition or subtraction is selected according to the value of i according to equation (5). Specifically, i = 0,
In cycles 3, 4, and 7, addition is selected, and i = 1, 2, 2,
In cycles 5 and 6, control is performed to select subtraction.

The operation of the one-dimensional IDCT processor according to the third embodiment of the present invention will be described below with reference to FIGS.

In the first to eighth cycles, the eight data y ₀₀ , y ₁₀ , y ₂₀ ,
_{y 30, y 40, y 50} , y 60, y 70 are sequentially inputted. These data are stored in registers 400 to 407, respectively.

In the ninth cycle, the data in the input buffer 10 is transferred to the constant multiplication circuit 11 and the DA circuit 12. That is, the data y _00, y ₄₀ to the input register 410, 411 of the constant multiplier circuit 11, the data y _10, y _20, y
₃₀ , y ₅₀ , y ₆₀ , and y ₇₀ are stored in shift registers 420 to 425 of the DA circuit 12, respectively.

In the tenth to thirteenth cycles, the data y ₀₀ is selected by the two-input selector 412 of the constant multiplication circuit 11, the constant multiplication t ₀ y ₀₀ is executed by the multiplier 413, and the result is stored in the temporary register 414. Written.
In the fourteenth to seventeenth cycles, the two-input selector 41
2, the data y ₄₀ is selected, the constant multiplication t ₀ y ₄₀ is executed by the multiplier 413, and the result is stored in the temporary register 4
15 is written. On the other hand, in the DA circuit 12, the tenth
To the seventeenth cycle, the 6-bit input RAC4
26 to 433, the eight partial inner products ω ₀₀ , ω ₁₀ , ω ₂₀ ,
ω ₃₀ , ω ₄₀ , ω ₅₀ , ω ₆₀ , ω ₇₀ are obtained.

In the eighteenth cycle, the constant multiplication circuit 11
The data held in the temporary registers 414 and 415 are transferred to the buffer registers 416 and 417, and the output data from the 6-bit input RACs 426 to 433 of the DA circuit 12 are transferred to the buffer registers 434 to 441, respectively.

In the nineteenth through twenty-sixth cycles, the 8-input selector 442 of the DA circuit 12 sets the partial inner products ω ₀₀ , ω ₁₀ ,
ω ₂₀ , ω ₃₀ , ω ₄₀ , ω ₅₀ , ω ₆₀ and ω ₇₀ are sequentially supplied to the RA circuit 13. On the other hand, the products t ₀ y ₀₀ and t ₀ y ₄₀ are supplied from the constant operation circuit 11 to the RA circuit 13. RA circuit 11
The three-input adder / subtractor 450 calculates the inner product w according to equation (5).
_{00, w 10, w 20,} w 30, w 40, w 50, and sequentially outputs w _60, w _70.

The next eight data y ₀₁ , y ₁₁ , y ₂₁ ,
The processing related to y ₃₁ , y ₄₁ , y ₅₁ , y ₆₁ , and y ₇₁ is performed in the ninth to thirty-fourth cycles in the same manner as the processing in the first to twenty-sixth cycles. As a result, the inner products w ₀₁ , w ₁₁ , w ₂₁ , w ₃₁ ,
w ₄₁ , w ₅₁ , w ₆₁ , w ₇₁ are sequentially output.

By repeating the same processing as described above, the input data y _{00 to} y ₇₀ , y _{01 to} y ₇₁ , and the continuously supplied input data y _{00 to} y ₇₀ ,
..., output data w _{00 to} w ₇₀ , w ₀₁ corresponding to y _{07 to} y _{77
~w 71, ..., w 07 ~w} 77 can be obtained continuously.

As described above, according to the third embodiment, a one-dimensional IDCT processor in which the number of multipliers is reduced to one can be realized. Moreover, the multiplier 4 in the constant multiplication circuit 11
13 has a smaller circuit scale than a two-variable input multiplier. Further, since a part of the inner product calculation is performed by the constant multiplication circuit 11, the ROM size of the DA circuit 12 is reduced.

Hereinafter, a modification of the third embodiment will be described. Equation (5) is modified as follows: w _ij = t ₀ (y _0j ± y _4j ) + ω _ij (7) Here, “±” in equation (7) is
"+" when i = 0,3,4,7, i = 1,2,2
In the case of 5, 6, it means "-", respectively (see FIG. 1). The constant multiplication circuit 11 of FIG. 17 and the RA circuit 13 of FIG. 18 employ the calculation procedure of Expression (7).

The constant multiplication circuit 11 shown in FIG. 17 includes an input register 500 for holding data y _0j , an input register 501 for holding data y _4j , and an addition y _0j
+ Y _4j and subtraction y _0j −y _4j for sequentially executing two-input adder / subtractor 502 and two constant multiplications t ₀ (y _0j +
y _4j ), a multiplier 503 for sequentially executing t ₀ (y _0j −y _4j ), a temporary register 504 for holding the product t ₀ (y _0j + y _4j ), and a product t ₀ (y _0j − y _4j ), and both temporary registers 504 and 504.
It is composed of two buffer registers 506 and 507 for holding the output of 505.

When the constant multiplication circuit 11 of FIG. 17 is employed, the RA circuit 13 of FIG. 16 is modified as shown in FIG. The RA circuit 13 in FIG. 18 includes two products t ₀ (y _0j + y _4j ) and t ₀ (y _0j −y) supplied from the constant multiplication circuit 11.
_4j ), and the addition of the product selected by the two-input selector 510 and the partial inner product ω _ij supplied from the DA circuit 12 to execute the inner product w and a two-input adder 511 for _{obtaining ij} . According to equation (7), 2-input selector 510 determines that t ₀ (y _0j +
y _4j ), and in the cycle of i = 1, 2, 5, 6, t
₀ (y _0j −y _4j ) is controlled.

The matrix operation shown in FIG. 10 is modified as shown in FIG. Half of the elements of the matrix of 8 rows and 6 columns in FIG. 19 are 0. Therefore, the matrix operation of FIG.
It is divided into two as shown in FIG. The four partial inner products ρ _0j , ρ _1j , ρ _2j , ρ _{3j in FIG.
Are} four 2-bit input RACs, and the four partial inner products σ _0j , σ _1j , σ _2j , and σ _3j in FIG. _20B can be obtained by the four 4-bit input RACs. FIG.
From (a) and FIG. 20 (b), ω _0j = ρ _0j + σ _0j ω _1j = ρ _1j + σ _1j ω _2j = ρ _2j + σ _2j ω _3j = ρ _3j + σ _3j ω _4j = ρ _3j -σ _3j ω _5j = It can be seen that ρ _2j −σ _2j ω _6j = ρ _{1j −σ 1j} ω _7j = ρ _{0j −σ 0j} (8). The DA circuit 12 in FIG.
The matrix calculations shown in FIGS. 20A and 20B are respectively executed by RAC, and the partial inner product ω _ij is obtained by using Expression (8).

The DA circuit 12 shown in FIG. 21 includes six shift registers 700 to 705 and four 4-bit input RAC7s.
06 to 709 and four 2-bit input RACs 710 to 7
13, eight buffer registers 714 to 721, a first four-input selector 722, and a second four-input selector 7.
23 and a two-input adder / subtractor 724. The shift registers 700 to 705 store data y _1j , y _2j , y
_3j , _y5j , _y6j , and _y7j are held, and the least significant two bits are shifted out one after another. Least significant bit of each of the four shift registers 700,702,703,705 as first bit slice word s _0, as a bit slice word s ₁ bit of the second order of magnitude higher than the least significant bit of each Each 4-bit input RAC7
06 to 709. Two shift registers 70
1, 704, the least significant bit of which is supplied as a third bit slice word r ₀ , and the bit one digit higher than the least significant bit is supplied as a fourth bit slice word r ₁ to the 2-bit inputs RAC 710-713, respectively. Is done.
As shown in FIG. 22, the 4-bit input RAC 706 includes a first ROM 81, a second ROM 82, a three-input adder / subtractor 83, a shifter 84, and an accumulation register 85. The internal configuration of another 4-bit input RAC in FIG. 21 is the same as that in FIG. Therefore, four partial inner products σ _0j , σ _1j , σ are obtained by four 4-bit inputs RAC 706 to ₇₀₉ .
_2j and σ _3j are obtained in parallel. 2-bit input RAC71
0 is the first ROM 91 and the second ROM 91, as shown in FIG.
ROM 92, 3-input adder / subtractor 93, and shifter 94
And an accumulation register 95. The internal configuration of another 2-bit input RAC in FIG. 21 is the same as that in FIG.
Therefore, four 2-bit inputs RAC 710-713
, Four partial inner products ρ _0j , ρ _1j , ρ _2j , ρ _3j are obtained in parallel. The buffer registers 714 to 721 hold the outputs of the eight RACs 706 to 713 so as to guarantee the pipeline operation of the one-dimensional IDCT processor. The first four-input selector 722 selects the data held in the buffer registers 714 to 717 and inputs the partial inner products σ _0j , σ _1j , σ _2j , σ _3j , σ _3j , σ _2j , σ _1j , and σ _0j. These are sequentially supplied to the adder / subtractor 724. Second
Of the buffer registers 718 to
721 is selected, and the partial inner products ρ _0j , ρ _1j ,
ρ _2j , ρ _3j , ρ _3j , ρ _2j , ρ _1j , and ρ _0j are sequentially supplied to the two-input adder / subtractor 724. 2-input adder / subtractor 72
4 executes addition / subtraction according to the equation (8).
That is, the partial inner product ω _ij (i = 0 to 7, j = 0 to 7)
Ω _0j , ω _1j , ω _2j , ω _3j , ω _4j , ω _5j , ω _6j , ω _7j
Are output from the two-input adder / subtractor 724 in the following order.

The internal configurations of the constant operation circuit 11 and the RA circuit 13 in FIG. 11 are appropriately selected from a combination of FIGS. 13 and 16 and a combination of FIGS. 17 and 18. The internal configuration of the DA circuit 12 in FIG.
4 and FIG. 21 or the like.

In the first to third embodiments, the 8-point IDCT processing has been described.
Point IDCT processing, 8-point IDST processing, 16
It can be easily transformed into a point IDST process or the like.

[0062]

As described above, according to the present invention, the required number of multipliers is greatly reduced, and as a result, the circuit scale of the orthogonal transform processor is reduced. Further, if each of the plurality of inner product calculations is divided into two constant multiplications and one partial inner product calculation, the ROM size is reduced as compared with the case where all the inner product calculations are realized by DA circuits. As a result, the circuit scale of the orthogonal transform processor is reduced.

[Brief description of the drawings]

FIG. 1 illustrates a matrix operation to be performed by an IDCT processor according to the present invention.

FIG. 2 is a diagram showing one execution procedure of the matrix operation of FIG. 1;

FIG. 3 is a diagram showing a coefficient matrix used in the procedure of FIG. 2;

FIG. 4 is a configuration diagram of an IDCT processor according to the first embodiment of the present invention, which employs the coefficient matrix of FIG. 3;

FIG. 5 is an internal configuration diagram of one accumulator in FIG. 4;

FIG. 6 is a diagram showing a modification of the accumulator of FIG.

FIG. 7 is a diagram showing another execution procedure of the matrix operation of FIG. 1;

FIG. 8 is a diagram showing a coefficient matrix used in the procedure of FIG. 7;

FIG. 9 is a configuration diagram of an IDCT processor according to a second embodiment of the present invention employing the coefficient matrix of FIG. 8;

FIG. 10 is a diagram showing a part of the matrix operation of FIG. 1;

FIG. 11 is a configuration diagram of an IDCT processor according to a third embodiment of the present invention.

FIG. 12 is an internal configuration diagram of an input buffer in FIG. 11;

13 is an internal configuration diagram of a constant multiplication circuit in FIG.

14 is an internal configuration diagram of the distribution operation circuit in FIG.

FIG. 15 for performing the matrix operation of FIG. 10;
FIG. 4 is an internal configuration diagram of one of the 6-bit input RACs.

FIG. 16 is an internal configuration diagram of the synthesis operation circuit in FIG. 11;

FIG. 17 is a diagram illustrating a modification of the constant multiplication circuit of FIG. 13;

18 is an internal configuration diagram of a synthesis operation circuit in the IDCT processor employing the constant multiplication circuit of FIG.

FIG. 19 is a diagram illustrating a matrix operation derived from FIG. 10;

FIGS. 20 (a) and (b) are two divisions of FIG.
FIG. 7 is a diagram showing two matrix operations.

FIG. 21 is a diagram illustrating a modification of the distribution calculation circuit of FIG. 14;

FIG. 22 is a diagram for explaining the matrix operation shown in FIG.
FIG. 22 is an internal configuration diagram of one 4-bit input RAC in FIG. 21.

FIG. 23 is a diagram for explaining the matrix operation shown in FIG.
FIG. 22 is an internal configuration diagram of one 2-bit input RAC in FIG. 21.

[Explanation of symbols]

 Reference Signs List 10 input buffer 11 constant multiplication circuit 12 distribution operation circuit (DA circuit) 13 synthesis operation circuit (RA circuit) 71, 72, 81, 82, 91, 92 ROM 73, 83, 93 3-input adder / subtractor 74, 84, 94 shifter 75, 85, 95 Accumulation registers 101 to 104, 302 to 304 Coefficient memories 105 to 108, 306 to 308 Multipliers 109 to 116, 310 to 317 Accumulators 117, 3188 8-input selectors 2014 4-input selectors 202 2's complement Device 203 adder 204 accumulation register 205 buffer register 212 one's complementer 301 input register 305 two-input selector 309 temporary register 400-407 register 410,411,500,501 input register 412,510 two-input selector 413,503 multiplier 414,41 , 504, 505 Temporary register 416, 417, 506, 507 Buffer register 420-425, 700-705 Shift register 426-433 6-bit input RAC 434-441, 714-721 Buffer register 442 8-input selector 450 3-input adder / subtractor 502 2-input adder / subtractor 511 2-input adder 706-709 4-bit input RAC 710-713 2-bit input RAC 722,723 4-input selector 724 2-input adder / subtractor

────────────────────────────────────────────────── ─── Continued on the front page (58) Fields surveyed (Int. Cl. ⁶ , DB name) G06F 17/14 G16T 1/00 H03M 7/30 H04N 1/41 JICST file (JOIS)

Claims (20)

(57) [Claims] 1. An orthogonal transformation processor for performing orthogonal transformation processing on input data composed of 2 ^{n + 1} (n is an integer of 2 or more) elements, wherein 2 ^{n + 1} × 2 n ^{+ 1} pieces of 2 ⁿ × 2 ^{n + 1} coefficients of the coefficient of each of the absolute values respectively 2
first to second ⁿ coefficient memories for storing ^{n + 1} pieces each, one element of the input data and the first to second
and from the corresponding first to perform each one and the multiplication of 2 ^{n + 1} pieces of storing coefficients of the coefficient memory of the 2 ⁿ multipliers of the coefficient memory of ^n, the orthogonal transform matrix To perform accumulation using the results of the first to second ⁿ multipliers, respectively, while restoring the sign of the coefficient of the orthogonal transformation matrix so as to obtain the corresponding 2 ^{n + 1} inner products in parallel. from the first and the 2 ^{n + 1} of the accumulator, 2 for sequentially selecting outputs as an element of the output data of said orthogonal transform processor results first from the 2 ^{n + 1} accumulator ^{n +} An orthogonal transformation processor comprising a ^one- input selector. 2. The orthogonal transform processor according to claim 1, wherein n is 2. 3. The orthogonal transform processor according to claim 2, wherein each of the first to eighth accumulators includes a result itself of one of the first to fourth multipliers. A two's complementer for selecting and outputting any of the two's complements of the result, an adder for executing an addition of an output of the two's complementer and an accumulation result, and the accumulation result An accumulation register for holding and outputting the result of the adder as an intermediate value of the accumulation result, using 0 as an initial value of the accumulation result, and a buffer register for holding and outputting the output of the accumulation register. An orthogonal transformation processor characterized in that: 4. The orthogonal transform processor according to claim 3, wherein each of said first to eighth accumulators comprises one of said first to fourth accumulators.
A four-input selector for selecting and outputting the result of one of the multipliers as an input to the two's complementer. 5. The orthogonal transform processor according to claim 2, wherein each of the first to eighth accumulators includes a result itself of one of the first to fourth multipliers. A one's complement for selecting and outputting one of the one's complement of the result, an adder for executing an addition of the output of the one's complement and the accumulation result, and the accumulation result An accumulation register for holding and outputting the result of the adder as an intermediate value of the accumulation result, and a buffer register for holding and outputting the output of the accumulation register. An orthogonal transformation processor characterized in that: 6. The orthogonal transform processor according to claim 5, wherein each of said first to eighth accumulators comprises said first to fourth accumulators.
A four-input selector for selecting and outputting a result of one of the multipliers as an input of the one's complementer. 7. An orthogonal transformation processor for performing orthogonal transformation processing on input data composed of 2 ^{n + 1} (n is an integer of 2 or more) elements, wherein 2 ^{n + 1} × of 2 n ^{+ 1} coefficients ^{(2 n -1) × 2 n} + 1 coefficients of each of the absolute value from the first for storing each 2 ^{n + 1} or each of the first (2 ⁿ -
1) a coefficient memory, an input register for holding and outputting one element of the input data supplied as an input, and a two-input selector for selecting and outputting one of an input and an output of the input register. And the output of the two-input selector and two of the first coefficient memory
a first multiplier for performing multiplication with one of ^{n + 1} storage coefficients; an output of the input register; and a second to (2 ⁿ -1)
Second to (2 ⁿ -1) multipliers for respectively performing multiplication with one of 2 ^{n +1} storage coefficients of a corresponding coefficient memory of the coefficient memories of A temporary register for holding and outputting the result of the multiplier of 1, and ^{2n + 1} inner products corresponding to the orthogonal transformation matrix are obtained in parallel while restoring the sign of the coefficient of the orthogonal transformation matrix. A first to a second ( ^{n + 1) -th} accumulator for performing an accumulation using a result of the first to a (2 ⁿ -1) ^-th multiplier and an output of the temporary register, respectively; orthogonal transform processor, characterized in that a 2 ^{n + 1} input selector for sequentially selecting outputs the result of the 2 ^{n + 1} of the accumulator as an element of the output data of said orthogonal transform processor from. 8. The orthogonal transform processor according to claim 7, wherein n is 2. 9. The orthogonal transform processor according to claim 8, wherein each of said first to eighth accumulators comprises: a result of said first to third multipliers and an output of said temporary register. A four-input selector for selecting and outputting one of the outputs, an output itself of the four-input selector, a two's complementer for selectively outputting one of the two's complement of the output, and a two's complementer. An adder for performing addition of the output and the accumulation result; and for preliminarily holding 0 as the initial value of the accumulation result, and holding and outputting the result of the adder as an intermediate value of the accumulation result. An accumulation register, and a buffer register for holding and outputting an output of the accumulation register. 10. The orthogonal transform processor according to claim 8, wherein each of said first to eighth accumulators comprises: a first one of said first to third multipliers; A four-input selector for selecting and outputting one of the outputs, an output itself of the four-input selector, a one's complementer for selectively outputting one of the one's complement of the output, and a one's complementer An adder for performing the addition of the output and the accumulation result; anda pre-holding a constant initial value of the accumulation result, and holding and outputting the result of the adder as an intermediate value of the accumulation result. An orthogonal transformation processor comprising: an accumulation register; and a buffer register for holding and outputting an output of the accumulation register. 11. An orthogonal transformation processor for performing orthogonal transformation processing on input data composed of 2 ^{n + 1} (n is an integer of 2 or more) elements, wherein 2 ^{n + 1} consecutive input data are provided. An input buffer for collectively holding and outputting the elements of the above, and a ^{first of the} 2 ^{n + 1} elements from the input buffer.
Input the 2nd element and the (2 ⁿ +1) th element
A constant multiplier circuit for parallel outputting pieces of constant multiplication result, the input from the buffer of the other (2 n ^{+ 1} -2) by entering the number of elements, 2 ^{n + 1} pieces of which corresponds to the orthogonal transform matrix A distribution operation circuit for sequentially outputting partial inner products; and a synthesis operation of two outputs of the constant multiplication circuit and an output of the distribution operation circuit so as to obtain an element of output data of the orthogonal transformation processor. An orthogonal transformation processor, comprising: 12. The orthogonal transform processor according to claim 11, wherein n is 2. 13. The orthogonal transform processor according to claim 12, wherein said input buffer includes eight registers for holding and outputting each of eight consecutive elements of said input data. Orthogonal transform processor. 14. The orthogonal transformation processor according to claim 12, wherein said constant multiplication circuit holds and outputs a first element of eight consecutive elements of said input data. A second input register for holding and outputting a fifth element of eight consecutive elements of the input data; an output of the first input register and an output of the second input register A two-input selector for sequentially selecting and outputting: a first constant multiplication of an output of the first input register by using an output of the two-input selector; and a second constant of the second input register A multiplier for sequentially executing multiplication, a first temporary register for holding and outputting the result of the first constant multiplication, and a second temporary register for holding and outputting the result of the second constant multiplication. A temporary register; A first buffer register for holding and outputting the output of the first temporary register; and a second buffer register for holding and outputting the output of the second temporary register. A three-input adder / subtractor for performing addition / subtraction using the output of the first buffer register and the output of the distribution operation circuit as addition inputs and using the output of the second buffer register as an addition / subtraction input, respectively. An orthogonal transformation processor characterized by the above-mentioned. 15. The orthogonal transformation processor according to claim 12, wherein said constant multiplication circuit holds and outputs a first element of eight consecutive elements of said input data. A second input register for holding and outputting a fifth element of eight consecutive elements of the input data; an output of the first input register and an output of the second input register A two-input adder / subtracter for sequentially executing addition and subtraction with the first input, a first constant multiplication of the addition result of the two-input addition / subtraction, and a second constant multiplication of the subtraction result of the two-input addition / subtraction. A multiplier for executing; a first temporary register for holding and outputting the result of the first constant multiplication; a second temporary register for holding and outputting the result of the second constant multiplication; The first temporary cash register A first buffer register for holding and outputting the output of the second temporary register; and a second buffer register for holding and outputting the output of the second temporary register. A two-input selector for selecting and outputting one of the outputs of the second buffer register; and a two-input adder for executing an addition of the output of the two-input selector and the output of the distribution operation circuit. An orthogonal transformation processor characterized by the above-mentioned. 16. The orthogonal transformation processor according to claim 12, wherein said distribution operation circuit comprises a second, a third, a fourth, a sixth, a seventh and a seventh one of eight consecutive elements of said input data. The eighth element is retained, and the least significant bit of each of the six elements is collected into a first bit slice word, and the bit one digit higher than the least significant bit of each of the six elements is collected to form a second bit slice word. Six shift registers for sequentially shifting out the least significant two bits of each of the six elements so as to form a bit slice word, and eight partial dot products corresponding to the orthogonal transformation matrix are obtained in parallel. 8 pieces of 6-bit input RACs for respectively executing a multiply-accumulate operation based on the first and second bit slice words; Buff Registers and, an orthogonal transform processor, characterized in that an 8-input selector for sequentially selecting an output of the eight buffer registers. 17. The orthogonal transform processor according to claim 16, wherein each of said eight 6-bit input RACs is a vector based on said orthogonal transform matrix such that said first bit slice word is indexed as an address. A first ROM for storing a partial sum of an inner product, and a second ROM for storing a partial sum of a vector inner product based on the orthogonal transformation matrix so as to be indexed using the second bit slice word as an address. And a partial sum indexed from the first ROM as a first addition input, a partial sum indexed from the second ROM as an addition / subtraction input, and an accumulation result as a second addition input. A three-input adder / subtracter for performing addition / subtraction, a shifter for shifting the result of the three-input adder / subtractor to the left, and holding in advance 0 as an initial value of the accumulation result; And an accumulation register for holding and outputting an output of the shifter as an intermediate value of the accumulation result. 18. The orthogonal transformation processor according to claim 12, wherein the distribution operation circuit holds second, fourth, sixth, and eighth elements of eight consecutive elements of the input data. And the least significant bits of each of the four elements are collected into a first bit slice word, and the bits one digit higher than the least significant bit of each of the four elements are collected into a second bit slice word. And four shift registers for sequentially shifting out the least significant two bits of each of the four elements, and holding third and seventh elements of eight consecutive elements of the input data. And collecting the least significant bits of each of the two elements to form a third bit slice word,
Two shift registers for shifting out the least significant two bits of each of the two elements one after the other so as to collect bits one digit higher than the least significant bit of each of the elements into a fourth bit slice word And four 4-bit input RACs for respectively performing a product-sum operation based on the first and second bit slice words so as to obtain four partial inner products corresponding to the orthogonal transformation matrix in parallel. Four 2-bit input RACs for respectively performing a product-sum operation based on the third and fourth bit slice words so as to obtain four partial inner products corresponding to the orthogonal transformation matrix in parallel; First to fourth buffer registers for holding and outputting the results of the four 4-bit input RACs; and fifth to fifth buffer registers for holding and outputting the results of the four 2-bit input RACs 8 buffer registers, a first 4-input selector for sequentially selecting and outputting the outputs of the first to fourth buffer registers, and a first 4-input selector for sequentially selecting and outputting the outputs of the fifth to eighth buffer registers. A second four-input selector; and a two-input adder / subtractor for performing addition / subtraction using the output of the first four-input selector as an addition / subtraction input and the output of the second four-input selector as an addition input. An orthogonal transformation processor characterized in that: 19. The orthogonal transform processor of claim 18, wherein each of said four 4-bit inputs RAC is a vector based on said orthogonal transform matrix such that said first bit slice word is indexed as an address. A first ROM for storing a partial sum of an inner product, and a second ROM for storing a partial sum of a vector inner product based on the orthogonal transformation matrix so as to be indexed using the second bit slice word as an address. And a partial sum indexed from the first ROM as a first addition input, a partial sum indexed from the second ROM as an addition / subtraction input, and an accumulation result as a second addition input. A three-input adder / subtracter for performing addition / subtraction, a shifter for shifting the result of the three-input adder / subtractor to the left, and holding in advance 0 as an initial value of the accumulation result; And an accumulation register for holding and outputting an output of the shifter as an intermediate value of the accumulation result. 20. The orthogonal transform processor of claim 18, wherein each of the four 2-bit inputs RAC is a vector based on the orthogonal transform matrix such that the third bit slice word is indexed as an address. A first ROM for storing a partial sum of an inner product, and a second ROM for storing a partial sum of a vector inner product based on the orthogonal transformation matrix so as to be indexed using the fourth bit slice word as an address. And a partial sum indexed from the first ROM as a first addition input, a partial sum indexed from the second ROM as an addition / subtraction input, and an accumulation result as a second addition input. A three-input adder / subtracter for performing addition / subtraction, a shifter for shifting the result of the three-input adder / subtractor to the left, and holding in advance 0 as an initial value of the accumulation result; And an accumulation register for holding and outputting an output of the shifter as an intermediate value of the accumulation result.